The examples and illustrations in this article suggest that we are just beginning to grapple with the many opportunities and challenges associated with multicore processors. Our initial steps have been limited by technology to modest changes in the overall balance of systems, but technology trends make it clear that the flexibility provided by future process technologies will present us with an abundance of opportunities to design microprocessor-based systems with radically different power, performance, and cost characteristics. The tension between maintaining high volumes by selling standardized products and increasing performance, performance/watt and performance/price by creating multiple differentiated products will be a major challenge for the computing industry. Even if we try to maintain a modest number of "fast" cores, process technology will enable us to provide more cores than users are currently capable of using effectively. This will challenge industry, academia, and computer users to work together to develop new methods to enable the use of multiple cores for "typical" applications, exploiting the physical locality of on-chip communications to enable more tightly coupled parallelism than has previously been widely adopted.
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2 Merriam-Webster Online: www.m-w.com/dictionary/balance
3 Merriam-Webster Online: www.m-w.com/dictionary/optimization
4 All data is freely available at www.spec.org/cpu2000/
5 McCalpin, J. “Composite Metrics for System Throughput in HPC”, unpublished work presented at SuperComputing2003, www.cs.virginia.edu/~mccalpin/SimpleCompositeMetrics2003-12-08.pdf
6 McCalpin, J. “Composite Metrics for System Throughput in HPC”, presented at the HPC Challenge Benchmark panel discussion at SuperComputing2003, www.cs.virginia.edu/~mccalpin/CompositeMetricsPanel2003-11-20b.pdf
7 McCalpin, J. “Using Timings for the SWIM Benchmark from the SPEC CPU Suites to Estimate Sustainable Memory Bandwidth”, revised to 2002-12-02, www.cs.virginia.edu/stream/SWIM-BW.html
8 Farkas, K. I., Jouppi, N. P., Chow, P.. "Register file design considerations in dynamically scheduled processors", 1996. Proceedings: Second International Symposium on High-Performance Computer Architecture, pp.40-51, 3-7 Feb 1996.
9 Results published at www.spec.org/ with IBM e326 2-socket servers running single-core and dual-core parts at 2.2 GHz, all running Suse Linux 9.0 and version 2.1 of the PathScale EKOPath compiler suite.
10 All revenue data here is based on an AMD analysis of the IDC 2Q2006 world-wide server tracker report. www.idc.com/
11 Li, Y., et al. ”CMP Design Space Exploration Subject to Physical Constraints”, The Twelfth International Symposium on High-Performance Computer Architecture, 2006, 11-15 Feb, 2006, pp 17-28. www.cs.virginia.edu/papers/hpca06.pdf