CTWatch
February 2007
The Promise and Perils of the Coming Multicore Revolution and Its Impact
John McCalpin, Advanced Micro Devices, Inc.
Chuck Moore, Advanced Micro Devices, Inc.
Phil Hester, Advanced Micro Devices, Inc.

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2. Initial Development of Multicore Chips

The initial development of multicore processors owed much to the continued shrinking of CMOS lithography. It has long been known that increasing the size/width of a CPU core quickly reaches the realm of diminishing returns.8 So as the size of a state-of-the-art core shrinks to a small fraction of an economically viable die size, the options are:

  • Produce a smaller chip
  • Add lots of cache
  • Add more cores

The option of adding more memory bandwidth typically adds significant cost outside of the processor chip, including revised motherboards (perhaps requiring more layers), additional DIMMs, etc. Because of these additional costs and the burden of socket incompatibility, the option of adding more memory bandwidth will be considered separately from options that involve only processor die size.

Figures 1 and 2 show some of the relative performance and performance/price metrics for these three options, assuming a 30% lithography shrink (i.e., 50% area shrink) which also allows a 17% frequency increase for the single core, but requires a 17% frequency decrease for the dual-core (to remain in the same power envelope). Note that the SPECfp_rate2000 benchmark consists of 14 individual tests that are modeled independently. These are summarized as a minimum speedup, median speedup, geometric mean speedup, and maximum speedup. For the dual-core processor option, both the single-core (uni) and dual-core (mp) speedups are estimated.

Figure 1

Figure 1: Estimated Relative SPECfp_rate2000 performance for three system configurations (based on the analytical model described in Section 1), assuming a 30% lithography shrink (50% area reduction) with a corresponding 17% frequency boost for the single-core chip and a 17% frequency reduction for the dual-core chip. The Smaller Chip is ½ the size of the reference chip, while the Bigger Cache and 2 Core versions are scaled to be the same size and have the same power requirements as the reference chip. Note that the Max Speedup for the Bigger Cache case is +156%, but is truncated by the scale here.

Figure 2

Figure 2: Estimated Relative SPECfp_rate2000/price for three system configurations (based on the analytical model described in Section 1), assuming a 30% lithography shrink (50% area shrink) with a corresponding 17% frequency boost for the single-core chip and a 17% frequency reduction for the dual-core chip.

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Reference this article
McCalpin, J., Moore, C., Hester, P. "The Role of Multicore Processors in the Evolution of General-Purpose Computing," CTWatch Quarterly, Volume 3, Number 1, February 2007. http://www.ctwatch.org/quarterly/articles/2007/02/the-role-of-multicore-processors-in-the-evolution-of-general-purpose-computing/

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