117{
118 unsigned int i, npmcs = 0, npmds = 0, base_pmc = 0;
122 uint64_t Pevents = 0, Cevents = 0, Mevents = 0;
123
124 DPRINT (
"dispatching event info to the PMCs and PMDs\n");
125
126
127
128
129
130
131
133 int j;
139 }
140 }
141 }
142
143
144
146 DPRINT (
"return: event count is 0\n");
151 }
152
153 memset (Pused, 0, sizeof(Pused));
154 memset (Cused, 0, sizeof(Cused));
155 memset (Mused, 0, sizeof(Mused));
156
157
158
160 unsigned int code, chip, ctr, ev, chipno;
162
163
164
165
166
167
173
174 DPRINT (
"%3d: code %3d chip %1d ctr %2d ev %1d chipno %2d\n", code,
i, chip, ctr, ev, chipno);
175
176
177
181 }
182
183
184
186 DPRINT (
"too many masks for event\n");
188 }
189
190
191
192
193
200 } else {
201 DPRINT (
"return: invalid chip\n");
203 }
204
205
206
208 DPRINT (
"return: ctr conflict\n");
211#if (CRAYX2_NO_REDUNDANT != 0)
212 DPRINT (
"return: ctr redundant\n");
214#else
215 DPRINT (
"warning: ctr redundant\n");
216#endif
217 }
218
219
220
225 npmds++;
226 }
228
230 DPRINT (
"P event mask %#16lx\n", Pevents);
231 DPRINT (
"C event mask %#16lx\n", Cevents);
232 DPRINT (
"M event mask %#16lx\n", Mevents);
236 }
237 }
238
239
240
241
243 uint64_t Pctrl = PFM_CPU_START;
244 uint64_t Pen = PFM_ENABLE_RW;
245
247 Pen |= PFM_ENABLE_KERNEL;
248 }
250 Pen |= PFM_ENABLE_EXL;
251 }
253 Pen |= PFM_ENABLE_USER;
254 }
255
256
257
259
264 npmcs++;
265
270 npmcs++;
271
276 npmcs++;
277 }
279 uint64_t Cctrl = PFM_CACHE_START;
280 uint64_t Cen = PFM_ENABLE_RW;
281
282
283
285
290 npmcs++;
291
296 npmcs++;
297
302 npmcs++;
303 }
305 uint64_t Mctrl = PFM_MEM_START;
306 uint64_t Men = PFM_ENABLE_RW;
307
308
309
311
316 npmcs++;
317
322 npmcs++;
323
328 npmcs++;
329 }
331
336 }
337 }
339}
static pme_crayx2_entry_t crayx2_pe[]
#define PFMLIB_ERR_EVTINCOMP
#define PFMLIB_ERR_TOOMANY
#define PFMLIB_ERR_EVTMANY
static counter_use_t pfm_crayx2_counter_use(unsigned int ctr, unsigned int event, uint32_t *used, uint64_t *evmsk)
static int pfm_crayx2_chip_use(uint32_t used[], unsigned int n)
#define PMU_CRAYX2_NUM_COUNTERS
#define PMU_CRAYX2_CPU_PMC_BASE
#define PMU_CRAYX2_CACHE_PMC_BASE
#define PMU_CRAYX2_MEMORY_PMC_BASE
#define PME_CRAYX2_CHIP_MEMORY
#define PME_CRAYX2_CACHE_CHIPS
#define PME_CRAYX2_CPU_CHIPS
#define PME_CRAYX2_MEMORY_CHIPS
#define PME_CRAYX2_CHIP_CPU
#define PME_CRAYX2_CHIP_CACHE
unsigned int unit_masks[PFMLIB_MAX_MASKS_PER_EVENT]
pfmlib_reg_t pfp_pmds[PFMLIB_MAX_PMDS]
pfmlib_reg_t pfp_pmcs[PFMLIB_MAX_PMCS]
unsigned int pfp_pmc_count
unsigned int pfp_pmd_count
unsigned long long reg_value
unsigned long reg_alt_addr
unsigned long long reg_addr