PAPI 7.1.0.0
Loading...
Searching...
No Matches
pfmlib_crayx2.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2007 Cray Inc.
3 * Contributed by Steve Kaufmann <sbk@cray.com> based on code from
4 * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P.
5 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
11 * of the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
18 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
19 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
20 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
21 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
22 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __PFMLIB_CRAYX2_H__
26#define __PFMLIB_CRAYX2_H__ 1
27/*
28 * Allows <asm/perfmon.h> to be included on its own.
29 */
30#define PFM_MAX_HW_PMCS 12
31#define PFM_MAX_HW_PMDS 512
32
33#include <asm/perfmon.h>
34#include <sys/types.h>
35
36/* Priviledge level mask for Cray-X2:
37 *
38 * PFM_PLM0 = Kernel
39 * PFM_PLM1 = Kernel
40 * PFM_PLM2 = Exception
41 * PFM_PLM3 = User
42 */
43
44/* The performance control (PMC) registers appear as follows:
45 * PMC0 control for CPU chip
46 * PMC1 events on CPU chip
47 * PMC2 enable for CPU chip
48 * PMC3 control for L2 Cache chip
49 * PMC4 events on L2 Cache chip
50 * PMC5 enable for L2 Cache chip
51 * PMC6 control for Memory chip
52 * PMC7 events on Memory chip
53 * PMC8 enable for Memory chip
54 *
55 * The performance data (PMD) registers appear for
56 * CPU (32), L2 Cache (16), and Memory (28*16) chips contiguously.
57 * There are four events per chip.
58 *
59 * PMD0 P chip, counter 0
60 * ...
61 * PMD31 P chip, counter 31
62 * PMD32 C chip, counter 0
63 * ...
64 * PMD47 C chip, counter 15
65 * PMD48 M chip 0, counter 0
66 * ...
67 * PMD495 M chip 15, counter 27
68 */
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74/* PMC counts
75 */
76#define PMU_CRAYX2_CPU_PMC_COUNT PFM_CPU_PMC_COUNT
77#define PMU_CRAYX2_CACHE_PMC_COUNT PFM_CACHE_PMC_COUNT
78#define PMU_CRAYX2_MEMORY_PMC_COUNT PFM_MEM_PMC_COUNT
79
80/* PMC bases
81 */
82#define PMU_CRAYX2_CPU_PMC_BASE PFM_CPU_PMC
83#define PMU_CRAYX2_CACHE_PMC_BASE PFM_CACHE_PMC
84#define PMU_CRAYX2_MEMORY_PMC_BASE PFM_MEM_PMC
85
86/* PMD counts
87 */
88#define PMU_CRAYX2_CPU_PMD_COUNT PFM_CPU_PMD_COUNT
89#define PMU_CRAYX2_CACHE_PMD_COUNT PFM_CACHE_PMD_COUNT
90#define PMU_CRAYX2_MEMORY_PMD_COUNT PFM_MEM_PMD_COUNT
91
92/* PMD bases
93*/
94#define PMU_CRAYX2_CPU_PMD_BASE PFM_CPU_PMD
95#define PMU_CRAYX2_CACHE_PMD_BASE PFM_CACHE_PMD
96#define PMU_CRAYX2_MEMORY_PMD_BASE PFM_MEM_PMD
97
98/* Total number of PMCs and PMDs
99 */
100#define PMU_CRAYX2_PMC_COUNT PFM_PMC_COUNT
101#define PMU_CRAYX2_PMD_COUNT PFM_PMD_COUNT
102#define PMU_CRAYX2_NUM_COUNTERS PFM_PMD_COUNT
103
104/* Counter width (can also be acquired via /sys/kernel/perfmon)
105 */
106#define PMU_CRAYX2_COUNTER_WIDTH 63
107
108/* PMU name (can also be acquired via /sys/kernel/perfmon)
109 */
110#define PMU_CRAYX2_NAME "Cray X2"
111
112#ifdef __cplusplus
113}
114#endif /* extern C */
115
116#endif /* __PFMLIB_CRAYX2_H__ */