PAPI 7.1.0.0
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crayx2_events.h
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1/*
2 * Copyright (c) 2007 Cray Inc.
3 * Contributed by Steve Kaufmann <sbk@cray.com> based on code from
4 * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P.
5 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
11 * of the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
18 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
19 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
20 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
21 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
22 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __CRAYX2_EVENTS_H__
26#define __CRAYX2_EVENTS_H__ 1
27
28#include "pfmlib_crayx2_priv.h"
29
30/*
31 *****************************************************************
32 ******* THIS TABLE IS GENERATED AUTOMATICALLY
33 ******* MODIFICATIONS REQUIRED FOR THE EVENT NAMES
34 ******* OR EVENT DESCRIPTIONS SHOULD BE MADE TO
35 ******* THE TEXT FILE AND THE TABLE REGENERATED
36 ******* Sat Nov 10 14:40:30 CST 2007
37 *****************************************************************
38 */
39
40static pme_crayx2_entry_t crayx2_pe[ ] =
41{
42 /* P Counter 0 Event 0 */
43 {
44 .pme_name = "CYCLES",
45 .pme_desc = "Cycles.",
46 .pme_code = 0,
47 .pme_flags = 0x0,
48 .pme_numasks = 0,
49 .pme_chip = PME_CRAYX2_CHIP_CPU,
50 .pme_ctr = 0,
51 .pme_event = 0,
52 .pme_chipno = 0,
53 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
54 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
55 .pme_nchips = PME_CRAYX2_CPU_CHIPS
56 },
57 /* P Counter 0 Event 1 */
58 {
59 .pme_name = "CYCLES",
60 .pme_desc = "Cycles.",
61 .pme_code = 1,
62 .pme_flags = 0x0,
63 .pme_numasks = 0,
64 .pme_chip = PME_CRAYX2_CHIP_CPU,
65 .pme_ctr = 0,
66 .pme_event = 1,
67 .pme_chipno = 0,
68 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
69 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
70 .pme_nchips = PME_CRAYX2_CPU_CHIPS
71 },
72 /* P Counter 0 Event 2 */
73 {
74 .pme_name = "CYCLES",
75 .pme_desc = "Cycles.",
76 .pme_code = 2,
77 .pme_flags = 0x0,
78 .pme_numasks = 0,
79 .pme_chip = PME_CRAYX2_CHIP_CPU,
80 .pme_ctr = 0,
81 .pme_event = 2,
82 .pme_chipno = 0,
83 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
84 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
85 .pme_nchips = PME_CRAYX2_CPU_CHIPS
86 },
87 /* P Counter 0 Event 3 */
88 {
89 .pme_name = "CYCLES",
90 .pme_desc = "Cycles.",
91 .pme_code = 3,
92 .pme_flags = 0x0,
93 .pme_numasks = 0,
94 .pme_chip = PME_CRAYX2_CHIP_CPU,
95 .pme_ctr = 0,
96 .pme_event = 3,
97 .pme_chipno = 0,
98 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
99 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
100 .pme_nchips = PME_CRAYX2_CPU_CHIPS
101 },
102 /* P Counter 1 Event 0 */
103 {
104 .pme_name = "INST_GRAD",
105 .pme_desc = "Number of instructions graduated.",
106 .pme_code = 4,
107 .pme_flags = 0x0,
108 .pme_numasks = 0,
109 .pme_chip = PME_CRAYX2_CHIP_CPU,
110 .pme_ctr = 1,
111 .pme_event = 0,
112 .pme_chipno = 0,
113 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
114 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
115 .pme_nchips = PME_CRAYX2_CPU_CHIPS
116 },
117 /* P Counter 1 Event 1 */
118 {
119 .pme_name = "INST_GRAD",
120 .pme_desc = "Number of instructions graduated.",
121 .pme_code = 5,
122 .pme_flags = 0x0,
123 .pme_numasks = 0,
124 .pme_chip = PME_CRAYX2_CHIP_CPU,
125 .pme_ctr = 1,
126 .pme_event = 1,
127 .pme_chipno = 0,
128 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
129 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
130 .pme_nchips = PME_CRAYX2_CPU_CHIPS
131 },
132 /* P Counter 1 Event 2 */
133 {
134 .pme_name = "INST_GRAD",
135 .pme_desc = "Number of instructions graduated.",
136 .pme_code = 6,
137 .pme_flags = 0x0,
138 .pme_numasks = 0,
139 .pme_chip = PME_CRAYX2_CHIP_CPU,
140 .pme_ctr = 1,
141 .pme_event = 2,
142 .pme_chipno = 0,
143 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
144 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
145 .pme_nchips = PME_CRAYX2_CPU_CHIPS
146 },
147 /* P Counter 1 Event 3 */
148 {
149 .pme_name = "INST_GRAD",
150 .pme_desc = "Number of instructions graduated.",
151 .pme_code = 7,
152 .pme_flags = 0x0,
153 .pme_numasks = 0,
154 .pme_chip = PME_CRAYX2_CHIP_CPU,
155 .pme_ctr = 1,
156 .pme_event = 3,
157 .pme_chipno = 0,
158 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
159 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
160 .pme_nchips = PME_CRAYX2_CPU_CHIPS
161 },
162 /* P Counter 2 Event 0 */
163 {
164 .pme_name = "INST_DISPATCH",
165 .pme_desc = "Number of instructions dispatched.",
166 .pme_code = 8,
167 .pme_flags = 0x0,
168 .pme_numasks = 0,
169 .pme_chip = PME_CRAYX2_CHIP_CPU,
170 .pme_ctr = 2,
171 .pme_event = 0,
172 .pme_chipno = 0,
173 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
174 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
175 .pme_nchips = PME_CRAYX2_CPU_CHIPS
176 },
177 /* P Counter 2 Event 1 */
178 {
179 .pme_name = "ITLB_MISS",
180 .pme_desc = "Number of Instruction TLB misses.",
181 .pme_code = 9,
182 .pme_flags = 0x0,
183 .pme_numasks = 0,
184 .pme_chip = PME_CRAYX2_CHIP_CPU,
185 .pme_ctr = 2,
186 .pme_event = 1,
187 .pme_chipno = 0,
188 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
189 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
190 .pme_nchips = PME_CRAYX2_CPU_CHIPS
191 },
192 /* P Counter 2 Event 2 */
193 {
194 .pme_name = "JB_CORRECT",
195 .pme_desc = "Number of jumps and branches predicted correctly.",
196 .pme_code = 10,
197 .pme_flags = 0x0,
198 .pme_numasks = 0,
199 .pme_chip = PME_CRAYX2_CHIP_CPU,
200 .pme_ctr = 2,
201 .pme_event = 2,
202 .pme_chipno = 0,
203 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
204 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
205 .pme_nchips = PME_CRAYX2_CPU_CHIPS
206 },
207 /* P Counter 2 Event 3 */
208 {
209 .pme_name = "STALL_VU_FUG1",
210 .pme_desc = "CPs VU stalled waiting for FUG 1.",
211 .pme_code = 11,
212 .pme_flags = 0x0,
213 .pme_numasks = 0,
214 .pme_chip = PME_CRAYX2_CHIP_CPU,
215 .pme_ctr = 2,
216 .pme_event = 3,
217 .pme_chipno = 0,
218 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
219 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
220 .pme_nchips = PME_CRAYX2_CPU_CHIPS
221 },
222 /* P Counter 3 Event 0 */
223 {
224 .pme_name = "INST_SYNCS",
225 .pme_desc = "Number of synchronization instructions graduated g=02.",
226 .pme_code = 12,
227 .pme_flags = 0x0,
228 .pme_numasks = 0,
229 .pme_chip = PME_CRAYX2_CHIP_CPU,
230 .pme_ctr = 3,
231 .pme_event = 0,
232 .pme_chipno = 0,
233 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
234 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
235 .pme_nchips = PME_CRAYX2_CPU_CHIPS
236 },
237 /* P Counter 3 Event 1 */
238 {
239 .pme_name = "INST_GSYNCS",
240 .pme_desc = "Number of Gsync instructions graduated g=02 & f=0-3.",
241 .pme_code = 13,
242 .pme_flags = 0x0,
243 .pme_numasks = 0,
244 .pme_chip = PME_CRAYX2_CHIP_CPU,
245 .pme_ctr = 3,
246 .pme_event = 1,
247 .pme_chipno = 0,
248 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
249 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
250 .pme_nchips = PME_CRAYX2_CPU_CHIPS
251 },
252 /* P Counter 3 Event 2 */
253 {
254 .pme_name = "STALL_DU_ICACHE",
255 .pme_desc = "CPs dispatch stalled waiting for instruction from Icache.",
256 .pme_code = 14,
257 .pme_flags = 0x0,
258 .pme_numasks = 0,
259 .pme_chip = PME_CRAYX2_CHIP_CPU,
260 .pme_ctr = 3,
261 .pme_event = 2,
262 .pme_chipno = 0,
263 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
264 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
265 .pme_nchips = PME_CRAYX2_CPU_CHIPS
266 },
267 /* P Counter 3 Event 3 */
268 {
269 .pme_name = "STALL_VU_FUG2",
270 .pme_desc = "CPs VU stalled waiting for FUG 2.",
271 .pme_code = 15,
272 .pme_flags = 0x0,
273 .pme_numasks = 0,
274 .pme_chip = PME_CRAYX2_CHIP_CPU,
275 .pme_ctr = 3,
276 .pme_event = 3,
277 .pme_chipno = 0,
278 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
279 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
280 .pme_nchips = PME_CRAYX2_CPU_CHIPS
281 },
282 /* P Counter 4 Event 0 */
283 {
284 .pme_name = "INST_AMO",
285 .pme_desc = "Number of AMO instructions graduated g=04.",
286 .pme_code = 16,
287 .pme_flags = 0x0,
288 .pme_numasks = 0,
289 .pme_chip = PME_CRAYX2_CHIP_CPU,
290 .pme_ctr = 4,
291 .pme_event = 0,
292 .pme_chipno = 0,
293 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
294 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
295 .pme_nchips = PME_CRAYX2_CPU_CHIPS
296 },
297 /* P Counter 4 Event 1 */
298 {
299 .pme_name = "ICACHE_FETCH",
300 .pme_desc = "Number of instruction fetch requests to memory.",
301 .pme_code = 17,
302 .pme_flags = 0x0,
303 .pme_numasks = 0,
304 .pme_chip = PME_CRAYX2_CHIP_CPU,
305 .pme_ctr = 4,
306 .pme_event = 1,
307 .pme_chipno = 0,
308 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
309 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
310 .pme_nchips = PME_CRAYX2_CPU_CHIPS
311 },
312 /* P Counter 4 Event 2 */
313 {
314 .pme_name = "STALL_DU_BRANCH_PRED",
315 .pme_desc = "CPs Dispatch stalled waiting for branch prediction register.",
316 .pme_code = 18,
317 .pme_flags = 0x0,
318 .pme_numasks = 0,
319 .pme_chip = PME_CRAYX2_CHIP_CPU,
320 .pme_ctr = 4,
321 .pme_event = 2,
322 .pme_chipno = 0,
323 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
324 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
325 .pme_nchips = PME_CRAYX2_CPU_CHIPS
326 },
327 /* P Counter 4 Event 3 */
328 {
329 .pme_name = "STALL_VU_FUG3",
330 .pme_desc = "CPs VU stalled waiting for FUG 3.",
331 .pme_code = 19,
332 .pme_flags = 0x0,
333 .pme_numasks = 0,
334 .pme_chip = PME_CRAYX2_CHIP_CPU,
335 .pme_ctr = 4,
336 .pme_event = 3,
337 .pme_chipno = 0,
338 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
339 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
340 .pme_nchips = PME_CRAYX2_CPU_CHIPS
341 },
342 /* P Counter 5 Event 0 */
343 {
344 .pme_name = "INST_A",
345 .pme_desc = "Number of A register instructions graduated g=05,40,42,43.",
346 .pme_code = 20,
347 .pme_flags = 0x0,
348 .pme_numasks = 0,
349 .pme_chip = PME_CRAYX2_CHIP_CPU,
350 .pme_ctr = 5,
351 .pme_event = 0,
352 .pme_chipno = 0,
353 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
354 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
355 .pme_nchips = PME_CRAYX2_CPU_CHIPS
356 },
357 /* P Counter 5 Event 1 */
358 {
359 .pme_name = "ICACHE_HIT",
360 .pme_desc = "Number of Icache hits.",
361 .pme_code = 21,
362 .pme_flags = 0x0,
363 .pme_numasks = 0,
364 .pme_chip = PME_CRAYX2_CHIP_CPU,
365 .pme_ctr = 5,
366 .pme_event = 1,
367 .pme_chipno = 0,
368 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
369 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
370 .pme_nchips = PME_CRAYX2_CPU_CHIPS
371 },
372 /* P Counter 5 Event 2 */
373 {
374 .pme_name = "STALL_DU_AREG",
375 .pme_desc = "CPs instruction dispatch stalled waiting for free A register.",
376 .pme_code = 22,
377 .pme_flags = 0x0,
378 .pme_numasks = 0,
379 .pme_chip = PME_CRAYX2_CHIP_CPU,
380 .pme_ctr = 5,
381 .pme_event = 2,
382 .pme_chipno = 0,
383 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
384 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
385 .pme_nchips = PME_CRAYX2_CPU_CHIPS
386 },
387 /* P Counter 5 Event 3 */
388 {
389 .pme_name = "STALL_VU",
390 .pme_desc = "CPs VU is stalled with a valid instruction.",
391 .pme_code = 23,
392 .pme_flags = 0x0,
393 .pme_numasks = 0,
394 .pme_chip = PME_CRAYX2_CHIP_CPU,
395 .pme_ctr = 5,
396 .pme_event = 3,
397 .pme_chipno = 0,
398 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
399 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
400 .pme_nchips = PME_CRAYX2_CPU_CHIPS
401 },
402 /* P Counter 6 Event 0 */
403 {
404 .pme_name = "INST_S_INT",
405 .pme_desc = "Number of S register integer instructions graduated g=60,62 & t1=1,63.",
406 .pme_code = 24,
407 .pme_flags = 0x0,
408 .pme_numasks = 0,
409 .pme_chip = PME_CRAYX2_CHIP_CPU,
410 .pme_ctr = 6,
411 .pme_event = 0,
412 .pme_chipno = 0,
413 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
414 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
415 .pme_nchips = PME_CRAYX2_CPU_CHIPS
416 },
417 /* P Counter 6 Event 1 */
418 {
419 .pme_name = "INST_MSYNCS",
420 .pme_desc = "Number of Msync instructions graduated g=02 & f=20-22.",
421 .pme_code = 25,
422 .pme_flags = 0x0,
423 .pme_numasks = 0,
424 .pme_chip = PME_CRAYX2_CHIP_CPU,
425 .pme_ctr = 6,
426 .pme_event = 1,
427 .pme_chipno = 0,
428 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
429 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
430 .pme_nchips = PME_CRAYX2_CPU_CHIPS
431 },
432 /* P Counter 6 Event 2 */
433 {
434 .pme_name = "STALL_DU_ACT_LIST_FULL",
435 .pme_desc = "CPs dispatch stalled waiting for active list entry.",
436 .pme_code = 26,
437 .pme_flags = 0x0,
438 .pme_numasks = 0,
439 .pme_chip = PME_CRAYX2_CHIP_CPU,
440 .pme_ctr = 6,
441 .pme_event = 2,
442 .pme_chipno = 0,
443 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
444 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
445 .pme_nchips = PME_CRAYX2_CPU_CHIPS
446 },
447 /* P Counter 6 Event 3 */
448 {
449 .pme_name = "STALL_VU_NO_INST",
450 .pme_desc = "CPs VU has no valid instruction.",
451 .pme_code = 27,
452 .pme_flags = 0x0,
453 .pme_numasks = 0,
454 .pme_chip = PME_CRAYX2_CHIP_CPU,
455 .pme_ctr = 6,
456 .pme_event = 3,
457 .pme_chipno = 0,
458 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
459 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
460 .pme_nchips = PME_CRAYX2_CPU_CHIPS
461 },
462 /* P Counter 7 Event 0 */
463 {
464 .pme_name = "INST_S_FP",
465 .pme_desc = "Number of S register FP instructions graduated g=62 & t1=0.",
466 .pme_code = 28,
467 .pme_flags = 0x0,
468 .pme_numasks = 0,
469 .pme_chip = PME_CRAYX2_CHIP_CPU,
470 .pme_ctr = 7,
471 .pme_event = 0,
472 .pme_chipno = 0,
473 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
474 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
475 .pme_nchips = PME_CRAYX2_CPU_CHIPS
476 },
477 /* P Counter 7 Event 1 */
478 {
479 .pme_name = "STLB_MISS",
480 .pme_desc = "Number of Scalar TLB misses.",
481 .pme_code = 29,
482 .pme_flags = 0x0,
483 .pme_numasks = 0,
484 .pme_chip = PME_CRAYX2_CHIP_CPU,
485 .pme_ctr = 7,
486 .pme_event = 1,
487 .pme_chipno = 0,
488 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
489 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
490 .pme_nchips = PME_CRAYX2_CPU_CHIPS
491 },
492 /* P Counter 7 Event 2 */
493 {
494 .pme_name = "STALL_DU_SREG",
495 .pme_desc = "CPs instruction dispatch stalled waiting for free S register.",
496 .pme_code = 30,
497 .pme_flags = 0x0,
498 .pme_numasks = 0,
499 .pme_chip = PME_CRAYX2_CHIP_CPU,
500 .pme_ctr = 7,
501 .pme_event = 2,
502 .pme_chipno = 0,
503 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
504 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
505 .pme_nchips = PME_CRAYX2_CPU_CHIPS
506 },
507 /* P Counter 7 Event 3 */
508 {
509 .pme_name = "STALL_VU_VR",
510 .pme_desc = "CPs VU is stalled waiting for busy V Reg.",
511 .pme_code = 31,
512 .pme_flags = 0x0,
513 .pme_numasks = 0,
514 .pme_chip = PME_CRAYX2_CHIP_CPU,
515 .pme_ctr = 7,
516 .pme_event = 3,
517 .pme_chipno = 0,
518 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
519 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
520 .pme_nchips = PME_CRAYX2_CPU_CHIPS
521 },
522 /* P Counter 8 Event 0 */
523 {
524 .pme_name = "INST_MISC",
525 .pme_desc = "Number of Misc. scalar instructions graduated g=00, 01, 03, 06, 34.",
526 .pme_code = 32,
527 .pme_flags = 0x0,
528 .pme_numasks = 0,
529 .pme_chip = PME_CRAYX2_CHIP_CPU,
530 .pme_ctr = 8,
531 .pme_event = 0,
532 .pme_chipno = 0,
533 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
534 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
535 .pme_nchips = PME_CRAYX2_CPU_CHIPS
536 },
537 /* P Counter 8 Event 1 */
538 {
539 .pme_name = "VTLB_MISS",
540 .pme_desc = "Number of vector TLB misses.",
541 .pme_code = 33,
542 .pme_flags = 0x0,
543 .pme_numasks = 0,
544 .pme_chip = PME_CRAYX2_CHIP_CPU,
545 .pme_ctr = 8,
546 .pme_event = 1,
547 .pme_chipno = 0,
548 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
549 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
550 .pme_nchips = PME_CRAYX2_CPU_CHIPS
551 },
552 /* P Counter 8 Event 2 */
553 {
554 .pme_name = "STALL_DU_INST",
555 .pme_desc = "CPs dispatch stalled due to an instruction such as a Gsync or Lsync FP that stops dispatch until it executes.",
556 .pme_code = 34,
557 .pme_flags = 0x0,
558 .pme_numasks = 0,
559 .pme_chip = PME_CRAYX2_CHIP_CPU,
560 .pme_ctr = 8,
561 .pme_event = 2,
562 .pme_chipno = 0,
563 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
564 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
565 .pme_nchips = PME_CRAYX2_CPU_CHIPS
566 },
567 /* P Counter 8 Event 3 */
568 {
569 .pme_name = "STALL_VLSU_NO_INST",
570 .pme_desc = "CPs VLSU has no valid instruction.",
571 .pme_code = 35,
572 .pme_flags = 0x0,
573 .pme_numasks = 0,
574 .pme_chip = PME_CRAYX2_CHIP_CPU,
575 .pme_ctr = 8,
576 .pme_event = 3,
577 .pme_chipno = 0,
578 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
579 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
580 .pme_nchips = PME_CRAYX2_CPU_CHIPS
581 },
582 /* P Counter 9 Event 0 */
583 {
584 .pme_name = "INST_JB",
585 .pme_desc = "Number of Jump and Branch instructions graduated g=50-57, 70-76.",
586 .pme_code = 36,
587 .pme_flags = 0x0,
588 .pme_numasks = 0,
589 .pme_chip = PME_CRAYX2_CHIP_CPU,
590 .pme_ctr = 9,
591 .pme_event = 0,
592 .pme_chipno = 0,
593 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
594 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
595 .pme_nchips = PME_CRAYX2_CPU_CHIPS
596 },
597 /* P Counter 9 Event 1 */
598 {
599 .pme_name = "ICACHE_MISS",
600 .pme_desc = "Number of Icache misses.",
601 .pme_code = 37,
602 .pme_flags = 0x0,
603 .pme_numasks = 0,
604 .pme_chip = PME_CRAYX2_CHIP_CPU,
605 .pme_ctr = 9,
606 .pme_event = 1,
607 .pme_chipno = 0,
608 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
609 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
610 .pme_nchips = PME_CRAYX2_CPU_CHIPS
611 },
612 /* P Counter 9 Event 2 */
613 {
614 .pme_name = "STALL_GRAD",
615 .pme_desc = "CPs no instructions graduate for any reason.",
616 .pme_code = 38,
617 .pme_flags = 0x0,
618 .pme_numasks = 0,
619 .pme_chip = PME_CRAYX2_CHIP_CPU,
620 .pme_ctr = 9,
621 .pme_event = 2,
622 .pme_chipno = 0,
623 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
624 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
625 .pme_nchips = PME_CRAYX2_CPU_CHIPS
626 },
627 /* P Counter 9 Event 3 */
628 {
629 .pme_name = "STALL_VLSU_LB",
630 .pme_desc = "CPs VLSU stalled waiting for load buffers (LB).",
631 .pme_code = 39,
632 .pme_flags = 0x0,
633 .pme_numasks = 0,
634 .pme_chip = PME_CRAYX2_CHIP_CPU,
635 .pme_ctr = 9,
636 .pme_event = 3,
637 .pme_chipno = 0,
638 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
639 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
640 .pme_nchips = PME_CRAYX2_CPU_CHIPS
641 },
642 /* P Counter 10 Event 0 */
643 {
644 .pme_name = "INST_MEM",
645 .pme_desc = "Number of A and S register load and store instructions graduated g=41, 44-47, 61, 64-67.",
646 .pme_code = 40,
647 .pme_flags = 0x0,
648 .pme_numasks = 0,
649 .pme_chip = PME_CRAYX2_CHIP_CPU,
650 .pme_ctr = 10,
651 .pme_event = 0,
652 .pme_chipno = 0,
653 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
654 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
655 .pme_nchips = PME_CRAYX2_CPU_CHIPS
656 },
657 /* P Counter 10 Event 1 */
658 {
659 .pme_name = "ICACHE_HIT_PEND",
660 .pme_desc = "Number of Icache hits to blocks with allocations pending.",
661 .pme_code = 41,
662 .pme_flags = 0x0,
663 .pme_numasks = 0,
664 .pme_chip = PME_CRAYX2_CHIP_CPU,
665 .pme_ctr = 10,
666 .pme_event = 1,
667 .pme_chipno = 0,
668 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
669 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
670 .pme_nchips = PME_CRAYX2_CPU_CHIPS
671 },
672 /* P Counter 10 Event 2 */
673 {
674 .pme_name = "STALL_GRAD_NO_INST",
675 .pme_desc = "CPs no instructions graduated due to empty active list.",
676 .pme_code = 42,
677 .pme_flags = 0x0,
678 .pme_numasks = 0,
679 .pme_chip = PME_CRAYX2_CHIP_CPU,
680 .pme_ctr = 10,
681 .pme_event = 2,
682 .pme_chipno = 0,
683 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
684 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
685 .pme_nchips = PME_CRAYX2_CPU_CHIPS
686 },
687 /* P Counter 10 Event 3 */
688 {
689 .pme_name = "STALL_VLSU_SB",
690 .pme_desc = "CPs VLSU stalled waiting for store buffer (SB).",
691 .pme_code = 43,
692 .pme_flags = 0x0,
693 .pme_numasks = 0,
694 .pme_chip = PME_CRAYX2_CHIP_CPU,
695 .pme_ctr = 10,
696 .pme_event = 3,
697 .pme_chipno = 0,
698 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
699 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
700 .pme_nchips = PME_CRAYX2_CPU_CHIPS
701 },
702 /* P Counter 11 Event 0 */
703 {
704 .pme_name = "INST_VFUG1",
705 .pme_desc = "Number of vector FUG 1 instructions graduated g=20-27, f=0-7,60-77 Add, sub, compare.",
706 .pme_code = 44,
707 .pme_flags = 0x0,
708 .pme_numasks = 0,
709 .pme_chip = PME_CRAYX2_CHIP_CPU,
710 .pme_ctr = 11,
711 .pme_event = 0,
712 .pme_chipno = 0,
713 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
714 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
715 .pme_nchips = PME_CRAYX2_CPU_CHIPS
716 },
717 /* P Counter 11 Event 1 */
718 {
719 .pme_name = "TLB_MISS",
720 .pme_desc = "Total number of TLB misses including ITLB, STLB, and VTLB.",
721 .pme_code = 45,
722 .pme_flags = 0x0,
723 .pme_numasks = 0,
724 .pme_chip = PME_CRAYX2_CHIP_CPU,
725 .pme_ctr = 11,
726 .pme_event = 1,
727 .pme_chipno = 0,
728 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
729 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
730 .pme_nchips = PME_CRAYX2_CPU_CHIPS
731 },
732 /* P Counter 11 Event 2 */
733 {
734 .pme_name = "STALL_GRAD_AX_INST",
735 .pme_desc = "CPs no instructions graduate and an A FUG instruction is at the head of the active list g=5, 40, 42, 43.",
736 .pme_code = 46,
737 .pme_flags = 0x0,
738 .pme_numasks = 0,
739 .pme_chip = PME_CRAYX2_CHIP_CPU,
740 .pme_ctr = 11,
741 .pme_event = 2,
742 .pme_chipno = 0,
743 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
744 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
745 .pme_nchips = PME_CRAYX2_CPU_CHIPS
746 },
747 /* P Counter 11 Event 3 */
748 {
749 .pme_name = "STALL_VLSU_RB",
750 .pme_desc = "CPs VLSU stalled waiting for request buffer (RB).",
751 .pme_code = 47,
752 .pme_flags = 0x0,
753 .pme_numasks = 0,
754 .pme_chip = PME_CRAYX2_CHIP_CPU,
755 .pme_ctr = 11,
756 .pme_event = 3,
757 .pme_chipno = 0,
758 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
759 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
760 .pme_nchips = PME_CRAYX2_CPU_CHIPS
761 },
762 /* P Counter 12 Event 0 */
763 {
764 .pme_name = "INST_VFUG2",
765 .pme_desc = "Number of vector FUG 2 instructions graduated g=20-27, f=30-37 (multiply, shift).",
766 .pme_code = 48,
767 .pme_flags = 0x0,
768 .pme_numasks = 0,
769 .pme_chip = PME_CRAYX2_CHIP_CPU,
770 .pme_ctr = 12,
771 .pme_event = 0,
772 .pme_chipno = 0,
773 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
774 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
775 .pme_nchips = PME_CRAYX2_CPU_CHIPS
776 },
777 /* P Counter 12 Event 1 */
778 {
779 .pme_name = "DCACHE_HIT",
780 .pme_desc = "Number of A or S loads that hit in the Dcache.",
781 .pme_code = 49,
782 .pme_flags = 0x0,
783 .pme_numasks = 0,
784 .pme_chip = PME_CRAYX2_CHIP_CPU,
785 .pme_ctr = 12,
786 .pme_event = 1,
787 .pme_chipno = 0,
788 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
789 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
790 .pme_nchips = PME_CRAYX2_CPU_CHIPS
791 },
792 /* P Counter 12 Event 2 */
793 {
794 .pme_name = "STALL_GRAD_SX_INST",
795 .pme_desc = "CPs no instructions graduate and an S FUG instruction is at the head of the active list g=60, 62, 63.",
796 .pme_code = 50,
797 .pme_flags = 0x0,
798 .pme_numasks = 0,
799 .pme_chip = PME_CRAYX2_CHIP_CPU,
800 .pme_ctr = 12,
801 .pme_event = 2,
802 .pme_chipno = 0,
803 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
804 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
805 .pme_nchips = PME_CRAYX2_CPU_CHIPS
806 },
807 /* P Counter 12 Event 3 */
808 {
809 .pme_name = "STALL_VLSU_VM",
810 .pme_desc = "CPs VLSU stalled waiting for VU vector mask (VM).",
811 .pme_code = 51,
812 .pme_flags = 0x0,
813 .pme_numasks = 0,
814 .pme_chip = PME_CRAYX2_CHIP_CPU,
815 .pme_ctr = 12,
816 .pme_event = 3,
817 .pme_chipno = 0,
818 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
819 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
820 .pme_nchips = PME_CRAYX2_CPU_CHIPS
821 },
822 /* P Counter 13 Event 0 */
823 {
824 .pme_name = "INST_VFUG3",
825 .pme_desc = "Number of vector FUG 3 instructions graduated g=20-27, f=10-27, 40-57, 77 div, sqrt, abs, cpsign, compress, merge, logical, bmm.",
826 .pme_code = 52,
827 .pme_flags = 0x0,
828 .pme_numasks = 0,
829 .pme_chip = PME_CRAYX2_CHIP_CPU,
830 .pme_ctr = 13,
831 .pme_event = 0,
832 .pme_chipno = 0,
833 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
834 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
835 .pme_nchips = PME_CRAYX2_CPU_CHIPS
836 },
837 /* P Counter 13 Event 1 */
838 {
839 .pme_name = "DCACHE_MISS",
840 .pme_desc = "Number of A or S loads that miss in the Dcache.",
841 .pme_code = 53,
842 .pme_flags = 0x0,
843 .pme_numasks = 0,
844 .pme_chip = PME_CRAYX2_CHIP_CPU,
845 .pme_ctr = 13,
846 .pme_event = 1,
847 .pme_chipno = 0,
848 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
849 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
850 .pme_nchips = PME_CRAYX2_CPU_CHIPS
851 },
852 /* P Counter 13 Event 2 */
853 {
854 .pme_name = "STALL_GRAD_FP_INST",
855 .pme_desc = "CPs no instructions graduate and an S FP instruction is at the head of the active list g=62, t1=0.",
856 .pme_code = 54,
857 .pme_flags = 0x0,
858 .pme_numasks = 0,
859 .pme_chip = PME_CRAYX2_CHIP_CPU,
860 .pme_ctr = 13,
861 .pme_event = 2,
862 .pme_chipno = 0,
863 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
864 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
865 .pme_nchips = PME_CRAYX2_CPU_CHIPS
866 },
867 /* P Counter 13 Event 3 */
868 {
869 .pme_name = "STALL_VLSU_SREF",
870 .pme_desc = "CPs VLSU stalled waiting for prior scalar instruction reference sent.",
871 .pme_code = 55,
872 .pme_flags = 0x0,
873 .pme_numasks = 0,
874 .pme_chip = PME_CRAYX2_CHIP_CPU,
875 .pme_ctr = 13,
876 .pme_event = 3,
877 .pme_chipno = 0,
878 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
879 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
880 .pme_nchips = PME_CRAYX2_CPU_CHIPS
881 },
882 /* P Counter 14 Event 0 */
883 {
884 .pme_name = "VOPS_EXT_FUG3",
885 .pme_desc = "Number of vector FUG 3 external operations g=20-27 f=25,57,77 compress, merge, bmm.",
886 .pme_code = 56,
887 .pme_flags = 0x0,
888 .pme_numasks = 0,
889 .pme_chip = PME_CRAYX2_CHIP_CPU,
890 .pme_ctr = 14,
891 .pme_event = 0,
892 .pme_chipno = 0,
893 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
894 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
895 .pme_nchips = PME_CRAYX2_CPU_CHIPS
896 },
897 /* P Counter 14 Event 1 */
898 {
899 .pme_name = "DCACHE_HIT_PEND",
900 .pme_desc = "Number of scalar loads that hit in the Dcache and in the FOQ and the load is merged with a pending allocation.",
901 .pme_code = 57,
902 .pme_flags = 0x0,
903 .pme_numasks = 0,
904 .pme_chip = PME_CRAYX2_CHIP_CPU,
905 .pme_ctr = 14,
906 .pme_event = 1,
907 .pme_chipno = 0,
908 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
909 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
910 .pme_nchips = PME_CRAYX2_CPU_CHIPS
911 },
912 /* P Counter 14 Event 2 */
913 {
914 .pme_name = "STALL_GRAD_LOAD_INST",
915 .pme_desc = "CPs no instructions graduate and a scalar load is at the head of the active list.",
916 .pme_code = 58,
917 .pme_flags = 0x0,
918 .pme_numasks = 0,
919 .pme_chip = PME_CRAYX2_CHIP_CPU,
920 .pme_ctr = 14,
921 .pme_event = 2,
922 .pme_chipno = 0,
923 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
924 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
925 .pme_nchips = PME_CRAYX2_CPU_CHIPS
926 },
927 /* P Counter 14 Event 3 */
928 {
929 .pme_name = "STALL_VLSU_INDEX",
930 .pme_desc = "CPS VLSU stalled waiting for busy scatter or gather index register.",
931 .pme_code = 59,
932 .pme_flags = 0x0,
933 .pme_numasks = 0,
934 .pme_chip = PME_CRAYX2_CHIP_CPU,
935 .pme_ctr = 14,
936 .pme_event = 3,
937 .pme_chipno = 0,
938 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
939 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
940 .pme_nchips = PME_CRAYX2_CPU_CHIPS
941 },
942 /* P Counter 15 Event 0 */
943 {
944 .pme_name = "VOPS_LOG_FUG3",
945 .pme_desc = "Number of vector FUG 3 logical operations.",
946 .pme_code = 60,
947 .pme_flags = 0x0,
948 .pme_numasks = 0,
949 .pme_chip = PME_CRAYX2_CHIP_CPU,
950 .pme_ctr = 15,
951 .pme_event = 0,
952 .pme_chipno = 0,
953 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
954 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
955 .pme_nchips = PME_CRAYX2_CPU_CHIPS
956 },
957 /* P Counter 15 Event 1 */
958 {
959 .pme_name = "DCACHE_HIT_WORD",
960 .pme_desc = "Number of scalar loads that hit in the Dcache and hit in the FOQ and were not merged with a pending allocation.",
961 .pme_code = 61,
962 .pme_flags = 0x0,
963 .pme_numasks = 0,
964 .pme_chip = PME_CRAYX2_CHIP_CPU,
965 .pme_ctr = 15,
966 .pme_event = 1,
967 .pme_chipno = 0,
968 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
969 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
970 .pme_nchips = PME_CRAYX2_CPU_CHIPS
971 },
972 /* P Counter 15 Event 2 */
973 {
974 .pme_name = "STALL_GRAD_STORE_INST",
975 .pme_desc = "CPs no instructions graduate and a scalar store is at the head of the active list.",
976 .pme_code = 62,
977 .pme_flags = 0x0,
978 .pme_numasks = 0,
979 .pme_chip = PME_CRAYX2_CHIP_CPU,
980 .pme_ctr = 15,
981 .pme_event = 2,
982 .pme_chipno = 0,
983 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
984 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
985 .pme_nchips = PME_CRAYX2_CPU_CHIPS
986 },
987 /* P Counter 15 Event 3 */
988 {
989 .pme_name = "STALL_VLSU_FOM",
990 .pme_desc = "CPs VLSU stalled in forced order mode.",
991 .pme_code = 63,
992 .pme_flags = 0x0,
993 .pme_numasks = 0,
994 .pme_chip = PME_CRAYX2_CHIP_CPU,
995 .pme_ctr = 15,
996 .pme_event = 3,
997 .pme_chipno = 0,
998 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
999 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1000 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1001 },
1002 /* P Counter 16 Event 0 */
1003 {
1004 .pme_name = "INST_V",
1005 .pme_desc = "Number of elemental vector instructions graduated g=20-27, 30-33.",
1006 .pme_code = 64,
1007 .pme_flags = 0x0,
1008 .pme_numasks = 0,
1009 .pme_chip = PME_CRAYX2_CHIP_CPU,
1010 .pme_ctr = 16,
1011 .pme_event = 0,
1012 .pme_chipno = 0,
1013 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1014 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1015 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1016 },
1017 /* P Counter 16 Event 1 */
1018 {
1019 .pme_name = "INST_V_INT",
1020 .pme_desc = "Number of elemental vector integer instructions graduated g=20-27 & t1=",
1021 .pme_code = 65,
1022 .pme_flags = 0x0,
1023 .pme_numasks = 0,
1024 .pme_chip = PME_CRAYX2_CHIP_CPU,
1025 .pme_ctr = 16,
1026 .pme_event = 1,
1027 .pme_chipno = 0,
1028 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1029 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1030 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1031 },
1032 /* P Counter 16 Event 2 */
1033 {
1034 .pme_name = "INST_V_FP",
1035 .pme_desc = "Number of elemental vector FP instructions graduated g=20-27 & t1=0.",
1036 .pme_code = 66,
1037 .pme_flags = 0x0,
1038 .pme_numasks = 0,
1039 .pme_chip = PME_CRAYX2_CHIP_CPU,
1040 .pme_ctr = 16,
1041 .pme_event = 2,
1042 .pme_chipno = 0,
1043 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1044 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1045 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1046 },
1047 /* P Counter 16 Event 3 */
1048 {
1049 .pme_name = "INST_V_MEM",
1050 .pme_desc = "Number of elemental vector memory instructions graduated g=30-33.",
1051 .pme_code = 67,
1052 .pme_flags = 0x0,
1053 .pme_numasks = 0,
1054 .pme_chip = PME_CRAYX2_CHIP_CPU,
1055 .pme_ctr = 16,
1056 .pme_event = 3,
1057 .pme_chipno = 0,
1058 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1059 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1060 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1061 },
1062 /* P Counter 17 Event 0 */
1063 {
1064 .pme_name = "VOPS_VL",
1065 .pme_desc = "Inst_V * Current VL.",
1066 .pme_code = 68,
1067 .pme_flags = 0x0,
1068 .pme_numasks = 0,
1069 .pme_chip = PME_CRAYX2_CHIP_CPU,
1070 .pme_ctr = 17,
1071 .pme_event = 0,
1072 .pme_chipno = 0,
1073 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1074 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1075 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1076 },
1077 /* P Counter 17 Event 1 */
1078 {
1079 .pme_name = "DCACHE_INVAL_V",
1080 .pme_desc = "Number of Dcache invalidates due to vector stores.",
1081 .pme_code = 69,
1082 .pme_flags = 0x0,
1083 .pme_numasks = 0,
1084 .pme_chip = PME_CRAYX2_CHIP_CPU,
1085 .pme_ctr = 17,
1086 .pme_event = 1,
1087 .pme_chipno = 0,
1088 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1089 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1090 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1091 },
1092 /* P Counter 17 Event 2 */
1093 {
1094 .pme_name = "VOPS_VL_32-BIT",
1095 .pme_desc = "Inst_V * Current VL for 32-bit operations only.",
1096 .pme_code = 70,
1097 .pme_flags = 0x0,
1098 .pme_numasks = 0,
1099 .pme_chip = PME_CRAYX2_CHIP_CPU,
1100 .pme_ctr = 17,
1101 .pme_event = 2,
1102 .pme_chipno = 0,
1103 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1104 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1105 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1106 },
1107 /* P Counter 17 Event 3 */
1108 {
1109 .pme_name = "STALL_VLSU",
1110 .pme_desc = "Stall vector load store for any reason.",
1111 .pme_code = 71,
1112 .pme_flags = 0x0,
1113 .pme_numasks = 0,
1114 .pme_chip = PME_CRAYX2_CHIP_CPU,
1115 .pme_ctr = 17,
1116 .pme_event = 3,
1117 .pme_chipno = 0,
1118 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1119 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1120 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1121 },
1122 /* P Counter 18 Event 0 */
1123 {
1124 .pme_name = "VOPS_INT_ADD",
1125 .pme_desc = "Number of selected vector integer add operations g=20-27 & f=0-3 & t1=",
1126 .pme_code = 72,
1127 .pme_flags = 0x0,
1128 .pme_numasks = 0,
1129 .pme_chip = PME_CRAYX2_CHIP_CPU,
1130 .pme_ctr = 18,
1131 .pme_event = 0,
1132 .pme_chipno = 0,
1133 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1134 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1135 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1136 },
1137 /* P Counter 18 Event 1 */
1138 {
1139 .pme_name = "DCACHE_INVAL_L2",
1140 .pme_desc = "Number of Dcache invalidates from L2 cache.",
1141 .pme_code = 73,
1142 .pme_flags = 0x0,
1143 .pme_numasks = 0,
1144 .pme_chip = PME_CRAYX2_CHIP_CPU,
1145 .pme_ctr = 18,
1146 .pme_event = 1,
1147 .pme_chipno = 0,
1148 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1149 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1150 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1151 },
1152 /* P Counter 18 Event 2 */
1153 {
1154 .pme_name = "STALL_GRAD_XFER_INST",
1155 .pme_desc = "Number of CPs no instruction graduates and an A to S or S to A move is at the head of the active list.",
1156 .pme_code = 74,
1157 .pme_flags = 0x0,
1158 .pme_numasks = 0,
1159 .pme_chip = PME_CRAYX2_CHIP_CPU,
1160 .pme_ctr = 18,
1161 .pme_event = 2,
1162 .pme_chipno = 0,
1163 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1164 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1165 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1166 },
1167 /* P Counter 18 Event 3 */
1168 {
1169 .pme_name = "STALL_VU_VM",
1170 .pme_desc = "CPs VU stalled waiting for vector mask.",
1171 .pme_code = 75,
1172 .pme_flags = 0x0,
1173 .pme_numasks = 0,
1174 .pme_chip = PME_CRAYX2_CHIP_CPU,
1175 .pme_ctr = 18,
1176 .pme_event = 3,
1177 .pme_chipno = 0,
1178 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1179 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1180 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1181 },
1182 /* P Counter 19 Event 0 */
1183 {
1184 .pme_name = "VOPS_FP_ADD",
1185 .pme_desc = "Number of selected vector FP add operations g=20-27 & f=0-3 & t1=0.",
1186 .pme_code = 76,
1187 .pme_flags = 0x0,
1188 .pme_numasks = 0,
1189 .pme_chip = PME_CRAYX2_CHIP_CPU,
1190 .pme_ctr = 19,
1191 .pme_event = 0,
1192 .pme_chipno = 0,
1193 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1194 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1195 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1196 },
1197 /* P Counter 19 Event 1 */
1198 {
1199 .pme_name = "DCACHE_INVALIDATE",
1200 .pme_desc = "Total Number of Dcache invalidates.",
1201 .pme_code = 77,
1202 .pme_flags = 0x0,
1203 .pme_numasks = 0,
1204 .pme_chip = PME_CRAYX2_CHIP_CPU,
1205 .pme_ctr = 19,
1206 .pme_event = 1,
1207 .pme_chipno = 0,
1208 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1209 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1210 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1211 },
1212 /* P Counter 19 Event 2 */
1213 {
1214 .pme_name = "STALL_GRAD_VXFER_INST",
1215 .pme_desc = "CPs no instruction graduates and a V to A or V to S move is at the head of the active list.",
1216 .pme_code = 78,
1217 .pme_flags = 0x0,
1218 .pme_numasks = 0,
1219 .pme_chip = PME_CRAYX2_CHIP_CPU,
1220 .pme_ctr = 19,
1221 .pme_event = 2,
1222 .pme_chipno = 0,
1223 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1224 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1225 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1226 },
1227 /* P Counter 19 Event 3 */
1228 {
1229 .pme_name = "STALL_VU_VR_MEM",
1230 .pme_desc = "CPs VU is stalled waiting on a busy vector register being loaded from memory.",
1231 .pme_code = 79,
1232 .pme_flags = 0x0,
1233 .pme_numasks = 0,
1234 .pme_chip = PME_CRAYX2_CHIP_CPU,
1235 .pme_ctr = 19,
1236 .pme_event = 3,
1237 .pme_chipno = 0,
1238 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1239 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1240 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1241 },
1242 /* P Counter 20 Event 0 */
1243 {
1244 .pme_name = "VOPS_INT_LOG",
1245 .pme_desc = "Number of selected vector integer logical operations g=20-27 & f=10-27 & t1=1.",
1246 .pme_code = 80,
1247 .pme_flags = 0x0,
1248 .pme_numasks = 0,
1249 .pme_chip = PME_CRAYX2_CHIP_CPU,
1250 .pme_ctr = 20,
1251 .pme_event = 0,
1252 .pme_chipno = 0,
1253 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1254 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1255 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1256 },
1257 /* P Counter 20 Event 1 */
1258 {
1259 .pme_name = "BRANCH_PRED",
1260 .pme_desc = "Number of branches predicted.",
1261 .pme_code = 81,
1262 .pme_flags = 0x0,
1263 .pme_numasks = 0,
1264 .pme_chip = PME_CRAYX2_CHIP_CPU,
1265 .pme_ctr = 20,
1266 .pme_event = 1,
1267 .pme_chipno = 0,
1268 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1269 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1270 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1271 },
1272 /* P Counter 20 Event 2 */
1273 {
1274 .pme_name = "STALL_GRAD_VLSU_INST",
1275 .pme_desc = "Number of CPs no instruction graduates and a vector load, store, or AMO instruction is at the head of the active list.",
1276 .pme_code = 82,
1277 .pme_flags = 0x0,
1278 .pme_numasks = 0,
1279 .pme_chip = PME_CRAYX2_CHIP_CPU,
1280 .pme_ctr = 20,
1281 .pme_event = 2,
1282 .pme_chipno = 0,
1283 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1284 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1285 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1286 },
1287 /* P Counter 20 Event 3 */
1288 {
1289 .pme_name = "STALL_VU_TLB",
1290 .pme_desc = "CPs VU stalled waiting for a memory translation.",
1291 .pme_code = 83,
1292 .pme_flags = 0x0,
1293 .pme_numasks = 0,
1294 .pme_chip = PME_CRAYX2_CHIP_CPU,
1295 .pme_ctr = 20,
1296 .pme_event = 3,
1297 .pme_chipno = 0,
1298 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1299 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1300 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1301 },
1302 /* P Counter 21 Event 0 */
1303 {
1304 .pme_name = "VOPS_FP_DIV",
1305 .pme_desc = "Number of selected vector FP divide and sqrt operations g=20-27 & f=10-11 & t1=0.",
1306 .pme_code = 84,
1307 .pme_flags = 0x0,
1308 .pme_numasks = 0,
1309 .pme_chip = PME_CRAYX2_CHIP_CPU,
1310 .pme_ctr = 21,
1311 .pme_event = 0,
1312 .pme_chipno = 0,
1313 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1314 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1315 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1316 },
1317 /* P Counter 21 Event 1 */
1318 {
1319 .pme_name = "BRANCH_CORRECT",
1320 .pme_desc = "Number of branches predicted correctly.",
1321 .pme_code = 85,
1322 .pme_flags = 0x0,
1323 .pme_numasks = 0,
1324 .pme_chip = PME_CRAYX2_CHIP_CPU,
1325 .pme_ctr = 21,
1326 .pme_event = 1,
1327 .pme_chipno = 0,
1328 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1329 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1330 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1331 },
1332 /* P Counter 21 Event 2 */
1333 {
1334 .pme_name = "STALL_SLSQ_DEST",
1335 .pme_desc = "SLS issue stall for FOQ, PARB, ORB full or Lsync vs active.",
1336 .pme_code = 86,
1337 .pme_flags = 0x0,
1338 .pme_numasks = 0,
1339 .pme_chip = PME_CRAYX2_CHIP_CPU,
1340 .pme_ctr = 21,
1341 .pme_event = 2,
1342 .pme_chipno = 0,
1343 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1344 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1345 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1346 },
1347 /* P Counter 21 Event 3 */
1348 {
1349 .pme_name = "STALL_VLSU_VK_PORT",
1350 .pme_desc = "CPs VLSU stalled waiting for scatter or gather index register read port.",
1351 .pme_code = 87,
1352 .pme_flags = 0x0,
1353 .pme_numasks = 0,
1354 .pme_chip = PME_CRAYX2_CHIP_CPU,
1355 .pme_ctr = 21,
1356 .pme_event = 3,
1357 .pme_chipno = 0,
1358 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1359 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1360 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1361 },
1362 /* P Counter 22 Event 0 */
1363 {
1364 .pme_name = "VOPS_INT_SHIFT",
1365 .pme_desc = "Number of selected vector integer shift operations g=20-27 & f=30-37 & t1=",
1366 .pme_code = 88,
1367 .pme_flags = 0x0,
1368 .pme_numasks = 0,
1369 .pme_chip = PME_CRAYX2_CHIP_CPU,
1370 .pme_ctr = 22,
1371 .pme_event = 0,
1372 .pme_chipno = 0,
1373 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1374 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1375 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1376 },
1377 /* P Counter 22 Event 1 */
1378 {
1379 .pme_name = "JTB_PRED",
1380 .pme_desc = "Number of jumps predicted g=57 & f=0,20.",
1381 .pme_code = 89,
1382 .pme_flags = 0x0,
1383 .pme_numasks = 0,
1384 .pme_chip = PME_CRAYX2_CHIP_CPU,
1385 .pme_ctr = 22,
1386 .pme_event = 1,
1387 .pme_chipno = 0,
1388 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1389 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1390 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1391 },
1392 /* P Counter 22 Event 2 */
1393 {
1394 .pme_name = "STALL_GRAD_ARQ_DEST",
1395 .pme_desc = "Stall arq issue due to vdispatch, control unit, or A to S full.",
1396 .pme_code = 90,
1397 .pme_flags = 0x0,
1398 .pme_numasks = 0,
1399 .pme_chip = PME_CRAYX2_CHIP_CPU,
1400 .pme_ctr = 22,
1401 .pme_event = 2,
1402 .pme_chipno = 0,
1403 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1404 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1405 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1406 },
1407 /* P Counter 22 Event 3 */
1408 {
1409 .pme_name = "STALL_VLSU_ADR_PORT",
1410 .pme_desc = "CPs VLSU stalled waiting for address read port.",
1411 .pme_code = 91,
1412 .pme_flags = 0x0,
1413 .pme_numasks = 0,
1414 .pme_chip = PME_CRAYX2_CHIP_CPU,
1415 .pme_ctr = 22,
1416 .pme_event = 3,
1417 .pme_chipno = 0,
1418 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1419 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1420 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1421 },
1422 /* P Counter 23 Event 0 */
1423 {
1424 .pme_name = "VOPS_FP_MULT",
1425 .pme_desc = "Number of selected vector FP multiply operations g=20-27 & f=30-37 & t1=0.",
1426 .pme_code = 92,
1427 .pme_flags = 0x0,
1428 .pme_numasks = 0,
1429 .pme_chip = PME_CRAYX2_CHIP_CPU,
1430 .pme_ctr = 23,
1431 .pme_event = 0,
1432 .pme_chipno = 0,
1433 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1434 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1435 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1436 },
1437 /* P Counter 23 Event 1 */
1438 {
1439 .pme_name = "JTB_CORRECT",
1440 .pme_desc = "Number of jumps predicted correctly g=57 & f=0,20.",
1441 .pme_code = 93,
1442 .pme_flags = 0x0,
1443 .pme_numasks = 0,
1444 .pme_chip = PME_CRAYX2_CHIP_CPU,
1445 .pme_ctr = 23,
1446 .pme_event = 1,
1447 .pme_chipno = 0,
1448 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1449 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1450 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1451 },
1452 /* P Counter 23 Event 2 */
1453 {
1454 .pme_name = "STALL_SRQ_DEST",
1455 .pme_desc = "Stall srq issue due to vdispatch or S to A full.",
1456 .pme_code = 94,
1457 .pme_flags = 0x0,
1458 .pme_numasks = 0,
1459 .pme_chip = PME_CRAYX2_CHIP_CPU,
1460 .pme_ctr = 23,
1461 .pme_event = 2,
1462 .pme_chipno = 0,
1463 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1464 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1465 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1466 },
1467 /* P Counter 23 Event 3 */
1468 {
1469 .pme_name = "STALL_VLSU_MISC",
1470 .pme_desc = "CPs VLSU stalled due to miscellaneous instructions.",
1471 .pme_code = 95,
1472 .pme_flags = 0x0,
1473 .pme_numasks = 0,
1474 .pme_chip = PME_CRAYX2_CHIP_CPU,
1475 .pme_ctr = 23,
1476 .pme_event = 3,
1477 .pme_chipno = 0,
1478 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1479 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1480 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1481 },
1482 /* P Counter 24 Event 0 */
1483 {
1484 .pme_name = "VOPS_LOAD_INDEX",
1485 .pme_desc = "Number of selected vector load indexed references g=30-33 & f2=1 & f0=0.",
1486 .pme_code = 96,
1487 .pme_flags = 0x0,
1488 .pme_numasks = 0,
1489 .pme_chip = PME_CRAYX2_CHIP_CPU,
1490 .pme_ctr = 24,
1491 .pme_event = 0,
1492 .pme_chipno = 0,
1493 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1494 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1495 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1496 },
1497 /* P Counter 24 Event 1 */
1498 {
1499 .pme_name = "VOPS_INT_MISC",
1500 .pme_desc = "Number of selected vector integer misc. operations g=20-27 & f=40-77 & t1=",
1501 .pme_code = 97,
1502 .pme_flags = 0x0,
1503 .pme_numasks = 0,
1504 .pme_chip = PME_CRAYX2_CHIP_CPU,
1505 .pme_ctr = 24,
1506 .pme_event = 1,
1507 .pme_chipno = 0,
1508 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1509 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1510 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1511 },
1512 /* P Counter 24 Event 2 */
1513 {
1514 .pme_name = "INST_LSYNCVS",
1515 .pme_desc = "Number of LsyncVS instructions graduated.",
1516 .pme_code = 98,
1517 .pme_flags = 0x0,
1518 .pme_numasks = 0,
1519 .pme_chip = PME_CRAYX2_CHIP_CPU,
1520 .pme_ctr = 24,
1521 .pme_event = 2,
1522 .pme_chipno = 0,
1523 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1524 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1525 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1526 },
1527 /* P Counter 24 Event 3 */
1528 {
1529 .pme_name = "VOPS_VL_64-BIT",
1530 .pme_desc = "Inst_V * Current VL for 64-bit operations only.",
1531 .pme_code = 99,
1532 .pme_flags = 0x0,
1533 .pme_numasks = 0,
1534 .pme_chip = PME_CRAYX2_CHIP_CPU,
1535 .pme_ctr = 24,
1536 .pme_event = 3,
1537 .pme_chipno = 0,
1538 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1539 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1540 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1541 },
1542 /* P Counter 25 Event 0 */
1543 {
1544 .pme_name = "VOPS_STORE_INDEX",
1545 .pme_desc = "Number of selected vector store indexed references g=30-33 & f2=1 & f0=1",
1546 .pme_code = 100,
1547 .pme_flags = 0x0,
1548 .pme_numasks = 0,
1549 .pme_chip = PME_CRAYX2_CHIP_CPU,
1550 .pme_ctr = 25,
1551 .pme_event = 0,
1552 .pme_chipno = 0,
1553 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1554 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1555 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1556 },
1557 /* P Counter 25 Event 1 */
1558 {
1559 .pme_name = "JRS_PRED",
1560 .pme_desc = "Number of return jumps predicted g=57, f=40.",
1561 .pme_code = 101,
1562 .pme_flags = 0x0,
1563 .pme_numasks = 0,
1564 .pme_chip = PME_CRAYX2_CHIP_CPU,
1565 .pme_ctr = 25,
1566 .pme_event = 1,
1567 .pme_chipno = 0,
1568 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1569 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1570 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1571 },
1572 /* P Counter 25 Event 2 */
1573 {
1574 .pme_name = "STALL_SLSQ_PARB",
1575 .pme_desc = "Number of CPs SLS issue stalled due to PARB full.",
1576 .pme_code = 102,
1577 .pme_flags = 0x0,
1578 .pme_numasks = 0,
1579 .pme_chip = PME_CRAYX2_CHIP_CPU,
1580 .pme_ctr = 25,
1581 .pme_event = 2,
1582 .pme_chipno = 0,
1583 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1584 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1585 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1586 },
1587 /* P Counter 25 Event 3 */
1588 {
1589 .pme_name = "<P:25:3>",
1590 .pme_desc = "<NA>",
1591 .pme_code = 103,
1592 .pme_flags = 0x0,
1593 .pme_numasks = 0,
1594 .pme_chip = PME_CRAYX2_CHIP_CPU,
1595 .pme_ctr = 25,
1596 .pme_event = 3,
1597 .pme_chipno = 0,
1598 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1599 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1600 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1601 },
1602 /* P Counter 26 Event 0 */
1603 {
1604 .pme_name = "VOPS_LOADS",
1605 .pme_desc = "Number of selected vector load references g=30-33 & f0=0.",
1606 .pme_code = 104,
1607 .pme_flags = 0x0,
1608 .pme_numasks = 0,
1609 .pme_chip = PME_CRAYX2_CHIP_CPU,
1610 .pme_ctr = 26,
1611 .pme_event = 0,
1612 .pme_chipno = 0,
1613 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1614 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1615 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1616 },
1617 /* P Counter 26 Event 1 */
1618 {
1619 .pme_name = "JRS_CORRECT",
1620 .pme_desc = "Number of return jumps predicted correctly g=57, f=40.",
1621 .pme_code = 105,
1622 .pme_flags = 0x0,
1623 .pme_numasks = 0,
1624 .pme_chip = PME_CRAYX2_CHIP_CPU,
1625 .pme_ctr = 26,
1626 .pme_event = 1,
1627 .pme_chipno = 0,
1628 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1629 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1630 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1631 },
1632 /* P Counter 26 Event 2 */
1633 {
1634 .pme_name = "STALL_SLSQ_ORB",
1635 .pme_desc = "Number of CPs SLS issue stalled due to all ORB entries in use.",
1636 .pme_code = 106,
1637 .pme_flags = 0x0,
1638 .pme_numasks = 0,
1639 .pme_chip = PME_CRAYX2_CHIP_CPU,
1640 .pme_ctr = 26,
1641 .pme_event = 2,
1642 .pme_chipno = 0,
1643 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1644 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1645 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1646 },
1647 /* P Counter 26 Event 3 */
1648 {
1649 .pme_name = "STALL_VU_MISC",
1650 .pme_desc = "CPs VU stalled due to miscellaneous instructions.",
1651 .pme_code = 107,
1652 .pme_flags = 0x0,
1653 .pme_numasks = 0,
1654 .pme_chip = PME_CRAYX2_CHIP_CPU,
1655 .pme_ctr = 26,
1656 .pme_event = 3,
1657 .pme_chipno = 0,
1658 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1659 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1660 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1661 },
1662 /* P Counter 27 Event 0 */
1663 {
1664 .pme_name = "VOPS_STORE",
1665 .pme_desc = "Number of selected vector store references g=30-33 & f0=",
1666 .pme_code = 108,
1667 .pme_flags = 0x0,
1668 .pme_numasks = 0,
1669 .pme_chip = PME_CRAYX2_CHIP_CPU,
1670 .pme_ctr = 27,
1671 .pme_event = 0,
1672 .pme_chipno = 0,
1673 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1674 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1675 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1676 },
1677 /* P Counter 27 Event 1 */
1678 {
1679 .pme_name = "INST_MEM_ALLOC",
1680 .pme_desc = "Number of A and S register memory instructions that allocate.",
1681 .pme_code = 109,
1682 .pme_flags = 0x0,
1683 .pme_numasks = 0,
1684 .pme_chip = PME_CRAYX2_CHIP_CPU,
1685 .pme_ctr = 27,
1686 .pme_event = 1,
1687 .pme_chipno = 0,
1688 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1689 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1690 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1691 },
1692 /* P Counter 27 Event 2 */
1693 {
1694 .pme_name = "STALL_SLSQ_FOQ",
1695 .pme_desc = "Number of CPs SLS issue stalled due to full FOQ.",
1696 .pme_code = 110,
1697 .pme_flags = 0x0,
1698 .pme_numasks = 0,
1699 .pme_chip = PME_CRAYX2_CHIP_CPU,
1700 .pme_ctr = 27,
1701 .pme_event = 2,
1702 .pme_chipno = 0,
1703 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1704 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1705 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1706 },
1707 /* P Counter 27 Event 3 */
1708 {
1709 .pme_name = "STALL_VDU_NO_INST_VU",
1710 .pme_desc = "CPs VDU and VU have no valid instructions.",
1711 .pme_code = 111,
1712 .pme_flags = 0x0,
1713 .pme_numasks = 0,
1714 .pme_chip = PME_CRAYX2_CHIP_CPU,
1715 .pme_ctr = 27,
1716 .pme_event = 3,
1717 .pme_chipno = 0,
1718 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1719 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1720 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1721 },
1722 /* P Counter 28 Event 0 */
1723 {
1724 .pme_name = "VOPS_LOAD_STRIDE",
1725 .pme_desc = "Number of selected vector load references that were stride >2 or <-2.",
1726 .pme_code = 112,
1727 .pme_flags = 0x0,
1728 .pme_numasks = 0,
1729 .pme_chip = PME_CRAYX2_CHIP_CPU,
1730 .pme_ctr = 28,
1731 .pme_event = 0,
1732 .pme_chipno = 0,
1733 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1734 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1735 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1736 },
1737 /* P Counter 28 Event 1 */
1738 {
1739 .pme_name = "INST_SYSCALL",
1740 .pme_desc = "Number of syscall instructions graduated g=01.",
1741 .pme_code = 113,
1742 .pme_flags = 0x0,
1743 .pme_numasks = 0,
1744 .pme_chip = PME_CRAYX2_CHIP_CPU,
1745 .pme_ctr = 28,
1746 .pme_event = 1,
1747 .pme_chipno = 0,
1748 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1749 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1750 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1751 },
1752 /* P Counter 28 Event 2 */
1753 {
1754 .pme_name = "STALL_SLSQ_LSYNC_VS",
1755 .pme_desc = "Number of CPs SLS issue is stalled due to active Lsync vs instruction.",
1756 .pme_code = 114,
1757 .pme_flags = 0x0,
1758 .pme_numasks = 0,
1759 .pme_chip = PME_CRAYX2_CHIP_CPU,
1760 .pme_ctr = 28,
1761 .pme_event = 2,
1762 .pme_chipno = 0,
1763 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1764 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1765 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1766 },
1767 /* P Counter 28 Event 3 */
1768 {
1769 .pme_name = "STALL_VDU_SOP_VU",
1770 .pme_desc = "Number of CPs vector issue has no instructions and the next instruction is waiting on an S reg operand.",
1771 .pme_code = 115,
1772 .pme_flags = 0x0,
1773 .pme_numasks = 0,
1774 .pme_chip = PME_CRAYX2_CHIP_CPU,
1775 .pme_ctr = 28,
1776 .pme_event = 3,
1777 .pme_chipno = 0,
1778 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1779 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1780 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1781 },
1782 /* P Counter 29 Event 0 */
1783 {
1784 .pme_name = "VOPS_STORE_STRIDE",
1785 .pme_desc = "Number of selected vector store references that were stride >2 or <-2.",
1786 .pme_code = 116,
1787 .pme_flags = 0x0,
1788 .pme_numasks = 0,
1789 .pme_chip = PME_CRAYX2_CHIP_CPU,
1790 .pme_ctr = 29,
1791 .pme_event = 0,
1792 .pme_chipno = 0,
1793 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1794 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1795 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1796 },
1797 /* P Counter 29 Event 1 */
1798 {
1799 .pme_name = "<P:29:1>",
1800 .pme_desc = "<NA>",
1801 .pme_code = 117,
1802 .pme_flags = 0x0,
1803 .pme_numasks = 0,
1804 .pme_chip = PME_CRAYX2_CHIP_CPU,
1805 .pme_ctr = 29,
1806 .pme_event = 1,
1807 .pme_chipno = 0,
1808 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1809 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1810 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1811 },
1812 /* P Counter 29 Event 2 */
1813 {
1814 .pme_name = "<P:29:2>",
1815 .pme_desc = "<NA>",
1816 .pme_code = 118,
1817 .pme_flags = 0x0,
1818 .pme_numasks = 0,
1819 .pme_chip = PME_CRAYX2_CHIP_CPU,
1820 .pme_ctr = 29,
1821 .pme_event = 2,
1822 .pme_chipno = 0,
1823 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1824 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1825 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1826 },
1827 /* P Counter 29 Event 3 */
1828 {
1829 .pme_name = "STALL_VDU_NO_INST_VLSU",
1830 .pme_desc = "CPs VDU and VLSU have no valid instructions.",
1831 .pme_code = 119,
1832 .pme_flags = 0x0,
1833 .pme_numasks = 0,
1834 .pme_chip = PME_CRAYX2_CHIP_CPU,
1835 .pme_ctr = 29,
1836 .pme_event = 3,
1837 .pme_chipno = 0,
1838 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1839 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1840 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1841 },
1842 /* P Counter 30 Event 0 */
1843 {
1844 .pme_name = "VOPS_LOAD_ALLOC",
1845 .pme_desc = "Number of selected vector load references that were marked allocate (cache line requests count as 1).",
1846 .pme_code = 120,
1847 .pme_flags = 0x0,
1848 .pme_numasks = 0,
1849 .pme_chip = PME_CRAYX2_CHIP_CPU,
1850 .pme_ctr = 30,
1851 .pme_event = 0,
1852 .pme_chipno = 0,
1853 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1854 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1855 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1856 },
1857 /* P Counter 30 Event 1 */
1858 {
1859 .pme_name = "INST_LOAD",
1860 .pme_desc = "Number of A or S memory loads g=44, 45, 41 & f0=0, 64, 65, 61 & f0=0.",
1861 .pme_code = 121,
1862 .pme_flags = 0x0,
1863 .pme_numasks = 0,
1864 .pme_chip = PME_CRAYX2_CHIP_CPU,
1865 .pme_ctr = 30,
1866 .pme_event = 1,
1867 .pme_chipno = 0,
1868 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1869 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1870 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1871 },
1872 /* P Counter 30 Event 2 */
1873 {
1874 .pme_name = "EXCEPTIONS_TAKEN",
1875 .pme_desc = "Taken exception count.",
1876 .pme_code = 122,
1877 .pme_flags = 0x0,
1878 .pme_numasks = 0,
1879 .pme_chip = PME_CRAYX2_CHIP_CPU,
1880 .pme_ctr = 30,
1881 .pme_event = 2,
1882 .pme_chipno = 0,
1883 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1884 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1885 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1886 },
1887 /* P Counter 30 Event 3 */
1888 {
1889 .pme_name = "STALL_VDU_SCM_VLSU",
1890 .pme_desc = "CPs VDU stalled waiting for scalar commit and VLSU has no valid instruction.",
1891 .pme_code = 123,
1892 .pme_flags = 0x0,
1893 .pme_numasks = 0,
1894 .pme_chip = PME_CRAYX2_CHIP_CPU,
1895 .pme_ctr = 30,
1896 .pme_event = 3,
1897 .pme_chipno = 0,
1898 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1899 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1900 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1901 },
1902 /* P Counter 31 Event 0 */
1903 {
1904 .pme_name = "VOPS_STORE_ALLOC",
1905 .pme_desc = "Number of selected vector stores references that were marked allocate (cache line requests count as 1).",
1906 .pme_code = 124,
1907 .pme_flags = 0x0,
1908 .pme_numasks = 0,
1909 .pme_chip = PME_CRAYX2_CHIP_CPU,
1910 .pme_ctr = 31,
1911 .pme_event = 0,
1912 .pme_chipno = 0,
1913 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1914 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1915 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1916 },
1917 /* P Counter 31 Event 1 */
1918 {
1919 .pme_name = "BRANCH_TAKEN",
1920 .pme_desc = "Number of taken branches.",
1921 .pme_code = 125,
1922 .pme_flags = 0x0,
1923 .pme_numasks = 0,
1924 .pme_chip = PME_CRAYX2_CHIP_CPU,
1925 .pme_ctr = 31,
1926 .pme_event = 1,
1927 .pme_chipno = 0,
1928 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1929 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1930 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1931 },
1932 /* P Counter 31 Event 2 */
1933 {
1934 .pme_name = "INST_LSYNCSV",
1935 .pme_desc = "Number of graduated Lsync SV instructions.",
1936 .pme_code = 126,
1937 .pme_flags = 0x0,
1938 .pme_numasks = 0,
1939 .pme_chip = PME_CRAYX2_CHIP_CPU,
1940 .pme_ctr = 31,
1941 .pme_event = 2,
1942 .pme_chipno = 0,
1943 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1944 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1945 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1946 },
1947 /* P Counter 31 Event 3 */
1948 {
1949 .pme_name = "STALL_VDU_SCM_VU",
1950 .pme_desc = "CPs VDU stalled waiting for scalar commit and VU has no valid instruction.",
1951 .pme_code = 127,
1952 .pme_flags = 0x0,
1953 .pme_numasks = 0,
1954 .pme_chip = PME_CRAYX2_CHIP_CPU,
1955 .pme_ctr = 31,
1956 .pme_event = 3,
1957 .pme_chipno = 0,
1958 .pme_base = PMU_CRAYX2_CPU_PMD_BASE,
1959 .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP,
1960 .pme_nchips = PME_CRAYX2_CPU_CHIPS
1961 },
1962 /* C Counter 0 Event 0 */
1963 {
1964 .pme_name = "REQUESTS",
1965 .pme_desc = "Processor requests processed.",
1966 .pme_code = 128,
1967 .pme_flags = 0x0,
1968 .pme_numasks = 0,
1969 .pme_chip = PME_CRAYX2_CHIP_CACHE,
1970 .pme_ctr = 0,
1971 .pme_event = 0,
1972 .pme_chipno = 0,
1973 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
1974 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
1975 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
1976 },
1977 /* C Counter 0 Event 1 */
1978 {
1979 .pme_name = "L2_MISSES",
1980 .pme_desc = "Cache line allocations.",
1981 .pme_code = 129,
1982 .pme_flags = 0x0,
1983 .pme_numasks = 0,
1984 .pme_chip = PME_CRAYX2_CHIP_CACHE,
1985 .pme_ctr = 0,
1986 .pme_event = 1,
1987 .pme_chipno = 0,
1988 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
1989 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
1990 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
1991 },
1992 /* C Counter 0 Event 2 */
1993 {
1994 .pme_name = "M_OUT_BUSY",
1995 .pme_desc = "Cycles W chip output port busy.",
1996 .pme_code = 130,
1997 .pme_flags = 0x0,
1998 .pme_numasks = 0,
1999 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2000 .pme_ctr = 0,
2001 .pme_event = 2,
2002 .pme_chipno = 0,
2003 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2004 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2005 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2006 },
2007 /* C Counter 0 Event 3 */
2008 {
2009 .pme_name = "REPLAYED",
2010 .pme_desc = "Requests sent to replay queue.",
2011 .pme_code = 131,
2012 .pme_flags = 0x0,
2013 .pme_numasks = 0,
2014 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2015 .pme_ctr = 0,
2016 .pme_event = 3,
2017 .pme_chipno = 0,
2018 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2019 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2020 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2021 },
2022 /* C Counter 1 Event 0 */
2023 {
2024 .pme_name = "ALLOC_REQUESTS",
2025 .pme_desc = "Allocating requests (Read, ReadUC, ReadShared, ReadUCShared, ReadMod, SWrite, VWrite).",
2026 .pme_code = 132,
2027 .pme_flags = 0x0,
2028 .pme_numasks = 0,
2029 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2030 .pme_ctr = 1,
2031 .pme_event = 0,
2032 .pme_chipno = 0,
2033 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2034 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2035 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2036 },
2037 /* C Counter 1 Event 1 */
2038 {
2039 .pme_name = "<C:1:1>",
2040 .pme_desc = "<NA>",
2041 .pme_code = 133,
2042 .pme_flags = 0x0,
2043 .pme_numasks = 0,
2044 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2045 .pme_ctr = 1,
2046 .pme_event = 1,
2047 .pme_chipno = 0,
2048 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2049 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2050 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2051 },
2052 /* C Counter 1 Event 2 */
2053 {
2054 .pme_name = "M_OUT_BLOCK",
2055 .pme_desc = "CyclesWchip output port blocked (something to send but no flow control credits).",
2056 .pme_code = 134,
2057 .pme_flags = 0x0,
2058 .pme_numasks = 0,
2059 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2060 .pme_ctr = 1,
2061 .pme_event = 2,
2062 .pme_chipno = 0,
2063 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2064 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2065 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2066 },
2067 /* C Counter 1 Event 3 */
2068 {
2069 .pme_name = "LS/VS",
2070 .pme_desc = "Replayed Ls or Vs Requests sent to the replay queue.",
2071 .pme_code = 135,
2072 .pme_flags = 0x0,
2073 .pme_numasks = 0,
2074 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2075 .pme_ctr = 1,
2076 .pme_event = 3,
2077 .pme_chipno = 0,
2078 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2079 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2080 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2081 },
2082 /* C Counter 2 Event 0 */
2083 {
2084 .pme_name = "DWORDS_ALLOCATED",
2085 .pme_desc = "Dwords written into L2 from L3 (excluding updates).",
2086 .pme_code = 136,
2087 .pme_flags = 0x0,
2088 .pme_numasks = 0,
2089 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2090 .pme_ctr = 2,
2091 .pme_event = 0,
2092 .pme_chipno = 0,
2093 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2094 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2095 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2096 },
2097 /* C Counter 2 Event 1 */
2098 {
2099 .pme_name = "<C:2:1>",
2100 .pme_desc = "<NA>",
2101 .pme_code = 137,
2102 .pme_flags = 0x0,
2103 .pme_numasks = 0,
2104 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2105 .pme_ctr = 2,
2106 .pme_event = 1,
2107 .pme_chipno = 0,
2108 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2109 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2110 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2111 },
2112 /* C Counter 2 Event 2 */
2113 {
2114 .pme_name = "NW_OUT_BUSY",
2115 .pme_desc = "Cycles NIF output port busy.",
2116 .pme_code = 138,
2117 .pme_flags = 0x0,
2118 .pme_numasks = 0,
2119 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2120 .pme_ctr = 2,
2121 .pme_event = 2,
2122 .pme_chipno = 0,
2123 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2124 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2125 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2126 },
2127 /* C Counter 2 Event 3 */
2128 {
2129 .pme_name = "REPLAY_PENDING",
2130 .pme_desc = "Requests sent to replay queue because the line was in PendingReq state.",
2131 .pme_code = 139,
2132 .pme_flags = 0x0,
2133 .pme_numasks = 0,
2134 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2135 .pme_ctr = 2,
2136 .pme_event = 3,
2137 .pme_chipno = 0,
2138 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2139 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2140 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2141 },
2142 /* C Counter 3 Event 0 */
2143 {
2144 .pme_name = "DWORDS_EVICTED",
2145 .pme_desc = "Dwords written back to L3.",
2146 .pme_code = 140,
2147 .pme_flags = 0x0,
2148 .pme_numasks = 0,
2149 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2150 .pme_ctr = 3,
2151 .pme_event = 0,
2152 .pme_chipno = 0,
2153 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2154 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2155 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2156 },
2157 /* C Counter 3 Event 1 */
2158 {
2159 .pme_name = "CACHE_LINE_EVICTIONS",
2160 .pme_desc = "Cache lines evicted due to new allocations.",
2161 .pme_code = 141,
2162 .pme_flags = 0x0,
2163 .pme_numasks = 0,
2164 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2165 .pme_ctr = 3,
2166 .pme_event = 1,
2167 .pme_chipno = 0,
2168 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2169 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2170 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2171 },
2172 /* C Counter 3 Event 2 */
2173 {
2174 .pme_name = "NW_OUT_BLOCK",
2175 .pme_desc = "Cycles NIF output port blocked (something to send but no flow control credits).",
2176 .pme_code = 142,
2177 .pme_flags = 0x0,
2178 .pme_numasks = 0,
2179 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2180 .pme_ctr = 3,
2181 .pme_event = 2,
2182 .pme_chipno = 0,
2183 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2184 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2185 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2186 },
2187 /* C Counter 3 Event 3 */
2188 {
2189 .pme_name = "REPLAY_ALLOC",
2190 .pme_desc = "Requests sent to replay queue because a line could not be allocated due to all ways pending.",
2191 .pme_code = 143,
2192 .pme_flags = 0x0,
2193 .pme_numasks = 0,
2194 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2195 .pme_ctr = 3,
2196 .pme_event = 3,
2197 .pme_chipno = 0,
2198 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2199 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2200 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2201 },
2202 /* C Counter 4 Event 0 */
2203 {
2204 .pme_name = "ALLOC_WRITE_TO_L2",
2205 .pme_desc = "Dwords written to L2 by local allocating write requests.",
2206 .pme_code = 144,
2207 .pme_flags = 0x0,
2208 .pme_numasks = 0,
2209 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2210 .pme_ctr = 4,
2211 .pme_event = 0,
2212 .pme_chipno = 0,
2213 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2214 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2215 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2216 },
2217 /* C Counter 4 Event 1 */
2218 {
2219 .pme_name = "DROPS",
2220 .pme_desc = "Drops sent to directory.",
2221 .pme_code = 145,
2222 .pme_flags = 0x0,
2223 .pme_numasks = 0,
2224 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2225 .pme_ctr = 4,
2226 .pme_event = 1,
2227 .pme_chipno = 0,
2228 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2229 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2230 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2231 },
2232 /* C Counter 4 Event 2 */
2233 {
2234 .pme_name = "<C:4:2>",
2235 .pme_desc = "<NA>",
2236 .pme_code = 146,
2237 .pme_flags = 0x0,
2238 .pme_numasks = 0,
2239 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2240 .pme_ctr = 4,
2241 .pme_event = 2,
2242 .pme_chipno = 0,
2243 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2244 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2245 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2246 },
2247 /* C Counter 4 Event 3 */
2248 {
2249 .pme_name = "REPLAY_WAKEUPS",
2250 .pme_desc = "Replay queue wakeups.",
2251 .pme_code = 147,
2252 .pme_flags = 0x0,
2253 .pme_numasks = 0,
2254 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2255 .pme_ctr = 4,
2256 .pme_event = 3,
2257 .pme_chipno = 0,
2258 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2259 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2260 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2261 },
2262 /* C Counter 5 Event 0 */
2263 {
2264 .pme_name = "NON_ALLOC_WRITE_TO_L2",
2265 .pme_desc = "Dwords written to L2 by local non-allocating write requests.",
2266 .pme_code = 148,
2267 .pme_flags = 0x0,
2268 .pme_numasks = 0,
2269 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2270 .pme_ctr = 5,
2271 .pme_event = 0,
2272 .pme_chipno = 0,
2273 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2274 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2275 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2276 },
2277 /* C Counter 5 Event 1 */
2278 {
2279 .pme_name = "WRITE_BACKS",
2280 .pme_desc = "WriteBacks sent to directory.",
2281 .pme_code = 149,
2282 .pme_flags = 0x0,
2283 .pme_numasks = 0,
2284 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2285 .pme_ctr = 5,
2286 .pme_event = 1,
2287 .pme_chipno = 0,
2288 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2289 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2290 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2291 },
2292 /* C Counter 5 Event 2 */
2293 {
2294 .pme_name = "<C:5:2>",
2295 .pme_desc = "<NA>",
2296 .pme_code = 150,
2297 .pme_flags = 0x0,
2298 .pme_numasks = 0,
2299 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2300 .pme_ctr = 5,
2301 .pme_event = 2,
2302 .pme_chipno = 0,
2303 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2304 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2305 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2306 },
2307 /* C Counter 5 Event 3 */
2308 {
2309 .pme_name = "REPLAY_MATCHES",
2310 .pme_desc = "Requests matched during replay wakeups (Replay_Matches/Replay_Wakeups=avg. number of matches per wakeup).",
2311 .pme_code = 151,
2312 .pme_flags = 0x0,
2313 .pme_numasks = 0,
2314 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2315 .pme_ctr = 5,
2316 .pme_event = 3,
2317 .pme_chipno = 0,
2318 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2319 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2320 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2321 },
2322 /* C Counter 6 Event 0 */
2323 {
2324 .pme_name = "NON_ALLOC_WRITE_TO_L3",
2325 .pme_desc = "Dwords written to L3 by local non-allocating write requests.",
2326 .pme_code = 152,
2327 .pme_flags = 0x0,
2328 .pme_numasks = 0,
2329 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2330 .pme_ctr = 6,
2331 .pme_event = 0,
2332 .pme_chipno = 0,
2333 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2334 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2335 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2336 },
2337 /* C Counter 6 Event 1 */
2338 {
2339 .pme_name = "FWD_REQ",
2340 .pme_desc = "Forwarded requests received (FlushReq, FwdRead, FwdReadShared, FwdGet).",
2341 .pme_code = 153,
2342 .pme_flags = 0x0,
2343 .pme_numasks = 0,
2344 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2345 .pme_ctr = 6,
2346 .pme_event = 1,
2347 .pme_chipno = 0,
2348 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2349 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2350 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2351 },
2352 /* C Counter 6 Event 2 */
2353 {
2354 .pme_name = "<C:6:2>",
2355 .pme_desc = "<NA>",
2356 .pme_code = 154,
2357 .pme_flags = 0x0,
2358 .pme_numasks = 0,
2359 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2360 .pme_ctr = 6,
2361 .pme_event = 2,
2362 .pme_chipno = 0,
2363 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2364 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2365 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2366 },
2367 /* C Counter 6 Event 3 */
2368 {
2369 .pme_name = "<C:6:3>",
2370 .pme_desc = "<NA>",
2371 .pme_code = 155,
2372 .pme_flags = 0x0,
2373 .pme_numasks = 0,
2374 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2375 .pme_ctr = 6,
2376 .pme_event = 3,
2377 .pme_chipno = 0,
2378 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2379 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2380 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2381 },
2382 /* C Counter 7 Event 0 */
2383 {
2384 .pme_name = "ALLOC_READ_FROM_L2",
2385 .pme_desc = "Dwords read from L2 by local allocating read requests.",
2386 .pme_code = 156,
2387 .pme_flags = 0x0,
2388 .pme_numasks = 0,
2389 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2390 .pme_ctr = 7,
2391 .pme_event = 0,
2392 .pme_chipno = 0,
2393 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2394 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2395 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2396 },
2397 /* C Counter 7 Event 1 */
2398 {
2399 .pme_name = "FWD_READ_ALL",
2400 .pme_desc = "FwdReads and FwdReadShared received.",
2401 .pme_code = 157,
2402 .pme_flags = 0x0,
2403 .pme_numasks = 0,
2404 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2405 .pme_ctr = 7,
2406 .pme_event = 1,
2407 .pme_chipno = 0,
2408 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2409 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2410 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2411 },
2412 /* C Counter 7 Event 2 */
2413 {
2414 .pme_name = "STALL_RP_FULL_NW",
2415 .pme_desc = "Cycles NW request queue stalled due to replay queue full.",
2416 .pme_code = 158,
2417 .pme_flags = 0x0,
2418 .pme_numasks = 0,
2419 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2420 .pme_ctr = 7,
2421 .pme_event = 2,
2422 .pme_chipno = 0,
2423 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2424 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2425 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2426 },
2427 /* C Counter 7 Event 3 */
2428 {
2429 .pme_name = "ALLOC_NO_FILL",
2430 .pme_desc = "ReadMods sent to directory when the entire line is dirty.",
2431 .pme_code = 159,
2432 .pme_flags = 0x0,
2433 .pme_numasks = 0,
2434 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2435 .pme_ctr = 7,
2436 .pme_event = 3,
2437 .pme_chipno = 0,
2438 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2439 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2440 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2441 },
2442 /* C Counter 8 Event 0 */
2443 {
2444 .pme_name = "NON_ALLOC_READ_FROM_L2",
2445 .pme_desc = "Dwords read from L2 by local non-allocating read requests.",
2446 .pme_code = 160,
2447 .pme_flags = 0x0,
2448 .pme_numasks = 0,
2449 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2450 .pme_ctr = 8,
2451 .pme_event = 0,
2452 .pme_chipno = 0,
2453 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2454 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2455 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2456 },
2457 /* C Counter 8 Event 1 */
2458 {
2459 .pme_name = "FWD_READ_SHARED_RECV",
2460 .pme_desc = "FwdReadShareds received.",
2461 .pme_code = 161,
2462 .pme_flags = 0x0,
2463 .pme_numasks = 0,
2464 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2465 .pme_ctr = 8,
2466 .pme_event = 1,
2467 .pme_chipno = 0,
2468 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2469 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2470 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2471 },
2472 /* C Counter 8 Event 2 */
2473 {
2474 .pme_name = "STALL_RP_FULL_PROC",
2475 .pme_desc = "Cycles Ls/Vs request queue stalled due to replay queue full.",
2476 .pme_code = 162,
2477 .pme_flags = 0x0,
2478 .pme_numasks = 0,
2479 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2480 .pme_ctr = 8,
2481 .pme_event = 2,
2482 .pme_chipno = 0,
2483 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2484 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2485 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2486 },
2487 /* C Counter 8 Event 3 */
2488 {
2489 .pme_name = "UPGRADES",
2490 .pme_desc = "ReadMods sent to directory when the line was currently in ShClean state.",
2491 .pme_code = 163,
2492 .pme_flags = 0x0,
2493 .pme_numasks = 0,
2494 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2495 .pme_ctr = 8,
2496 .pme_event = 3,
2497 .pme_chipno = 0,
2498 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2499 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2500 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2501 },
2502 /* C Counter 9 Event 0 */
2503 {
2504 .pme_name = "NON_ALLOC_READ_FROM_L3",
2505 .pme_desc = "Dwords read from L3 by local non-allocating read requests.",
2506 .pme_code = 164,
2507 .pme_flags = 0x0,
2508 .pme_numasks = 0,
2509 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2510 .pme_ctr = 9,
2511 .pme_event = 0,
2512 .pme_chipno = 0,
2513 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2514 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2515 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2516 },
2517 /* C Counter 9 Event 1 */
2518 {
2519 .pme_name = "FWD_GET_RECV",
2520 .pme_desc = "FwdGets received.",
2521 .pme_code = 165,
2522 .pme_flags = 0x0,
2523 .pme_numasks = 0,
2524 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2525 .pme_ctr = 9,
2526 .pme_event = 1,
2527 .pme_chipno = 0,
2528 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2529 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2530 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2531 },
2532 /* C Counter 9 Event 2 */
2533 {
2534 .pme_name = "STALL_TB_FULL",
2535 .pme_desc = "Cycles bank request queue stalled due to transient buffer full.",
2536 .pme_code = 166,
2537 .pme_flags = 0x0,
2538 .pme_numasks = 0,
2539 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2540 .pme_ctr = 9,
2541 .pme_event = 2,
2542 .pme_chipno = 0,
2543 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2544 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2545 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2546 },
2547 /* C Counter 9 Event 3 */
2548 {
2549 .pme_name = "<C:9:3>",
2550 .pme_desc = "<NA>",
2551 .pme_code = 167,
2552 .pme_flags = 0x0,
2553 .pme_numasks = 0,
2554 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2555 .pme_ctr = 9,
2556 .pme_event = 3,
2557 .pme_chipno = 0,
2558 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2559 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2560 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2561 },
2562 /* C Counter 10 Event 0 */
2563 {
2564 .pme_name = "NETWORK_WRITE_TO_L2",
2565 .pme_desc = "Dwords written to L2 by remote write requests.",
2566 .pme_code = 168,
2567 .pme_flags = 0x0,
2568 .pme_numasks = 0,
2569 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2570 .pme_ctr = 10,
2571 .pme_event = 0,
2572 .pme_chipno = 0,
2573 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2574 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2575 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2576 },
2577 /* C Counter 10 Event 1 */
2578 {
2579 .pme_name = "FLUSH_REQ",
2580 .pme_desc = "FlushReqs received.",
2581 .pme_code = 169,
2582 .pme_flags = 0x0,
2583 .pme_numasks = 0,
2584 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2585 .pme_ctr = 10,
2586 .pme_event = 1,
2587 .pme_chipno = 0,
2588 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2589 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2590 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2591 },
2592 /* C Counter 10 Event 2 */
2593 {
2594 .pme_name = "STALL_VWRITENA",
2595 .pme_desc = "Cycles bank request queue stalled due to VWriteNA bit being set.",
2596 .pme_code = 170,
2597 .pme_flags = 0x0,
2598 .pme_numasks = 0,
2599 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2600 .pme_ctr = 10,
2601 .pme_event = 2,
2602 .pme_chipno = 0,
2603 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2604 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2605 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2606 },
2607 /* C Counter 10 Event 3 */
2608 {
2609 .pme_name = "<C:10:3>",
2610 .pme_desc = "<NA>",
2611 .pme_code = 171,
2612 .pme_flags = 0x0,
2613 .pme_numasks = 0,
2614 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2615 .pme_ctr = 10,
2616 .pme_event = 3,
2617 .pme_chipno = 0,
2618 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2619 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2620 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2621 },
2622 /* C Counter 11 Event 0 */
2623 {
2624 .pme_name = "NETWORK_WRITE_TO_L3",
2625 .pme_desc = "Dwords written to L3 by remote write requests.",
2626 .pme_code = 172,
2627 .pme_flags = 0x0,
2628 .pme_numasks = 0,
2629 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2630 .pme_ctr = 11,
2631 .pme_event = 0,
2632 .pme_chipno = 0,
2633 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2634 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2635 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2636 },
2637 /* C Counter 11 Event 1 */
2638 {
2639 .pme_name = "UPDATES_RECV",
2640 .pme_desc = "Updates received.",
2641 .pme_code = 173,
2642 .pme_flags = 0x0,
2643 .pme_numasks = 0,
2644 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2645 .pme_ctr = 11,
2646 .pme_event = 1,
2647 .pme_chipno = 0,
2648 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2649 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2650 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2651 },
2652 /* C Counter 11 Event 2 */
2653 {
2654 .pme_name = "PROT_ENGINE_IDLE_NO_REQUEST",
2655 .pme_desc = "Cycles protocol engine idle due to no new requests to process.",
2656 .pme_code = 174,
2657 .pme_flags = 0x0,
2658 .pme_numasks = 0,
2659 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2660 .pme_ctr = 11,
2661 .pme_event = 2,
2662 .pme_chipno = 0,
2663 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2664 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2665 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2666 },
2667 /* C Counter 11 Event 3 */
2668 {
2669 .pme_name = "READ_DATA_TO_VECTOR_UNIT_PIPE_0_3",
2670 .pme_desc = "Swords delivered to vector unit via pipes 0 - 3.",
2671 .pme_code = 175,
2672 .pme_flags = 0x0,
2673 .pme_numasks = 0,
2674 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2675 .pme_ctr = 11,
2676 .pme_event = 3,
2677 .pme_chipno = 0,
2678 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2679 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2680 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2681 },
2682 /* C Counter 12 Event 0 */
2683 {
2684 .pme_name = "NETWORK_READ_FROM_L2",
2685 .pme_desc = "Dwords read from L2 by remote read requests.",
2686 .pme_code = 176,
2687 .pme_flags = 0x0,
2688 .pme_numasks = 0,
2689 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2690 .pme_ctr = 12,
2691 .pme_event = 0,
2692 .pme_chipno = 0,
2693 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2694 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2695 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2696 },
2697 /* C Counter 12 Event 1 */
2698 {
2699 .pme_name = "<C:12:1>",
2700 .pme_desc = "<NA>",
2701 .pme_code = 177,
2702 .pme_flags = 0x0,
2703 .pme_numasks = 0,
2704 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2705 .pme_ctr = 12,
2706 .pme_event = 1,
2707 .pme_chipno = 0,
2708 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2709 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2710 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2711 },
2712 /* C Counter 12 Event 2 */
2713 {
2714 .pme_name = "UPDATE_NACK_SENT",
2715 .pme_desc = "UpdateNacks sent.",
2716 .pme_code = 178,
2717 .pme_flags = 0x0,
2718 .pme_numasks = 0,
2719 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2720 .pme_ctr = 12,
2721 .pme_event = 2,
2722 .pme_chipno = 0,
2723 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2724 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2725 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2726 },
2727 /* C Counter 12 Event 3 */
2728 {
2729 .pme_name = "READ_DATA_TO_VECTOR_UNIT_PIPE_4_7",
2730 .pme_desc = "Swords delivered to vector unit via pipes 4 - 7.",
2731 .pme_code = 179,
2732 .pme_flags = 0x0,
2733 .pme_numasks = 0,
2734 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2735 .pme_ctr = 12,
2736 .pme_event = 3,
2737 .pme_chipno = 0,
2738 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2739 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2740 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2741 },
2742 /* C Counter 13 Event 0 */
2743 {
2744 .pme_name = "NETWORK_READ_FROM_L3",
2745 .pme_desc = "Dwords read from L3 by remote read requests.",
2746 .pme_code = 180,
2747 .pme_flags = 0x0,
2748 .pme_numasks = 0,
2749 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2750 .pme_ctr = 13,
2751 .pme_event = 0,
2752 .pme_chipno = 0,
2753 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2754 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2755 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2756 },
2757 /* C Counter 13 Event 1 */
2758 {
2759 .pme_name = "NACKS_SENT",
2760 .pme_desc = "FlushAcks and UpdateNacks sent (these happen when there's a race b/w a forwarded request and an eviction by the current owner).",
2761 .pme_code = 181,
2762 .pme_flags = 0x0,
2763 .pme_numasks = 0,
2764 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2765 .pme_ctr = 13,
2766 .pme_event = 1,
2767 .pme_chipno = 0,
2768 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2769 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2770 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2771 },
2772 /* C Counter 13 Event 2 */
2773 {
2774 .pme_name = "INVAL_RECV",
2775 .pme_desc = "Inval packets received from the directory.",
2776 .pme_code = 182,
2777 .pme_flags = 0x0,
2778 .pme_numasks = 0,
2779 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2780 .pme_ctr = 13,
2781 .pme_event = 2,
2782 .pme_chipno = 0,
2783 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2784 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2785 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2786 },
2787 /* C Counter 13 Event 3 */
2788 {
2789 .pme_name = "READ_DATA_TO_SCALAR_UNIT",
2790 .pme_desc = "Dwords delivered to scalar unit.",
2791 .pme_code = 183,
2792 .pme_flags = 0x0,
2793 .pme_numasks = 0,
2794 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2795 .pme_ctr = 13,
2796 .pme_event = 3,
2797 .pme_chipno = 0,
2798 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2799 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2800 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2801 },
2802 /* C Counter 14 Event 0 */
2803 {
2804 .pme_name = "REMOTE_READS",
2805 .pme_desc = "Dwords read from remote nodes.",
2806 .pme_code = 184,
2807 .pme_flags = 0x0,
2808 .pme_numasks = 0,
2809 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2810 .pme_ctr = 14,
2811 .pme_event = 0,
2812 .pme_chipno = 0,
2813 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2814 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2815 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2816 },
2817 /* C Counter 14 Event 1 */
2818 {
2819 .pme_name = "LOCAL_INVAL",
2820 .pme_desc = "Local writes that cause invals of other Dcaches.",
2821 .pme_code = 185,
2822 .pme_flags = 0x0,
2823 .pme_numasks = 0,
2824 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2825 .pme_ctr = 14,
2826 .pme_event = 1,
2827 .pme_chipno = 0,
2828 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2829 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2830 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2831 },
2832 /* C Counter 14 Event 2 */
2833 {
2834 .pme_name = "MARKED_REQS",
2835 .pme_desc = "Memory requests sent with TID 0.",
2836 .pme_code = 186,
2837 .pme_flags = 0x0,
2838 .pme_numasks = 0,
2839 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2840 .pme_ctr = 14,
2841 .pme_event = 2,
2842 .pme_chipno = 0,
2843 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2844 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2845 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2846 },
2847 /* C Counter 14 Event 3 */
2848 {
2849 .pme_name = "READ_DATA_TO_ICACHE",
2850 .pme_desc = "Dwords delivered to Icache.",
2851 .pme_code = 187,
2852 .pme_flags = 0x0,
2853 .pme_numasks = 0,
2854 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2855 .pme_ctr = 14,
2856 .pme_event = 3,
2857 .pme_chipno = 0,
2858 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2859 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2860 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2861 },
2862 /* C Counter 15 Event 0 */
2863 {
2864 .pme_name = "REMOTE_WRITES",
2865 .pme_desc = "Dwords written to remote nodes.",
2866 .pme_code = 188,
2867 .pme_flags = 0x0,
2868 .pme_numasks = 0,
2869 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2870 .pme_ctr = 15,
2871 .pme_event = 0,
2872 .pme_chipno = 0,
2873 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2874 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2875 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2876 },
2877 /* C Counter 15 Event 1 */
2878 {
2879 .pme_name = "DCACHE_INVAL_EVENTS",
2880 .pme_desc = "State transitions (evictions, directory Invals or forwards, processor writes) requiring Dcache invals.",
2881 .pme_code = 189,
2882 .pme_flags = 0x0,
2883 .pme_numasks = 0,
2884 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2885 .pme_ctr = 15,
2886 .pme_event = 1,
2887 .pme_chipno = 0,
2888 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2889 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2890 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2891 },
2892 /* C Counter 15 Event 2 */
2893 {
2894 .pme_name = "MARKED_CYCLES",
2895 .pme_desc = "Cycles with a TID 0 request outstanding.",
2896 .pme_code = 190,
2897 .pme_flags = 0x0,
2898 .pme_numasks = 0,
2899 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2900 .pme_ctr = 15,
2901 .pme_event = 2,
2902 .pme_chipno = 0,
2903 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2904 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2905 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2906 },
2907 /* C Counter 15 Event 3 */
2908 {
2909 .pme_name = "READ_DATA_TO_NIF",
2910 .pme_desc = "Dwords delivered to NIF.",
2911 .pme_code = 191,
2912 .pme_flags = 0x0,
2913 .pme_numasks = 0,
2914 .pme_chip = PME_CRAYX2_CHIP_CACHE,
2915 .pme_ctr = 15,
2916 .pme_event = 3,
2917 .pme_chipno = 0,
2918 .pme_base = PMU_CRAYX2_CACHE_PMD_BASE,
2919 .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP,
2920 .pme_nchips = PME_CRAYX2_CACHE_CHIPS
2921 },
2922 /* M Counter 0 Event 0 */
2923 {
2924 .pme_name = "W_IN_IDLE_0@0",
2925 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 0)",
2926 .pme_code = 192,
2927 .pme_flags = 0x0,
2928 .pme_numasks = 0,
2929 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
2930 .pme_ctr = 0,
2931 .pme_event = 0,
2932 .pme_chipno = 0,
2933 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
2934 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
2935 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
2936 },
2937 {
2938 .pme_name = "W_IN_IDLE_0@1",
2939 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 1)",
2940 .pme_code = 193,
2941 .pme_flags = 0x0,
2942 .pme_numasks = 0,
2943 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
2944 .pme_ctr = 0,
2945 .pme_event = 0,
2946 .pme_chipno = 1,
2947 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
2948 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
2949 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
2950 },
2951 {
2952 .pme_name = "W_IN_IDLE_0@2",
2953 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 2)",
2954 .pme_code = 194,
2955 .pme_flags = 0x0,
2956 .pme_numasks = 0,
2957 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
2958 .pme_ctr = 0,
2959 .pme_event = 0,
2960 .pme_chipno = 2,
2961 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
2962 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
2963 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
2964 },
2965 {
2966 .pme_name = "W_IN_IDLE_0@3",
2967 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 3)",
2968 .pme_code = 195,
2969 .pme_flags = 0x0,
2970 .pme_numasks = 0,
2971 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
2972 .pme_ctr = 0,
2973 .pme_event = 0,
2974 .pme_chipno = 3,
2975 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
2976 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
2977 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
2978 },
2979 {
2980 .pme_name = "W_IN_IDLE_0@4",
2981 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 4)",
2982 .pme_code = 196,
2983 .pme_flags = 0x0,
2984 .pme_numasks = 0,
2985 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
2986 .pme_ctr = 0,
2987 .pme_event = 0,
2988 .pme_chipno = 4,
2989 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
2990 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
2991 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
2992 },
2993 {
2994 .pme_name = "W_IN_IDLE_0@5",
2995 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 5)",
2996 .pme_code = 197,
2997 .pme_flags = 0x0,
2998 .pme_numasks = 0,
2999 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3000 .pme_ctr = 0,
3001 .pme_event = 0,
3002 .pme_chipno = 5,
3003 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3004 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3005 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3006 },
3007 {
3008 .pme_name = "W_IN_IDLE_0@6",
3009 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 6)",
3010 .pme_code = 198,
3011 .pme_flags = 0x0,
3012 .pme_numasks = 0,
3013 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3014 .pme_ctr = 0,
3015 .pme_event = 0,
3016 .pme_chipno = 6,
3017 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3018 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3019 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3020 },
3021 {
3022 .pme_name = "W_IN_IDLE_0@7",
3023 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 7)",
3024 .pme_code = 199,
3025 .pme_flags = 0x0,
3026 .pme_numasks = 0,
3027 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3028 .pme_ctr = 0,
3029 .pme_event = 0,
3030 .pme_chipno = 7,
3031 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3032 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3033 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3034 },
3035 {
3036 .pme_name = "W_IN_IDLE_0@8",
3037 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 8)",
3038 .pme_code = 200,
3039 .pme_flags = 0x0,
3040 .pme_numasks = 0,
3041 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3042 .pme_ctr = 0,
3043 .pme_event = 0,
3044 .pme_chipno = 8,
3045 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3046 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3047 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3048 },
3049 {
3050 .pme_name = "W_IN_IDLE_0@9",
3051 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 9)",
3052 .pme_code = 201,
3053 .pme_flags = 0x0,
3054 .pme_numasks = 0,
3055 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3056 .pme_ctr = 0,
3057 .pme_event = 0,
3058 .pme_chipno = 9,
3059 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3060 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3061 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3062 },
3063 {
3064 .pme_name = "W_IN_IDLE_0@10",
3065 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 10)",
3066 .pme_code = 202,
3067 .pme_flags = 0x0,
3068 .pme_numasks = 0,
3069 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3070 .pme_ctr = 0,
3071 .pme_event = 0,
3072 .pme_chipno = 10,
3073 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3074 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3075 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3076 },
3077 {
3078 .pme_name = "W_IN_IDLE_0@11",
3079 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 11)",
3080 .pme_code = 203,
3081 .pme_flags = 0x0,
3082 .pme_numasks = 0,
3083 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3084 .pme_ctr = 0,
3085 .pme_event = 0,
3086 .pme_chipno = 11,
3087 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3088 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3089 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3090 },
3091 {
3092 .pme_name = "W_IN_IDLE_0@12",
3093 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 12)",
3094 .pme_code = 204,
3095 .pme_flags = 0x0,
3096 .pme_numasks = 0,
3097 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3098 .pme_ctr = 0,
3099 .pme_event = 0,
3100 .pme_chipno = 12,
3101 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3102 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3103 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3104 },
3105 {
3106 .pme_name = "W_IN_IDLE_0@13",
3107 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 13)",
3108 .pme_code = 205,
3109 .pme_flags = 0x0,
3110 .pme_numasks = 0,
3111 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3112 .pme_ctr = 0,
3113 .pme_event = 0,
3114 .pme_chipno = 13,
3115 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3116 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3117 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3118 },
3119 {
3120 .pme_name = "W_IN_IDLE_0@14",
3121 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 14)",
3122 .pme_code = 206,
3123 .pme_flags = 0x0,
3124 .pme_numasks = 0,
3125 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3126 .pme_ctr = 0,
3127 .pme_event = 0,
3128 .pme_chipno = 14,
3129 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3130 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3131 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3132 },
3133 {
3134 .pme_name = "W_IN_IDLE_0@15",
3135 .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 15)",
3136 .pme_code = 207,
3137 .pme_flags = 0x0,
3138 .pme_numasks = 0,
3139 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3140 .pme_ctr = 0,
3141 .pme_event = 0,
3142 .pme_chipno = 15,
3143 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3144 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3145 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3146 },
3147 /* M Counter 0 Event 1 */
3148 {
3149 .pme_name = "STALL_REPLAY_FULL@0",
3150 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 0)",
3151 .pme_code = 208,
3152 .pme_flags = 0x0,
3153 .pme_numasks = 0,
3154 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3155 .pme_ctr = 0,
3156 .pme_event = 1,
3157 .pme_chipno = 0,
3158 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3159 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3160 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3161 },
3162 {
3163 .pme_name = "STALL_REPLAY_FULL@1",
3164 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 1)",
3165 .pme_code = 209,
3166 .pme_flags = 0x0,
3167 .pme_numasks = 0,
3168 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3169 .pme_ctr = 0,
3170 .pme_event = 1,
3171 .pme_chipno = 1,
3172 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3173 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3174 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3175 },
3176 {
3177 .pme_name = "STALL_REPLAY_FULL@2",
3178 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 2)",
3179 .pme_code = 210,
3180 .pme_flags = 0x0,
3181 .pme_numasks = 0,
3182 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3183 .pme_ctr = 0,
3184 .pme_event = 1,
3185 .pme_chipno = 2,
3186 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3187 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3188 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3189 },
3190 {
3191 .pme_name = "STALL_REPLAY_FULL@3",
3192 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 3)",
3193 .pme_code = 211,
3194 .pme_flags = 0x0,
3195 .pme_numasks = 0,
3196 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3197 .pme_ctr = 0,
3198 .pme_event = 1,
3199 .pme_chipno = 3,
3200 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3201 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3202 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3203 },
3204 {
3205 .pme_name = "STALL_REPLAY_FULL@4",
3206 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 4)",
3207 .pme_code = 212,
3208 .pme_flags = 0x0,
3209 .pme_numasks = 0,
3210 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3211 .pme_ctr = 0,
3212 .pme_event = 1,
3213 .pme_chipno = 4,
3214 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3215 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3216 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3217 },
3218 {
3219 .pme_name = "STALL_REPLAY_FULL@5",
3220 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 5)",
3221 .pme_code = 213,
3222 .pme_flags = 0x0,
3223 .pme_numasks = 0,
3224 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3225 .pme_ctr = 0,
3226 .pme_event = 1,
3227 .pme_chipno = 5,
3228 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3229 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3230 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3231 },
3232 {
3233 .pme_name = "STALL_REPLAY_FULL@6",
3234 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 6)",
3235 .pme_code = 214,
3236 .pme_flags = 0x0,
3237 .pme_numasks = 0,
3238 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3239 .pme_ctr = 0,
3240 .pme_event = 1,
3241 .pme_chipno = 6,
3242 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3243 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3244 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3245 },
3246 {
3247 .pme_name = "STALL_REPLAY_FULL@7",
3248 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 7)",
3249 .pme_code = 215,
3250 .pme_flags = 0x0,
3251 .pme_numasks = 0,
3252 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3253 .pme_ctr = 0,
3254 .pme_event = 1,
3255 .pme_chipno = 7,
3256 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3257 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3258 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3259 },
3260 {
3261 .pme_name = "STALL_REPLAY_FULL@8",
3262 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 8)",
3263 .pme_code = 216,
3264 .pme_flags = 0x0,
3265 .pme_numasks = 0,
3266 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3267 .pme_ctr = 0,
3268 .pme_event = 1,
3269 .pme_chipno = 8,
3270 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3271 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3272 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3273 },
3274 {
3275 .pme_name = "STALL_REPLAY_FULL@9",
3276 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 9)",
3277 .pme_code = 217,
3278 .pme_flags = 0x0,
3279 .pme_numasks = 0,
3280 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3281 .pme_ctr = 0,
3282 .pme_event = 1,
3283 .pme_chipno = 9,
3284 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3285 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3286 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3287 },
3288 {
3289 .pme_name = "STALL_REPLAY_FULL@10",
3290 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 10)",
3291 .pme_code = 218,
3292 .pme_flags = 0x0,
3293 .pme_numasks = 0,
3294 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3295 .pme_ctr = 0,
3296 .pme_event = 1,
3297 .pme_chipno = 10,
3298 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3299 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3300 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3301 },
3302 {
3303 .pme_name = "STALL_REPLAY_FULL@11",
3304 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 11)",
3305 .pme_code = 219,
3306 .pme_flags = 0x0,
3307 .pme_numasks = 0,
3308 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3309 .pme_ctr = 0,
3310 .pme_event = 1,
3311 .pme_chipno = 11,
3312 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3313 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3314 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3315 },
3316 {
3317 .pme_name = "STALL_REPLAY_FULL@12",
3318 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 12)",
3319 .pme_code = 220,
3320 .pme_flags = 0x0,
3321 .pme_numasks = 0,
3322 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3323 .pme_ctr = 0,
3324 .pme_event = 1,
3325 .pme_chipno = 12,
3326 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3327 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3328 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3329 },
3330 {
3331 .pme_name = "STALL_REPLAY_FULL@13",
3332 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 13)",
3333 .pme_code = 221,
3334 .pme_flags = 0x0,
3335 .pme_numasks = 0,
3336 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3337 .pme_ctr = 0,
3338 .pme_event = 1,
3339 .pme_chipno = 13,
3340 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3341 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3342 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3343 },
3344 {
3345 .pme_name = "STALL_REPLAY_FULL@14",
3346 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 14)",
3347 .pme_code = 222,
3348 .pme_flags = 0x0,
3349 .pme_numasks = 0,
3350 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3351 .pme_ctr = 0,
3352 .pme_event = 1,
3353 .pme_chipno = 14,
3354 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3355 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3356 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3357 },
3358 {
3359 .pme_name = "STALL_REPLAY_FULL@15",
3360 .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 15)",
3361 .pme_code = 223,
3362 .pme_flags = 0x0,
3363 .pme_numasks = 0,
3364 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3365 .pme_ctr = 0,
3366 .pme_event = 1,
3367 .pme_chipno = 15,
3368 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3369 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3370 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3371 },
3372 /* M Counter 0 Event 2 */
3373 {
3374 .pme_name = "W_OUT_IDLE_0@0",
3375 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 0)",
3376 .pme_code = 224,
3377 .pme_flags = 0x0,
3378 .pme_numasks = 0,
3379 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3380 .pme_ctr = 0,
3381 .pme_event = 2,
3382 .pme_chipno = 0,
3383 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3384 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3385 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3386 },
3387 {
3388 .pme_name = "W_OUT_IDLE_0@1",
3389 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 1)",
3390 .pme_code = 225,
3391 .pme_flags = 0x0,
3392 .pme_numasks = 0,
3393 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3394 .pme_ctr = 0,
3395 .pme_event = 2,
3396 .pme_chipno = 1,
3397 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3398 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3399 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3400 },
3401 {
3402 .pme_name = "W_OUT_IDLE_0@2",
3403 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 2)",
3404 .pme_code = 226,
3405 .pme_flags = 0x0,
3406 .pme_numasks = 0,
3407 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3408 .pme_ctr = 0,
3409 .pme_event = 2,
3410 .pme_chipno = 2,
3411 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3412 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3413 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3414 },
3415 {
3416 .pme_name = "W_OUT_IDLE_0@3",
3417 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 3)",
3418 .pme_code = 227,
3419 .pme_flags = 0x0,
3420 .pme_numasks = 0,
3421 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3422 .pme_ctr = 0,
3423 .pme_event = 2,
3424 .pme_chipno = 3,
3425 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3426 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3427 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3428 },
3429 {
3430 .pme_name = "W_OUT_IDLE_0@4",
3431 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 4)",
3432 .pme_code = 228,
3433 .pme_flags = 0x0,
3434 .pme_numasks = 0,
3435 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3436 .pme_ctr = 0,
3437 .pme_event = 2,
3438 .pme_chipno = 4,
3439 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3440 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3441 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3442 },
3443 {
3444 .pme_name = "W_OUT_IDLE_0@5",
3445 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 5)",
3446 .pme_code = 229,
3447 .pme_flags = 0x0,
3448 .pme_numasks = 0,
3449 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3450 .pme_ctr = 0,
3451 .pme_event = 2,
3452 .pme_chipno = 5,
3453 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3454 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3455 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3456 },
3457 {
3458 .pme_name = "W_OUT_IDLE_0@6",
3459 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 6)",
3460 .pme_code = 230,
3461 .pme_flags = 0x0,
3462 .pme_numasks = 0,
3463 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3464 .pme_ctr = 0,
3465 .pme_event = 2,
3466 .pme_chipno = 6,
3467 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3468 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3469 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3470 },
3471 {
3472 .pme_name = "W_OUT_IDLE_0@7",
3473 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 7)",
3474 .pme_code = 231,
3475 .pme_flags = 0x0,
3476 .pme_numasks = 0,
3477 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3478 .pme_ctr = 0,
3479 .pme_event = 2,
3480 .pme_chipno = 7,
3481 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3482 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3483 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3484 },
3485 {
3486 .pme_name = "W_OUT_IDLE_0@8",
3487 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 8)",
3488 .pme_code = 232,
3489 .pme_flags = 0x0,
3490 .pme_numasks = 0,
3491 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3492 .pme_ctr = 0,
3493 .pme_event = 2,
3494 .pme_chipno = 8,
3495 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3496 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3497 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3498 },
3499 {
3500 .pme_name = "W_OUT_IDLE_0@9",
3501 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 9)",
3502 .pme_code = 233,
3503 .pme_flags = 0x0,
3504 .pme_numasks = 0,
3505 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3506 .pme_ctr = 0,
3507 .pme_event = 2,
3508 .pme_chipno = 9,
3509 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3510 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3511 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3512 },
3513 {
3514 .pme_name = "W_OUT_IDLE_0@10",
3515 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 10)",
3516 .pme_code = 234,
3517 .pme_flags = 0x0,
3518 .pme_numasks = 0,
3519 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3520 .pme_ctr = 0,
3521 .pme_event = 2,
3522 .pme_chipno = 10,
3523 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3524 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3525 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3526 },
3527 {
3528 .pme_name = "W_OUT_IDLE_0@11",
3529 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 11)",
3530 .pme_code = 235,
3531 .pme_flags = 0x0,
3532 .pme_numasks = 0,
3533 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3534 .pme_ctr = 0,
3535 .pme_event = 2,
3536 .pme_chipno = 11,
3537 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3538 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3539 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3540 },
3541 {
3542 .pme_name = "W_OUT_IDLE_0@12",
3543 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 12)",
3544 .pme_code = 236,
3545 .pme_flags = 0x0,
3546 .pme_numasks = 0,
3547 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3548 .pme_ctr = 0,
3549 .pme_event = 2,
3550 .pme_chipno = 12,
3551 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3552 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3553 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3554 },
3555 {
3556 .pme_name = "W_OUT_IDLE_0@13",
3557 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 13)",
3558 .pme_code = 237,
3559 .pme_flags = 0x0,
3560 .pme_numasks = 0,
3561 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3562 .pme_ctr = 0,
3563 .pme_event = 2,
3564 .pme_chipno = 13,
3565 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3566 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3567 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3568 },
3569 {
3570 .pme_name = "W_OUT_IDLE_0@14",
3571 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 14)",
3572 .pme_code = 238,
3573 .pme_flags = 0x0,
3574 .pme_numasks = 0,
3575 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3576 .pme_ctr = 0,
3577 .pme_event = 2,
3578 .pme_chipno = 14,
3579 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3580 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3581 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3582 },
3583 {
3584 .pme_name = "W_OUT_IDLE_0@15",
3585 .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 15)",
3586 .pme_code = 239,
3587 .pme_flags = 0x0,
3588 .pme_numasks = 0,
3589 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3590 .pme_ctr = 0,
3591 .pme_event = 2,
3592 .pme_chipno = 15,
3593 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3594 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3595 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3596 },
3597 /* M Counter 0 Event 3 */
3598 {
3599 .pme_name = "<M:0:3>@0",
3600 .pme_desc = "<NA>",
3601 .pme_code = 240,
3602 .pme_flags = 0x0,
3603 .pme_numasks = 0,
3604 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3605 .pme_ctr = 0,
3606 .pme_event = 3,
3607 .pme_chipno = 0,
3608 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3609 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3610 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3611 },
3612 {
3613 .pme_name = "<M:0:3>@1",
3614 .pme_desc = "<NA>",
3615 .pme_code = 241,
3616 .pme_flags = 0x0,
3617 .pme_numasks = 0,
3618 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3619 .pme_ctr = 0,
3620 .pme_event = 3,
3621 .pme_chipno = 1,
3622 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3623 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3624 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3625 },
3626 {
3627 .pme_name = "<M:0:3>@2",
3628 .pme_desc = "<NA>",
3629 .pme_code = 242,
3630 .pme_flags = 0x0,
3631 .pme_numasks = 0,
3632 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3633 .pme_ctr = 0,
3634 .pme_event = 3,
3635 .pme_chipno = 2,
3636 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3637 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3638 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3639 },
3640 {
3641 .pme_name = "<M:0:3>@3",
3642 .pme_desc = "<NA>",
3643 .pme_code = 243,
3644 .pme_flags = 0x0,
3645 .pme_numasks = 0,
3646 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3647 .pme_ctr = 0,
3648 .pme_event = 3,
3649 .pme_chipno = 3,
3650 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3651 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3652 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3653 },
3654 {
3655 .pme_name = "<M:0:3>@4",
3656 .pme_desc = "<NA>",
3657 .pme_code = 244,
3658 .pme_flags = 0x0,
3659 .pme_numasks = 0,
3660 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3661 .pme_ctr = 0,
3662 .pme_event = 3,
3663 .pme_chipno = 4,
3664 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3665 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3666 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3667 },
3668 {
3669 .pme_name = "<M:0:3>@5",
3670 .pme_desc = "<NA>",
3671 .pme_code = 245,
3672 .pme_flags = 0x0,
3673 .pme_numasks = 0,
3674 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3675 .pme_ctr = 0,
3676 .pme_event = 3,
3677 .pme_chipno = 5,
3678 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3679 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3680 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3681 },
3682 {
3683 .pme_name = "<M:0:3>@6",
3684 .pme_desc = "<NA>",
3685 .pme_code = 246,
3686 .pme_flags = 0x0,
3687 .pme_numasks = 0,
3688 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3689 .pme_ctr = 0,
3690 .pme_event = 3,
3691 .pme_chipno = 6,
3692 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3693 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3694 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3695 },
3696 {
3697 .pme_name = "<M:0:3>@7",
3698 .pme_desc = "<NA>",
3699 .pme_code = 247,
3700 .pme_flags = 0x0,
3701 .pme_numasks = 0,
3702 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3703 .pme_ctr = 0,
3704 .pme_event = 3,
3705 .pme_chipno = 7,
3706 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3707 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3708 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3709 },
3710 {
3711 .pme_name = "<M:0:3>@8",
3712 .pme_desc = "<NA>",
3713 .pme_code = 248,
3714 .pme_flags = 0x0,
3715 .pme_numasks = 0,
3716 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3717 .pme_ctr = 0,
3718 .pme_event = 3,
3719 .pme_chipno = 8,
3720 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3721 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3722 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3723 },
3724 {
3725 .pme_name = "<M:0:3>@9",
3726 .pme_desc = "<NA>",
3727 .pme_code = 249,
3728 .pme_flags = 0x0,
3729 .pme_numasks = 0,
3730 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3731 .pme_ctr = 0,
3732 .pme_event = 3,
3733 .pme_chipno = 9,
3734 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3735 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3736 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3737 },
3738 {
3739 .pme_name = "<M:0:3>@10",
3740 .pme_desc = "<NA>",
3741 .pme_code = 250,
3742 .pme_flags = 0x0,
3743 .pme_numasks = 0,
3744 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3745 .pme_ctr = 0,
3746 .pme_event = 3,
3747 .pme_chipno = 10,
3748 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3749 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3750 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3751 },
3752 {
3753 .pme_name = "<M:0:3>@11",
3754 .pme_desc = "<NA>",
3755 .pme_code = 251,
3756 .pme_flags = 0x0,
3757 .pme_numasks = 0,
3758 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3759 .pme_ctr = 0,
3760 .pme_event = 3,
3761 .pme_chipno = 11,
3762 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3763 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3764 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3765 },
3766 {
3767 .pme_name = "<M:0:3>@12",
3768 .pme_desc = "<NA>",
3769 .pme_code = 252,
3770 .pme_flags = 0x0,
3771 .pme_numasks = 0,
3772 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3773 .pme_ctr = 0,
3774 .pme_event = 3,
3775 .pme_chipno = 12,
3776 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3777 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3778 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3779 },
3780 {
3781 .pme_name = "<M:0:3>@13",
3782 .pme_desc = "<NA>",
3783 .pme_code = 253,
3784 .pme_flags = 0x0,
3785 .pme_numasks = 0,
3786 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3787 .pme_ctr = 0,
3788 .pme_event = 3,
3789 .pme_chipno = 13,
3790 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3791 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3792 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3793 },
3794 {
3795 .pme_name = "<M:0:3>@14",
3796 .pme_desc = "<NA>",
3797 .pme_code = 254,
3798 .pme_flags = 0x0,
3799 .pme_numasks = 0,
3800 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3801 .pme_ctr = 0,
3802 .pme_event = 3,
3803 .pme_chipno = 14,
3804 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3805 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3806 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3807 },
3808 {
3809 .pme_name = "<M:0:3>@15",
3810 .pme_desc = "<NA>",
3811 .pme_code = 255,
3812 .pme_flags = 0x0,
3813 .pme_numasks = 0,
3814 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3815 .pme_ctr = 0,
3816 .pme_event = 3,
3817 .pme_chipno = 15,
3818 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3819 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3820 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3821 },
3822 /* M Counter 1 Event 0 */
3823 {
3824 .pme_name = "W_IN_IDLE_1@0",
3825 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 0)",
3826 .pme_code = 256,
3827 .pme_flags = 0x0,
3828 .pme_numasks = 0,
3829 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3830 .pme_ctr = 1,
3831 .pme_event = 0,
3832 .pme_chipno = 0,
3833 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3834 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3835 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3836 },
3837 {
3838 .pme_name = "W_IN_IDLE_1@1",
3839 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 1)",
3840 .pme_code = 257,
3841 .pme_flags = 0x0,
3842 .pme_numasks = 0,
3843 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3844 .pme_ctr = 1,
3845 .pme_event = 0,
3846 .pme_chipno = 1,
3847 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3848 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3849 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3850 },
3851 {
3852 .pme_name = "W_IN_IDLE_1@2",
3853 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 2)",
3854 .pme_code = 258,
3855 .pme_flags = 0x0,
3856 .pme_numasks = 0,
3857 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3858 .pme_ctr = 1,
3859 .pme_event = 0,
3860 .pme_chipno = 2,
3861 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3862 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3863 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3864 },
3865 {
3866 .pme_name = "W_IN_IDLE_1@3",
3867 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 3)",
3868 .pme_code = 259,
3869 .pme_flags = 0x0,
3870 .pme_numasks = 0,
3871 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3872 .pme_ctr = 1,
3873 .pme_event = 0,
3874 .pme_chipno = 3,
3875 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3876 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3877 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3878 },
3879 {
3880 .pme_name = "W_IN_IDLE_1@4",
3881 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 4)",
3882 .pme_code = 260,
3883 .pme_flags = 0x0,
3884 .pme_numasks = 0,
3885 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3886 .pme_ctr = 1,
3887 .pme_event = 0,
3888 .pme_chipno = 4,
3889 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3890 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3891 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3892 },
3893 {
3894 .pme_name = "W_IN_IDLE_1@5",
3895 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 5)",
3896 .pme_code = 261,
3897 .pme_flags = 0x0,
3898 .pme_numasks = 0,
3899 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3900 .pme_ctr = 1,
3901 .pme_event = 0,
3902 .pme_chipno = 5,
3903 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3904 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3905 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3906 },
3907 {
3908 .pme_name = "W_IN_IDLE_1@6",
3909 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 6)",
3910 .pme_code = 262,
3911 .pme_flags = 0x0,
3912 .pme_numasks = 0,
3913 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3914 .pme_ctr = 1,
3915 .pme_event = 0,
3916 .pme_chipno = 6,
3917 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3918 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3919 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3920 },
3921 {
3922 .pme_name = "W_IN_IDLE_1@7",
3923 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 7)",
3924 .pme_code = 263,
3925 .pme_flags = 0x0,
3926 .pme_numasks = 0,
3927 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3928 .pme_ctr = 1,
3929 .pme_event = 0,
3930 .pme_chipno = 7,
3931 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3932 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3933 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3934 },
3935 {
3936 .pme_name = "W_IN_IDLE_1@8",
3937 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 8)",
3938 .pme_code = 264,
3939 .pme_flags = 0x0,
3940 .pme_numasks = 0,
3941 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3942 .pme_ctr = 1,
3943 .pme_event = 0,
3944 .pme_chipno = 8,
3945 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3946 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3947 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3948 },
3949 {
3950 .pme_name = "W_IN_IDLE_1@9",
3951 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 9)",
3952 .pme_code = 265,
3953 .pme_flags = 0x0,
3954 .pme_numasks = 0,
3955 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3956 .pme_ctr = 1,
3957 .pme_event = 0,
3958 .pme_chipno = 9,
3959 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3960 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3961 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3962 },
3963 {
3964 .pme_name = "W_IN_IDLE_1@10",
3965 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 10)",
3966 .pme_code = 266,
3967 .pme_flags = 0x0,
3968 .pme_numasks = 0,
3969 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3970 .pme_ctr = 1,
3971 .pme_event = 0,
3972 .pme_chipno = 10,
3973 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3974 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3975 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3976 },
3977 {
3978 .pme_name = "W_IN_IDLE_1@11",
3979 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 11)",
3980 .pme_code = 267,
3981 .pme_flags = 0x0,
3982 .pme_numasks = 0,
3983 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3984 .pme_ctr = 1,
3985 .pme_event = 0,
3986 .pme_chipno = 11,
3987 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
3988 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
3989 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
3990 },
3991 {
3992 .pme_name = "W_IN_IDLE_1@12",
3993 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 12)",
3994 .pme_code = 268,
3995 .pme_flags = 0x0,
3996 .pme_numasks = 0,
3997 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
3998 .pme_ctr = 1,
3999 .pme_event = 0,
4000 .pme_chipno = 12,
4001 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4002 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4003 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4004 },
4005 {
4006 .pme_name = "W_IN_IDLE_1@13",
4007 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 13)",
4008 .pme_code = 269,
4009 .pme_flags = 0x0,
4010 .pme_numasks = 0,
4011 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4012 .pme_ctr = 1,
4013 .pme_event = 0,
4014 .pme_chipno = 13,
4015 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4016 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4017 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4018 },
4019 {
4020 .pme_name = "W_IN_IDLE_1@14",
4021 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 14)",
4022 .pme_code = 270,
4023 .pme_flags = 0x0,
4024 .pme_numasks = 0,
4025 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4026 .pme_ctr = 1,
4027 .pme_event = 0,
4028 .pme_chipno = 14,
4029 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4030 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4031 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4032 },
4033 {
4034 .pme_name = "W_IN_IDLE_1@15",
4035 .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 15)",
4036 .pme_code = 271,
4037 .pme_flags = 0x0,
4038 .pme_numasks = 0,
4039 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4040 .pme_ctr = 1,
4041 .pme_event = 0,
4042 .pme_chipno = 15,
4043 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4044 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4045 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4046 },
4047 /* M Counter 1 Event 1 */
4048 {
4049 .pme_name = "STALL_TDB_FULL@0",
4050 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 0)",
4051 .pme_code = 272,
4052 .pme_flags = 0x0,
4053 .pme_numasks = 0,
4054 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4055 .pme_ctr = 1,
4056 .pme_event = 1,
4057 .pme_chipno = 0,
4058 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4059 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4060 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4061 },
4062 {
4063 .pme_name = "STALL_TDB_FULL@1",
4064 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 1)",
4065 .pme_code = 273,
4066 .pme_flags = 0x0,
4067 .pme_numasks = 0,
4068 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4069 .pme_ctr = 1,
4070 .pme_event = 1,
4071 .pme_chipno = 1,
4072 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4073 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4074 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4075 },
4076 {
4077 .pme_name = "STALL_TDB_FULL@2",
4078 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 2)",
4079 .pme_code = 274,
4080 .pme_flags = 0x0,
4081 .pme_numasks = 0,
4082 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4083 .pme_ctr = 1,
4084 .pme_event = 1,
4085 .pme_chipno = 2,
4086 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4087 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4088 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4089 },
4090 {
4091 .pme_name = "STALL_TDB_FULL@3",
4092 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 3)",
4093 .pme_code = 275,
4094 .pme_flags = 0x0,
4095 .pme_numasks = 0,
4096 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4097 .pme_ctr = 1,
4098 .pme_event = 1,
4099 .pme_chipno = 3,
4100 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4101 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4102 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4103 },
4104 {
4105 .pme_name = "STALL_TDB_FULL@4",
4106 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 4)",
4107 .pme_code = 276,
4108 .pme_flags = 0x0,
4109 .pme_numasks = 0,
4110 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4111 .pme_ctr = 1,
4112 .pme_event = 1,
4113 .pme_chipno = 4,
4114 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4115 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4116 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4117 },
4118 {
4119 .pme_name = "STALL_TDB_FULL@5",
4120 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 5)",
4121 .pme_code = 277,
4122 .pme_flags = 0x0,
4123 .pme_numasks = 0,
4124 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4125 .pme_ctr = 1,
4126 .pme_event = 1,
4127 .pme_chipno = 5,
4128 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4129 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4130 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4131 },
4132 {
4133 .pme_name = "STALL_TDB_FULL@6",
4134 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 6)",
4135 .pme_code = 278,
4136 .pme_flags = 0x0,
4137 .pme_numasks = 0,
4138 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4139 .pme_ctr = 1,
4140 .pme_event = 1,
4141 .pme_chipno = 6,
4142 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4143 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4144 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4145 },
4146 {
4147 .pme_name = "STALL_TDB_FULL@7",
4148 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 7)",
4149 .pme_code = 279,
4150 .pme_flags = 0x0,
4151 .pme_numasks = 0,
4152 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4153 .pme_ctr = 1,
4154 .pme_event = 1,
4155 .pme_chipno = 7,
4156 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4157 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4158 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4159 },
4160 {
4161 .pme_name = "STALL_TDB_FULL@8",
4162 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 8)",
4163 .pme_code = 280,
4164 .pme_flags = 0x0,
4165 .pme_numasks = 0,
4166 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4167 .pme_ctr = 1,
4168 .pme_event = 1,
4169 .pme_chipno = 8,
4170 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4171 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4172 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4173 },
4174 {
4175 .pme_name = "STALL_TDB_FULL@9",
4176 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 9)",
4177 .pme_code = 281,
4178 .pme_flags = 0x0,
4179 .pme_numasks = 0,
4180 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4181 .pme_ctr = 1,
4182 .pme_event = 1,
4183 .pme_chipno = 9,
4184 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4185 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4186 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4187 },
4188 {
4189 .pme_name = "STALL_TDB_FULL@10",
4190 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 10)",
4191 .pme_code = 282,
4192 .pme_flags = 0x0,
4193 .pme_numasks = 0,
4194 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4195 .pme_ctr = 1,
4196 .pme_event = 1,
4197 .pme_chipno = 10,
4198 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4199 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4200 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4201 },
4202 {
4203 .pme_name = "STALL_TDB_FULL@11",
4204 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 11)",
4205 .pme_code = 283,
4206 .pme_flags = 0x0,
4207 .pme_numasks = 0,
4208 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4209 .pme_ctr = 1,
4210 .pme_event = 1,
4211 .pme_chipno = 11,
4212 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4213 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4214 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4215 },
4216 {
4217 .pme_name = "STALL_TDB_FULL@12",
4218 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 12)",
4219 .pme_code = 284,
4220 .pme_flags = 0x0,
4221 .pme_numasks = 0,
4222 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4223 .pme_ctr = 1,
4224 .pme_event = 1,
4225 .pme_chipno = 12,
4226 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4227 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4228 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4229 },
4230 {
4231 .pme_name = "STALL_TDB_FULL@13",
4232 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 13)",
4233 .pme_code = 285,
4234 .pme_flags = 0x0,
4235 .pme_numasks = 0,
4236 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4237 .pme_ctr = 1,
4238 .pme_event = 1,
4239 .pme_chipno = 13,
4240 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4241 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4242 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4243 },
4244 {
4245 .pme_name = "STALL_TDB_FULL@14",
4246 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 14)",
4247 .pme_code = 286,
4248 .pme_flags = 0x0,
4249 .pme_numasks = 0,
4250 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4251 .pme_ctr = 1,
4252 .pme_event = 1,
4253 .pme_chipno = 14,
4254 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4255 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4256 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4257 },
4258 {
4259 .pme_name = "STALL_TDB_FULL@15",
4260 .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 15)",
4261 .pme_code = 287,
4262 .pme_flags = 0x0,
4263 .pme_numasks = 0,
4264 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4265 .pme_ctr = 1,
4266 .pme_event = 1,
4267 .pme_chipno = 15,
4268 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4269 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4270 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4271 },
4272 /* M Counter 1 Event 2 */
4273 {
4274 .pme_name = "W_OUT_IDLE_1@0",
4275 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 0)",
4276 .pme_code = 288,
4277 .pme_flags = 0x0,
4278 .pme_numasks = 0,
4279 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4280 .pme_ctr = 1,
4281 .pme_event = 2,
4282 .pme_chipno = 0,
4283 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4284 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4285 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4286 },
4287 {
4288 .pme_name = "W_OUT_IDLE_1@1",
4289 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 1)",
4290 .pme_code = 289,
4291 .pme_flags = 0x0,
4292 .pme_numasks = 0,
4293 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4294 .pme_ctr = 1,
4295 .pme_event = 2,
4296 .pme_chipno = 1,
4297 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4298 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4299 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4300 },
4301 {
4302 .pme_name = "W_OUT_IDLE_1@2",
4303 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 2)",
4304 .pme_code = 290,
4305 .pme_flags = 0x0,
4306 .pme_numasks = 0,
4307 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4308 .pme_ctr = 1,
4309 .pme_event = 2,
4310 .pme_chipno = 2,
4311 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4312 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4313 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4314 },
4315 {
4316 .pme_name = "W_OUT_IDLE_1@3",
4317 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 3)",
4318 .pme_code = 291,
4319 .pme_flags = 0x0,
4320 .pme_numasks = 0,
4321 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4322 .pme_ctr = 1,
4323 .pme_event = 2,
4324 .pme_chipno = 3,
4325 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4326 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4327 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4328 },
4329 {
4330 .pme_name = "W_OUT_IDLE_1@4",
4331 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 4)",
4332 .pme_code = 292,
4333 .pme_flags = 0x0,
4334 .pme_numasks = 0,
4335 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4336 .pme_ctr = 1,
4337 .pme_event = 2,
4338 .pme_chipno = 4,
4339 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4340 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4341 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4342 },
4343 {
4344 .pme_name = "W_OUT_IDLE_1@5",
4345 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 5)",
4346 .pme_code = 293,
4347 .pme_flags = 0x0,
4348 .pme_numasks = 0,
4349 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4350 .pme_ctr = 1,
4351 .pme_event = 2,
4352 .pme_chipno = 5,
4353 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4354 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4355 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4356 },
4357 {
4358 .pme_name = "W_OUT_IDLE_1@6",
4359 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 6)",
4360 .pme_code = 294,
4361 .pme_flags = 0x0,
4362 .pme_numasks = 0,
4363 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4364 .pme_ctr = 1,
4365 .pme_event = 2,
4366 .pme_chipno = 6,
4367 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4368 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4369 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4370 },
4371 {
4372 .pme_name = "W_OUT_IDLE_1@7",
4373 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 7)",
4374 .pme_code = 295,
4375 .pme_flags = 0x0,
4376 .pme_numasks = 0,
4377 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4378 .pme_ctr = 1,
4379 .pme_event = 2,
4380 .pme_chipno = 7,
4381 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4382 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4383 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4384 },
4385 {
4386 .pme_name = "W_OUT_IDLE_1@8",
4387 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 8)",
4388 .pme_code = 296,
4389 .pme_flags = 0x0,
4390 .pme_numasks = 0,
4391 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4392 .pme_ctr = 1,
4393 .pme_event = 2,
4394 .pme_chipno = 8,
4395 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4396 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4397 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4398 },
4399 {
4400 .pme_name = "W_OUT_IDLE_1@9",
4401 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 9)",
4402 .pme_code = 297,
4403 .pme_flags = 0x0,
4404 .pme_numasks = 0,
4405 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4406 .pme_ctr = 1,
4407 .pme_event = 2,
4408 .pme_chipno = 9,
4409 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4410 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4411 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4412 },
4413 {
4414 .pme_name = "W_OUT_IDLE_1@10",
4415 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 10)",
4416 .pme_code = 298,
4417 .pme_flags = 0x0,
4418 .pme_numasks = 0,
4419 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4420 .pme_ctr = 1,
4421 .pme_event = 2,
4422 .pme_chipno = 10,
4423 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4424 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4425 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4426 },
4427 {
4428 .pme_name = "W_OUT_IDLE_1@11",
4429 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 11)",
4430 .pme_code = 299,
4431 .pme_flags = 0x0,
4432 .pme_numasks = 0,
4433 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4434 .pme_ctr = 1,
4435 .pme_event = 2,
4436 .pme_chipno = 11,
4437 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4438 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4439 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4440 },
4441 {
4442 .pme_name = "W_OUT_IDLE_1@12",
4443 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 12)",
4444 .pme_code = 300,
4445 .pme_flags = 0x0,
4446 .pme_numasks = 0,
4447 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4448 .pme_ctr = 1,
4449 .pme_event = 2,
4450 .pme_chipno = 12,
4451 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4452 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4453 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4454 },
4455 {
4456 .pme_name = "W_OUT_IDLE_1@13",
4457 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 13)",
4458 .pme_code = 301,
4459 .pme_flags = 0x0,
4460 .pme_numasks = 0,
4461 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4462 .pme_ctr = 1,
4463 .pme_event = 2,
4464 .pme_chipno = 13,
4465 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4466 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4467 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4468 },
4469 {
4470 .pme_name = "W_OUT_IDLE_1@14",
4471 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 14)",
4472 .pme_code = 302,
4473 .pme_flags = 0x0,
4474 .pme_numasks = 0,
4475 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4476 .pme_ctr = 1,
4477 .pme_event = 2,
4478 .pme_chipno = 14,
4479 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4480 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4481 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4482 },
4483 {
4484 .pme_name = "W_OUT_IDLE_1@15",
4485 .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 15)",
4486 .pme_code = 303,
4487 .pme_flags = 0x0,
4488 .pme_numasks = 0,
4489 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4490 .pme_ctr = 1,
4491 .pme_event = 2,
4492 .pme_chipno = 15,
4493 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4494 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4495 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4496 },
4497 /* M Counter 1 Event 3 */
4498 {
4499 .pme_name = "FWD_READ_SHARED_SENT@0",
4500 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 0)",
4501 .pme_code = 304,
4502 .pme_flags = 0x0,
4503 .pme_numasks = 0,
4504 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4505 .pme_ctr = 1,
4506 .pme_event = 3,
4507 .pme_chipno = 0,
4508 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4509 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4510 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4511 },
4512 {
4513 .pme_name = "FWD_READ_SHARED_SENT@1",
4514 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 1)",
4515 .pme_code = 305,
4516 .pme_flags = 0x0,
4517 .pme_numasks = 0,
4518 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4519 .pme_ctr = 1,
4520 .pme_event = 3,
4521 .pme_chipno = 1,
4522 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4523 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4524 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4525 },
4526 {
4527 .pme_name = "FWD_READ_SHARED_SENT@2",
4528 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 2)",
4529 .pme_code = 306,
4530 .pme_flags = 0x0,
4531 .pme_numasks = 0,
4532 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4533 .pme_ctr = 1,
4534 .pme_event = 3,
4535 .pme_chipno = 2,
4536 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4537 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4538 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4539 },
4540 {
4541 .pme_name = "FWD_READ_SHARED_SENT@3",
4542 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 3)",
4543 .pme_code = 307,
4544 .pme_flags = 0x0,
4545 .pme_numasks = 0,
4546 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4547 .pme_ctr = 1,
4548 .pme_event = 3,
4549 .pme_chipno = 3,
4550 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4551 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4552 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4553 },
4554 {
4555 .pme_name = "FWD_READ_SHARED_SENT@4",
4556 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 4)",
4557 .pme_code = 308,
4558 .pme_flags = 0x0,
4559 .pme_numasks = 0,
4560 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4561 .pme_ctr = 1,
4562 .pme_event = 3,
4563 .pme_chipno = 4,
4564 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4565 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4566 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4567 },
4568 {
4569 .pme_name = "FWD_READ_SHARED_SENT@5",
4570 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 5)",
4571 .pme_code = 309,
4572 .pme_flags = 0x0,
4573 .pme_numasks = 0,
4574 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4575 .pme_ctr = 1,
4576 .pme_event = 3,
4577 .pme_chipno = 5,
4578 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4579 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4580 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4581 },
4582 {
4583 .pme_name = "FWD_READ_SHARED_SENT@6",
4584 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 6)",
4585 .pme_code = 310,
4586 .pme_flags = 0x0,
4587 .pme_numasks = 0,
4588 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4589 .pme_ctr = 1,
4590 .pme_event = 3,
4591 .pme_chipno = 6,
4592 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4593 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4594 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4595 },
4596 {
4597 .pme_name = "FWD_READ_SHARED_SENT@7",
4598 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 7)",
4599 .pme_code = 311,
4600 .pme_flags = 0x0,
4601 .pme_numasks = 0,
4602 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4603 .pme_ctr = 1,
4604 .pme_event = 3,
4605 .pme_chipno = 7,
4606 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4607 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4608 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4609 },
4610 {
4611 .pme_name = "FWD_READ_SHARED_SENT@8",
4612 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 8)",
4613 .pme_code = 312,
4614 .pme_flags = 0x0,
4615 .pme_numasks = 0,
4616 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4617 .pme_ctr = 1,
4618 .pme_event = 3,
4619 .pme_chipno = 8,
4620 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4621 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4622 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4623 },
4624 {
4625 .pme_name = "FWD_READ_SHARED_SENT@9",
4626 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 9)",
4627 .pme_code = 313,
4628 .pme_flags = 0x0,
4629 .pme_numasks = 0,
4630 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4631 .pme_ctr = 1,
4632 .pme_event = 3,
4633 .pme_chipno = 9,
4634 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4635 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4636 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4637 },
4638 {
4639 .pme_name = "FWD_READ_SHARED_SENT@10",
4640 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 10)",
4641 .pme_code = 314,
4642 .pme_flags = 0x0,
4643 .pme_numasks = 0,
4644 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4645 .pme_ctr = 1,
4646 .pme_event = 3,
4647 .pme_chipno = 10,
4648 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4649 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4650 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4651 },
4652 {
4653 .pme_name = "FWD_READ_SHARED_SENT@11",
4654 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 11)",
4655 .pme_code = 315,
4656 .pme_flags = 0x0,
4657 .pme_numasks = 0,
4658 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4659 .pme_ctr = 1,
4660 .pme_event = 3,
4661 .pme_chipno = 11,
4662 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4663 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4664 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4665 },
4666 {
4667 .pme_name = "FWD_READ_SHARED_SENT@12",
4668 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 12)",
4669 .pme_code = 316,
4670 .pme_flags = 0x0,
4671 .pme_numasks = 0,
4672 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4673 .pme_ctr = 1,
4674 .pme_event = 3,
4675 .pme_chipno = 12,
4676 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4677 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4678 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4679 },
4680 {
4681 .pme_name = "FWD_READ_SHARED_SENT@13",
4682 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 13)",
4683 .pme_code = 317,
4684 .pme_flags = 0x0,
4685 .pme_numasks = 0,
4686 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4687 .pme_ctr = 1,
4688 .pme_event = 3,
4689 .pme_chipno = 13,
4690 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4691 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4692 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4693 },
4694 {
4695 .pme_name = "FWD_READ_SHARED_SENT@14",
4696 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 14)",
4697 .pme_code = 318,
4698 .pme_flags = 0x0,
4699 .pme_numasks = 0,
4700 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4701 .pme_ctr = 1,
4702 .pme_event = 3,
4703 .pme_chipno = 14,
4704 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4705 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4706 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4707 },
4708 {
4709 .pme_name = "FWD_READ_SHARED_SENT@15",
4710 .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 15)",
4711 .pme_code = 319,
4712 .pme_flags = 0x0,
4713 .pme_numasks = 0,
4714 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4715 .pme_ctr = 1,
4716 .pme_event = 3,
4717 .pme_chipno = 15,
4718 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4719 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4720 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4721 },
4722 /* M Counter 2 Event 0 */
4723 {
4724 .pme_name = "UPDATES_SENT@0",
4725 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 0)",
4726 .pme_code = 320,
4727 .pme_flags = 0x0,
4728 .pme_numasks = 0,
4729 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4730 .pme_ctr = 2,
4731 .pme_event = 0,
4732 .pme_chipno = 0,
4733 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4734 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4735 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4736 },
4737 {
4738 .pme_name = "UPDATES_SENT@1",
4739 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 1)",
4740 .pme_code = 321,
4741 .pme_flags = 0x0,
4742 .pme_numasks = 0,
4743 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4744 .pme_ctr = 2,
4745 .pme_event = 0,
4746 .pme_chipno = 1,
4747 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4748 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4749 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4750 },
4751 {
4752 .pme_name = "UPDATES_SENT@2",
4753 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 2)",
4754 .pme_code = 322,
4755 .pme_flags = 0x0,
4756 .pme_numasks = 0,
4757 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4758 .pme_ctr = 2,
4759 .pme_event = 0,
4760 .pme_chipno = 2,
4761 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4762 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4763 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4764 },
4765 {
4766 .pme_name = "UPDATES_SENT@3",
4767 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 3)",
4768 .pme_code = 323,
4769 .pme_flags = 0x0,
4770 .pme_numasks = 0,
4771 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4772 .pme_ctr = 2,
4773 .pme_event = 0,
4774 .pme_chipno = 3,
4775 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4776 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4777 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4778 },
4779 {
4780 .pme_name = "UPDATES_SENT@4",
4781 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 4)",
4782 .pme_code = 324,
4783 .pme_flags = 0x0,
4784 .pme_numasks = 0,
4785 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4786 .pme_ctr = 2,
4787 .pme_event = 0,
4788 .pme_chipno = 4,
4789 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4790 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4791 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4792 },
4793 {
4794 .pme_name = "UPDATES_SENT@5",
4795 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 5)",
4796 .pme_code = 325,
4797 .pme_flags = 0x0,
4798 .pme_numasks = 0,
4799 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4800 .pme_ctr = 2,
4801 .pme_event = 0,
4802 .pme_chipno = 5,
4803 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4804 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4805 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4806 },
4807 {
4808 .pme_name = "UPDATES_SENT@6",
4809 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 6)",
4810 .pme_code = 326,
4811 .pme_flags = 0x0,
4812 .pme_numasks = 0,
4813 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4814 .pme_ctr = 2,
4815 .pme_event = 0,
4816 .pme_chipno = 6,
4817 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4818 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4819 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4820 },
4821 {
4822 .pme_name = "UPDATES_SENT@7",
4823 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 7)",
4824 .pme_code = 327,
4825 .pme_flags = 0x0,
4826 .pme_numasks = 0,
4827 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4828 .pme_ctr = 2,
4829 .pme_event = 0,
4830 .pme_chipno = 7,
4831 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4832 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4833 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4834 },
4835 {
4836 .pme_name = "UPDATES_SENT@8",
4837 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 8)",
4838 .pme_code = 328,
4839 .pme_flags = 0x0,
4840 .pme_numasks = 0,
4841 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4842 .pme_ctr = 2,
4843 .pme_event = 0,
4844 .pme_chipno = 8,
4845 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4846 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4847 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4848 },
4849 {
4850 .pme_name = "UPDATES_SENT@9",
4851 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 9)",
4852 .pme_code = 329,
4853 .pme_flags = 0x0,
4854 .pme_numasks = 0,
4855 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4856 .pme_ctr = 2,
4857 .pme_event = 0,
4858 .pme_chipno = 9,
4859 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4860 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4861 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4862 },
4863 {
4864 .pme_name = "UPDATES_SENT@10",
4865 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 10)",
4866 .pme_code = 330,
4867 .pme_flags = 0x0,
4868 .pme_numasks = 0,
4869 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4870 .pme_ctr = 2,
4871 .pme_event = 0,
4872 .pme_chipno = 10,
4873 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4874 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4875 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4876 },
4877 {
4878 .pme_name = "UPDATES_SENT@11",
4879 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 11)",
4880 .pme_code = 331,
4881 .pme_flags = 0x0,
4882 .pme_numasks = 0,
4883 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4884 .pme_ctr = 2,
4885 .pme_event = 0,
4886 .pme_chipno = 11,
4887 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4888 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4889 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4890 },
4891 {
4892 .pme_name = "UPDATES_SENT@12",
4893 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 12)",
4894 .pme_code = 332,
4895 .pme_flags = 0x0,
4896 .pme_numasks = 0,
4897 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4898 .pme_ctr = 2,
4899 .pme_event = 0,
4900 .pme_chipno = 12,
4901 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4902 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4903 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4904 },
4905 {
4906 .pme_name = "UPDATES_SENT@13",
4907 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 13)",
4908 .pme_code = 333,
4909 .pme_flags = 0x0,
4910 .pme_numasks = 0,
4911 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4912 .pme_ctr = 2,
4913 .pme_event = 0,
4914 .pme_chipno = 13,
4915 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4916 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4917 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4918 },
4919 {
4920 .pme_name = "UPDATES_SENT@14",
4921 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 14)",
4922 .pme_code = 334,
4923 .pme_flags = 0x0,
4924 .pme_numasks = 0,
4925 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4926 .pme_ctr = 2,
4927 .pme_event = 0,
4928 .pme_chipno = 14,
4929 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4930 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4931 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4932 },
4933 {
4934 .pme_name = "UPDATES_SENT@15",
4935 .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 15)",
4936 .pme_code = 335,
4937 .pme_flags = 0x0,
4938 .pme_numasks = 0,
4939 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4940 .pme_ctr = 2,
4941 .pme_event = 0,
4942 .pme_chipno = 15,
4943 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4944 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4945 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4946 },
4947 /* M Counter 2 Event 1 */
4948 {
4949 .pme_name = "STALL_MM_RESPQ@0",
4950 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 0)",
4951 .pme_code = 336,
4952 .pme_flags = 0x0,
4953 .pme_numasks = 0,
4954 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4955 .pme_ctr = 2,
4956 .pme_event = 1,
4957 .pme_chipno = 0,
4958 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4959 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4960 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4961 },
4962 {
4963 .pme_name = "STALL_MM_RESPQ@1",
4964 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 1)",
4965 .pme_code = 337,
4966 .pme_flags = 0x0,
4967 .pme_numasks = 0,
4968 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4969 .pme_ctr = 2,
4970 .pme_event = 1,
4971 .pme_chipno = 1,
4972 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4973 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4974 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4975 },
4976 {
4977 .pme_name = "STALL_MM_RESPQ@2",
4978 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 2)",
4979 .pme_code = 338,
4980 .pme_flags = 0x0,
4981 .pme_numasks = 0,
4982 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4983 .pme_ctr = 2,
4984 .pme_event = 1,
4985 .pme_chipno = 2,
4986 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
4987 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
4988 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
4989 },
4990 {
4991 .pme_name = "STALL_MM_RESPQ@3",
4992 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 3)",
4993 .pme_code = 339,
4994 .pme_flags = 0x0,
4995 .pme_numasks = 0,
4996 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
4997 .pme_ctr = 2,
4998 .pme_event = 1,
4999 .pme_chipno = 3,
5000 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5001 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5002 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5003 },
5004 {
5005 .pme_name = "STALL_MM_RESPQ@4",
5006 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 4)",
5007 .pme_code = 340,
5008 .pme_flags = 0x0,
5009 .pme_numasks = 0,
5010 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5011 .pme_ctr = 2,
5012 .pme_event = 1,
5013 .pme_chipno = 4,
5014 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5015 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5016 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5017 },
5018 {
5019 .pme_name = "STALL_MM_RESPQ@5",
5020 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 5)",
5021 .pme_code = 341,
5022 .pme_flags = 0x0,
5023 .pme_numasks = 0,
5024 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5025 .pme_ctr = 2,
5026 .pme_event = 1,
5027 .pme_chipno = 5,
5028 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5029 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5030 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5031 },
5032 {
5033 .pme_name = "STALL_MM_RESPQ@6",
5034 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 6)",
5035 .pme_code = 342,
5036 .pme_flags = 0x0,
5037 .pme_numasks = 0,
5038 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5039 .pme_ctr = 2,
5040 .pme_event = 1,
5041 .pme_chipno = 6,
5042 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5043 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5044 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5045 },
5046 {
5047 .pme_name = "STALL_MM_RESPQ@7",
5048 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 7)",
5049 .pme_code = 343,
5050 .pme_flags = 0x0,
5051 .pme_numasks = 0,
5052 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5053 .pme_ctr = 2,
5054 .pme_event = 1,
5055 .pme_chipno = 7,
5056 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5057 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5058 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5059 },
5060 {
5061 .pme_name = "STALL_MM_RESPQ@8",
5062 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 8)",
5063 .pme_code = 344,
5064 .pme_flags = 0x0,
5065 .pme_numasks = 0,
5066 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5067 .pme_ctr = 2,
5068 .pme_event = 1,
5069 .pme_chipno = 8,
5070 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5071 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5072 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5073 },
5074 {
5075 .pme_name = "STALL_MM_RESPQ@9",
5076 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 9)",
5077 .pme_code = 345,
5078 .pme_flags = 0x0,
5079 .pme_numasks = 0,
5080 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5081 .pme_ctr = 2,
5082 .pme_event = 1,
5083 .pme_chipno = 9,
5084 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5085 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5086 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5087 },
5088 {
5089 .pme_name = "STALL_MM_RESPQ@10",
5090 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 10)",
5091 .pme_code = 346,
5092 .pme_flags = 0x0,
5093 .pme_numasks = 0,
5094 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5095 .pme_ctr = 2,
5096 .pme_event = 1,
5097 .pme_chipno = 10,
5098 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5099 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5100 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5101 },
5102 {
5103 .pme_name = "STALL_MM_RESPQ@11",
5104 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 11)",
5105 .pme_code = 347,
5106 .pme_flags = 0x0,
5107 .pme_numasks = 0,
5108 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5109 .pme_ctr = 2,
5110 .pme_event = 1,
5111 .pme_chipno = 11,
5112 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5113 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5114 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5115 },
5116 {
5117 .pme_name = "STALL_MM_RESPQ@12",
5118 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 12)",
5119 .pme_code = 348,
5120 .pme_flags = 0x0,
5121 .pme_numasks = 0,
5122 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5123 .pme_ctr = 2,
5124 .pme_event = 1,
5125 .pme_chipno = 12,
5126 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5127 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5128 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5129 },
5130 {
5131 .pme_name = "STALL_MM_RESPQ@13",
5132 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 13)",
5133 .pme_code = 349,
5134 .pme_flags = 0x0,
5135 .pme_numasks = 0,
5136 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5137 .pme_ctr = 2,
5138 .pme_event = 1,
5139 .pme_chipno = 13,
5140 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5141 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5142 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5143 },
5144 {
5145 .pme_name = "STALL_MM_RESPQ@14",
5146 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 14)",
5147 .pme_code = 350,
5148 .pme_flags = 0x0,
5149 .pme_numasks = 0,
5150 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5151 .pme_ctr = 2,
5152 .pme_event = 1,
5153 .pme_chipno = 14,
5154 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5155 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5156 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5157 },
5158 {
5159 .pme_name = "STALL_MM_RESPQ@15",
5160 .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 15)",
5161 .pme_code = 351,
5162 .pme_flags = 0x0,
5163 .pme_numasks = 0,
5164 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5165 .pme_ctr = 2,
5166 .pme_event = 1,
5167 .pme_chipno = 15,
5168 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5169 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5170 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5171 },
5172 /* M Counter 2 Event 2 */
5173 {
5174 .pme_name = "W_OUT_IDLE_2@0",
5175 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 0)",
5176 .pme_code = 352,
5177 .pme_flags = 0x0,
5178 .pme_numasks = 0,
5179 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5180 .pme_ctr = 2,
5181 .pme_event = 2,
5182 .pme_chipno = 0,
5183 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5184 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5185 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5186 },
5187 {
5188 .pme_name = "W_OUT_IDLE_2@1",
5189 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 1)",
5190 .pme_code = 353,
5191 .pme_flags = 0x0,
5192 .pme_numasks = 0,
5193 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5194 .pme_ctr = 2,
5195 .pme_event = 2,
5196 .pme_chipno = 1,
5197 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5198 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5199 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5200 },
5201 {
5202 .pme_name = "W_OUT_IDLE_2@2",
5203 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 2)",
5204 .pme_code = 354,
5205 .pme_flags = 0x0,
5206 .pme_numasks = 0,
5207 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5208 .pme_ctr = 2,
5209 .pme_event = 2,
5210 .pme_chipno = 2,
5211 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5212 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5213 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5214 },
5215 {
5216 .pme_name = "W_OUT_IDLE_2@3",
5217 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 3)",
5218 .pme_code = 355,
5219 .pme_flags = 0x0,
5220 .pme_numasks = 0,
5221 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5222 .pme_ctr = 2,
5223 .pme_event = 2,
5224 .pme_chipno = 3,
5225 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5226 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5227 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5228 },
5229 {
5230 .pme_name = "W_OUT_IDLE_2@4",
5231 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 4)",
5232 .pme_code = 356,
5233 .pme_flags = 0x0,
5234 .pme_numasks = 0,
5235 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5236 .pme_ctr = 2,
5237 .pme_event = 2,
5238 .pme_chipno = 4,
5239 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5240 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5241 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5242 },
5243 {
5244 .pme_name = "W_OUT_IDLE_2@5",
5245 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 5)",
5246 .pme_code = 357,
5247 .pme_flags = 0x0,
5248 .pme_numasks = 0,
5249 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5250 .pme_ctr = 2,
5251 .pme_event = 2,
5252 .pme_chipno = 5,
5253 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5254 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5255 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5256 },
5257 {
5258 .pme_name = "W_OUT_IDLE_2@6",
5259 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 6)",
5260 .pme_code = 358,
5261 .pme_flags = 0x0,
5262 .pme_numasks = 0,
5263 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5264 .pme_ctr = 2,
5265 .pme_event = 2,
5266 .pme_chipno = 6,
5267 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5268 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5269 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5270 },
5271 {
5272 .pme_name = "W_OUT_IDLE_2@7",
5273 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 7)",
5274 .pme_code = 359,
5275 .pme_flags = 0x0,
5276 .pme_numasks = 0,
5277 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5278 .pme_ctr = 2,
5279 .pme_event = 2,
5280 .pme_chipno = 7,
5281 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5282 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5283 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5284 },
5285 {
5286 .pme_name = "W_OUT_IDLE_2@8",
5287 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 8)",
5288 .pme_code = 360,
5289 .pme_flags = 0x0,
5290 .pme_numasks = 0,
5291 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5292 .pme_ctr = 2,
5293 .pme_event = 2,
5294 .pme_chipno = 8,
5295 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5296 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5297 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5298 },
5299 {
5300 .pme_name = "W_OUT_IDLE_2@9",
5301 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 9)",
5302 .pme_code = 361,
5303 .pme_flags = 0x0,
5304 .pme_numasks = 0,
5305 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5306 .pme_ctr = 2,
5307 .pme_event = 2,
5308 .pme_chipno = 9,
5309 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5310 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5311 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5312 },
5313 {
5314 .pme_name = "W_OUT_IDLE_2@10",
5315 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 10)",
5316 .pme_code = 362,
5317 .pme_flags = 0x0,
5318 .pme_numasks = 0,
5319 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5320 .pme_ctr = 2,
5321 .pme_event = 2,
5322 .pme_chipno = 10,
5323 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5324 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5325 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5326 },
5327 {
5328 .pme_name = "W_OUT_IDLE_2@11",
5329 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 11)",
5330 .pme_code = 363,
5331 .pme_flags = 0x0,
5332 .pme_numasks = 0,
5333 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5334 .pme_ctr = 2,
5335 .pme_event = 2,
5336 .pme_chipno = 11,
5337 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5338 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5339 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5340 },
5341 {
5342 .pme_name = "W_OUT_IDLE_2@12",
5343 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 12)",
5344 .pme_code = 364,
5345 .pme_flags = 0x0,
5346 .pme_numasks = 0,
5347 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5348 .pme_ctr = 2,
5349 .pme_event = 2,
5350 .pme_chipno = 12,
5351 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5352 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5353 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5354 },
5355 {
5356 .pme_name = "W_OUT_IDLE_2@13",
5357 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 13)",
5358 .pme_code = 365,
5359 .pme_flags = 0x0,
5360 .pme_numasks = 0,
5361 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5362 .pme_ctr = 2,
5363 .pme_event = 2,
5364 .pme_chipno = 13,
5365 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5366 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5367 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5368 },
5369 {
5370 .pme_name = "W_OUT_IDLE_2@14",
5371 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 14)",
5372 .pme_code = 366,
5373 .pme_flags = 0x0,
5374 .pme_numasks = 0,
5375 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5376 .pme_ctr = 2,
5377 .pme_event = 2,
5378 .pme_chipno = 14,
5379 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5380 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5381 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5382 },
5383 {
5384 .pme_name = "W_OUT_IDLE_2@15",
5385 .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 15)",
5386 .pme_code = 367,
5387 .pme_flags = 0x0,
5388 .pme_numasks = 0,
5389 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5390 .pme_ctr = 2,
5391 .pme_event = 2,
5392 .pme_chipno = 15,
5393 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5394 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5395 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5396 },
5397 /* M Counter 2 Event 3 */
5398 {
5399 .pme_name = "W_IN_IDLE_2@0",
5400 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 0)",
5401 .pme_code = 368,
5402 .pme_flags = 0x0,
5403 .pme_numasks = 0,
5404 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5405 .pme_ctr = 2,
5406 .pme_event = 3,
5407 .pme_chipno = 0,
5408 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5409 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5410 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5411 },
5412 {
5413 .pme_name = "W_IN_IDLE_2@1",
5414 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 1)",
5415 .pme_code = 369,
5416 .pme_flags = 0x0,
5417 .pme_numasks = 0,
5418 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5419 .pme_ctr = 2,
5420 .pme_event = 3,
5421 .pme_chipno = 1,
5422 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5423 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5424 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5425 },
5426 {
5427 .pme_name = "W_IN_IDLE_2@2",
5428 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 2)",
5429 .pme_code = 370,
5430 .pme_flags = 0x0,
5431 .pme_numasks = 0,
5432 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5433 .pme_ctr = 2,
5434 .pme_event = 3,
5435 .pme_chipno = 2,
5436 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5437 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5438 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5439 },
5440 {
5441 .pme_name = "W_IN_IDLE_2@3",
5442 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 3)",
5443 .pme_code = 371,
5444 .pme_flags = 0x0,
5445 .pme_numasks = 0,
5446 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5447 .pme_ctr = 2,
5448 .pme_event = 3,
5449 .pme_chipno = 3,
5450 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5451 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5452 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5453 },
5454 {
5455 .pme_name = "W_IN_IDLE_2@4",
5456 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 4)",
5457 .pme_code = 372,
5458 .pme_flags = 0x0,
5459 .pme_numasks = 0,
5460 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5461 .pme_ctr = 2,
5462 .pme_event = 3,
5463 .pme_chipno = 4,
5464 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5465 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5466 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5467 },
5468 {
5469 .pme_name = "W_IN_IDLE_2@5",
5470 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 5)",
5471 .pme_code = 373,
5472 .pme_flags = 0x0,
5473 .pme_numasks = 0,
5474 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5475 .pme_ctr = 2,
5476 .pme_event = 3,
5477 .pme_chipno = 5,
5478 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5479 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5480 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5481 },
5482 {
5483 .pme_name = "W_IN_IDLE_2@6",
5484 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 6)",
5485 .pme_code = 374,
5486 .pme_flags = 0x0,
5487 .pme_numasks = 0,
5488 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5489 .pme_ctr = 2,
5490 .pme_event = 3,
5491 .pme_chipno = 6,
5492 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5493 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5494 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5495 },
5496 {
5497 .pme_name = "W_IN_IDLE_2@7",
5498 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 7)",
5499 .pme_code = 375,
5500 .pme_flags = 0x0,
5501 .pme_numasks = 0,
5502 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5503 .pme_ctr = 2,
5504 .pme_event = 3,
5505 .pme_chipno = 7,
5506 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5507 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5508 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5509 },
5510 {
5511 .pme_name = "W_IN_IDLE_2@8",
5512 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 8)",
5513 .pme_code = 376,
5514 .pme_flags = 0x0,
5515 .pme_numasks = 0,
5516 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5517 .pme_ctr = 2,
5518 .pme_event = 3,
5519 .pme_chipno = 8,
5520 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5521 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5522 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5523 },
5524 {
5525 .pme_name = "W_IN_IDLE_2@9",
5526 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 9)",
5527 .pme_code = 377,
5528 .pme_flags = 0x0,
5529 .pme_numasks = 0,
5530 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5531 .pme_ctr = 2,
5532 .pme_event = 3,
5533 .pme_chipno = 9,
5534 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5535 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5536 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5537 },
5538 {
5539 .pme_name = "W_IN_IDLE_2@10",
5540 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 10)",
5541 .pme_code = 378,
5542 .pme_flags = 0x0,
5543 .pme_numasks = 0,
5544 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5545 .pme_ctr = 2,
5546 .pme_event = 3,
5547 .pme_chipno = 10,
5548 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5549 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5550 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5551 },
5552 {
5553 .pme_name = "W_IN_IDLE_2@11",
5554 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 11)",
5555 .pme_code = 379,
5556 .pme_flags = 0x0,
5557 .pme_numasks = 0,
5558 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5559 .pme_ctr = 2,
5560 .pme_event = 3,
5561 .pme_chipno = 11,
5562 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5563 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5564 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5565 },
5566 {
5567 .pme_name = "W_IN_IDLE_2@12",
5568 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 12)",
5569 .pme_code = 380,
5570 .pme_flags = 0x0,
5571 .pme_numasks = 0,
5572 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5573 .pme_ctr = 2,
5574 .pme_event = 3,
5575 .pme_chipno = 12,
5576 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5577 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5578 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5579 },
5580 {
5581 .pme_name = "W_IN_IDLE_2@13",
5582 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 13)",
5583 .pme_code = 381,
5584 .pme_flags = 0x0,
5585 .pme_numasks = 0,
5586 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5587 .pme_ctr = 2,
5588 .pme_event = 3,
5589 .pme_chipno = 13,
5590 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5591 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5592 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5593 },
5594 {
5595 .pme_name = "W_IN_IDLE_2@14",
5596 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 14)",
5597 .pme_code = 382,
5598 .pme_flags = 0x0,
5599 .pme_numasks = 0,
5600 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5601 .pme_ctr = 2,
5602 .pme_event = 3,
5603 .pme_chipno = 14,
5604 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5605 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5606 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5607 },
5608 {
5609 .pme_name = "W_IN_IDLE_2@15",
5610 .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 15)",
5611 .pme_code = 383,
5612 .pme_flags = 0x0,
5613 .pme_numasks = 0,
5614 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5615 .pme_ctr = 2,
5616 .pme_event = 3,
5617 .pme_chipno = 15,
5618 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5619 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5620 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5621 },
5622 /* M Counter 3 Event 0 */
5623 {
5624 .pme_name = "NON_CACHED@0",
5625 .pme_desc = "Read requests satisfied from non-cached state. (M chip 0)",
5626 .pme_code = 384,
5627 .pme_flags = 0x0,
5628 .pme_numasks = 0,
5629 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5630 .pme_ctr = 3,
5631 .pme_event = 0,
5632 .pme_chipno = 0,
5633 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5634 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5635 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5636 },
5637 {
5638 .pme_name = "NON_CACHED@1",
5639 .pme_desc = "Read requests satisfied from non-cached state. (M chip 1)",
5640 .pme_code = 385,
5641 .pme_flags = 0x0,
5642 .pme_numasks = 0,
5643 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5644 .pme_ctr = 3,
5645 .pme_event = 0,
5646 .pme_chipno = 1,
5647 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5648 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5649 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5650 },
5651 {
5652 .pme_name = "NON_CACHED@2",
5653 .pme_desc = "Read requests satisfied from non-cached state. (M chip 2)",
5654 .pme_code = 386,
5655 .pme_flags = 0x0,
5656 .pme_numasks = 0,
5657 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5658 .pme_ctr = 3,
5659 .pme_event = 0,
5660 .pme_chipno = 2,
5661 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5662 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5663 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5664 },
5665 {
5666 .pme_name = "NON_CACHED@3",
5667 .pme_desc = "Read requests satisfied from non-cached state. (M chip 3)",
5668 .pme_code = 387,
5669 .pme_flags = 0x0,
5670 .pme_numasks = 0,
5671 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5672 .pme_ctr = 3,
5673 .pme_event = 0,
5674 .pme_chipno = 3,
5675 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5676 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5677 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5678 },
5679 {
5680 .pme_name = "NON_CACHED@4",
5681 .pme_desc = "Read requests satisfied from non-cached state. (M chip 4)",
5682 .pme_code = 388,
5683 .pme_flags = 0x0,
5684 .pme_numasks = 0,
5685 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5686 .pme_ctr = 3,
5687 .pme_event = 0,
5688 .pme_chipno = 4,
5689 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5690 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5691 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5692 },
5693 {
5694 .pme_name = "NON_CACHED@5",
5695 .pme_desc = "Read requests satisfied from non-cached state. (M chip 5)",
5696 .pme_code = 389,
5697 .pme_flags = 0x0,
5698 .pme_numasks = 0,
5699 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5700 .pme_ctr = 3,
5701 .pme_event = 0,
5702 .pme_chipno = 5,
5703 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5704 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5705 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5706 },
5707 {
5708 .pme_name = "NON_CACHED@6",
5709 .pme_desc = "Read requests satisfied from non-cached state. (M chip 6)",
5710 .pme_code = 390,
5711 .pme_flags = 0x0,
5712 .pme_numasks = 0,
5713 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5714 .pme_ctr = 3,
5715 .pme_event = 0,
5716 .pme_chipno = 6,
5717 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5718 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5719 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5720 },
5721 {
5722 .pme_name = "NON_CACHED@7",
5723 .pme_desc = "Read requests satisfied from non-cached state. (M chip 7)",
5724 .pme_code = 391,
5725 .pme_flags = 0x0,
5726 .pme_numasks = 0,
5727 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5728 .pme_ctr = 3,
5729 .pme_event = 0,
5730 .pme_chipno = 7,
5731 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5732 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5733 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5734 },
5735 {
5736 .pme_name = "NON_CACHED@8",
5737 .pme_desc = "Read requests satisfied from non-cached state. (M chip 8)",
5738 .pme_code = 392,
5739 .pme_flags = 0x0,
5740 .pme_numasks = 0,
5741 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5742 .pme_ctr = 3,
5743 .pme_event = 0,
5744 .pme_chipno = 8,
5745 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5746 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5747 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5748 },
5749 {
5750 .pme_name = "NON_CACHED@9",
5751 .pme_desc = "Read requests satisfied from non-cached state. (M chip 9)",
5752 .pme_code = 393,
5753 .pme_flags = 0x0,
5754 .pme_numasks = 0,
5755 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5756 .pme_ctr = 3,
5757 .pme_event = 0,
5758 .pme_chipno = 9,
5759 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5760 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5761 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5762 },
5763 {
5764 .pme_name = "NON_CACHED@10",
5765 .pme_desc = "Read requests satisfied from non-cached state. (M chip 10)",
5766 .pme_code = 394,
5767 .pme_flags = 0x0,
5768 .pme_numasks = 0,
5769 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5770 .pme_ctr = 3,
5771 .pme_event = 0,
5772 .pme_chipno = 10,
5773 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5774 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5775 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5776 },
5777 {
5778 .pme_name = "NON_CACHED@11",
5779 .pme_desc = "Read requests satisfied from non-cached state. (M chip 11)",
5780 .pme_code = 395,
5781 .pme_flags = 0x0,
5782 .pme_numasks = 0,
5783 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5784 .pme_ctr = 3,
5785 .pme_event = 0,
5786 .pme_chipno = 11,
5787 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5788 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5789 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5790 },
5791 {
5792 .pme_name = "NON_CACHED@12",
5793 .pme_desc = "Read requests satisfied from non-cached state. (M chip 12)",
5794 .pme_code = 396,
5795 .pme_flags = 0x0,
5796 .pme_numasks = 0,
5797 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5798 .pme_ctr = 3,
5799 .pme_event = 0,
5800 .pme_chipno = 12,
5801 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5802 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5803 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5804 },
5805 {
5806 .pme_name = "NON_CACHED@13",
5807 .pme_desc = "Read requests satisfied from non-cached state. (M chip 13)",
5808 .pme_code = 397,
5809 .pme_flags = 0x0,
5810 .pme_numasks = 0,
5811 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5812 .pme_ctr = 3,
5813 .pme_event = 0,
5814 .pme_chipno = 13,
5815 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5816 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5817 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5818 },
5819 {
5820 .pme_name = "NON_CACHED@14",
5821 .pme_desc = "Read requests satisfied from non-cached state. (M chip 14)",
5822 .pme_code = 398,
5823 .pme_flags = 0x0,
5824 .pme_numasks = 0,
5825 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5826 .pme_ctr = 3,
5827 .pme_event = 0,
5828 .pme_chipno = 14,
5829 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5830 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5831 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5832 },
5833 {
5834 .pme_name = "NON_CACHED@15",
5835 .pme_desc = "Read requests satisfied from non-cached state. (M chip 15)",
5836 .pme_code = 399,
5837 .pme_flags = 0x0,
5838 .pme_numasks = 0,
5839 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5840 .pme_ctr = 3,
5841 .pme_event = 0,
5842 .pme_chipno = 15,
5843 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5844 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5845 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5846 },
5847 /* M Counter 3 Event 1 */
5848 {
5849 .pme_name = "STALL_ASSOC@0",
5850 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 0)",
5851 .pme_code = 400,
5852 .pme_flags = 0x0,
5853 .pme_numasks = 0,
5854 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5855 .pme_ctr = 3,
5856 .pme_event = 1,
5857 .pme_chipno = 0,
5858 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5859 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5860 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5861 },
5862 {
5863 .pme_name = "STALL_ASSOC@1",
5864 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 1)",
5865 .pme_code = 401,
5866 .pme_flags = 0x0,
5867 .pme_numasks = 0,
5868 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5869 .pme_ctr = 3,
5870 .pme_event = 1,
5871 .pme_chipno = 1,
5872 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5873 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5874 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5875 },
5876 {
5877 .pme_name = "STALL_ASSOC@2",
5878 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 2)",
5879 .pme_code = 402,
5880 .pme_flags = 0x0,
5881 .pme_numasks = 0,
5882 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5883 .pme_ctr = 3,
5884 .pme_event = 1,
5885 .pme_chipno = 2,
5886 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5887 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5888 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5889 },
5890 {
5891 .pme_name = "STALL_ASSOC@3",
5892 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 3)",
5893 .pme_code = 403,
5894 .pme_flags = 0x0,
5895 .pme_numasks = 0,
5896 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5897 .pme_ctr = 3,
5898 .pme_event = 1,
5899 .pme_chipno = 3,
5900 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5901 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5902 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5903 },
5904 {
5905 .pme_name = "STALL_ASSOC@4",
5906 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 4)",
5907 .pme_code = 404,
5908 .pme_flags = 0x0,
5909 .pme_numasks = 0,
5910 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5911 .pme_ctr = 3,
5912 .pme_event = 1,
5913 .pme_chipno = 4,
5914 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5915 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5916 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5917 },
5918 {
5919 .pme_name = "STALL_ASSOC@5",
5920 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 5)",
5921 .pme_code = 405,
5922 .pme_flags = 0x0,
5923 .pme_numasks = 0,
5924 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5925 .pme_ctr = 3,
5926 .pme_event = 1,
5927 .pme_chipno = 5,
5928 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5929 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5930 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5931 },
5932 {
5933 .pme_name = "STALL_ASSOC@6",
5934 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 6)",
5935 .pme_code = 406,
5936 .pme_flags = 0x0,
5937 .pme_numasks = 0,
5938 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5939 .pme_ctr = 3,
5940 .pme_event = 1,
5941 .pme_chipno = 6,
5942 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5943 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5944 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5945 },
5946 {
5947 .pme_name = "STALL_ASSOC@7",
5948 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 7)",
5949 .pme_code = 407,
5950 .pme_flags = 0x0,
5951 .pme_numasks = 0,
5952 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5953 .pme_ctr = 3,
5954 .pme_event = 1,
5955 .pme_chipno = 7,
5956 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5957 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5958 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5959 },
5960 {
5961 .pme_name = "STALL_ASSOC@8",
5962 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 8)",
5963 .pme_code = 408,
5964 .pme_flags = 0x0,
5965 .pme_numasks = 0,
5966 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5967 .pme_ctr = 3,
5968 .pme_event = 1,
5969 .pme_chipno = 8,
5970 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5971 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5972 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5973 },
5974 {
5975 .pme_name = "STALL_ASSOC@9",
5976 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 9)",
5977 .pme_code = 409,
5978 .pme_flags = 0x0,
5979 .pme_numasks = 0,
5980 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5981 .pme_ctr = 3,
5982 .pme_event = 1,
5983 .pme_chipno = 9,
5984 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5985 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
5986 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
5987 },
5988 {
5989 .pme_name = "STALL_ASSOC@10",
5990 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 10)",
5991 .pme_code = 410,
5992 .pme_flags = 0x0,
5993 .pme_numasks = 0,
5994 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
5995 .pme_ctr = 3,
5996 .pme_event = 1,
5997 .pme_chipno = 10,
5998 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
5999 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6000 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6001 },
6002 {
6003 .pme_name = "STALL_ASSOC@11",
6004 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 11)",
6005 .pme_code = 411,
6006 .pme_flags = 0x0,
6007 .pme_numasks = 0,
6008 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6009 .pme_ctr = 3,
6010 .pme_event = 1,
6011 .pme_chipno = 11,
6012 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6013 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6014 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6015 },
6016 {
6017 .pme_name = "STALL_ASSOC@12",
6018 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 12)",
6019 .pme_code = 412,
6020 .pme_flags = 0x0,
6021 .pme_numasks = 0,
6022 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6023 .pme_ctr = 3,
6024 .pme_event = 1,
6025 .pme_chipno = 12,
6026 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6027 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6028 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6029 },
6030 {
6031 .pme_name = "STALL_ASSOC@13",
6032 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 13)",
6033 .pme_code = 413,
6034 .pme_flags = 0x0,
6035 .pme_numasks = 0,
6036 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6037 .pme_ctr = 3,
6038 .pme_event = 1,
6039 .pme_chipno = 13,
6040 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6041 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6042 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6043 },
6044 {
6045 .pme_name = "STALL_ASSOC@14",
6046 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 14)",
6047 .pme_code = 414,
6048 .pme_flags = 0x0,
6049 .pme_numasks = 0,
6050 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6051 .pme_ctr = 3,
6052 .pme_event = 1,
6053 .pme_chipno = 14,
6054 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6055 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6056 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6057 },
6058 {
6059 .pme_name = "STALL_ASSOC@15",
6060 .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 15)",
6061 .pme_code = 415,
6062 .pme_flags = 0x0,
6063 .pme_numasks = 0,
6064 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6065 .pme_ctr = 3,
6066 .pme_event = 1,
6067 .pme_chipno = 15,
6068 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6069 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6070 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6071 },
6072 /* M Counter 3 Event 2 */
6073 {
6074 .pme_name = "W_OUT_IDLE_3@0",
6075 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 0)",
6076 .pme_code = 416,
6077 .pme_flags = 0x0,
6078 .pme_numasks = 0,
6079 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6080 .pme_ctr = 3,
6081 .pme_event = 2,
6082 .pme_chipno = 0,
6083 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6084 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6085 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6086 },
6087 {
6088 .pme_name = "W_OUT_IDLE_3@1",
6089 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 1)",
6090 .pme_code = 417,
6091 .pme_flags = 0x0,
6092 .pme_numasks = 0,
6093 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6094 .pme_ctr = 3,
6095 .pme_event = 2,
6096 .pme_chipno = 1,
6097 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6098 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6099 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6100 },
6101 {
6102 .pme_name = "W_OUT_IDLE_3@2",
6103 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 2)",
6104 .pme_code = 418,
6105 .pme_flags = 0x0,
6106 .pme_numasks = 0,
6107 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6108 .pme_ctr = 3,
6109 .pme_event = 2,
6110 .pme_chipno = 2,
6111 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6112 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6113 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6114 },
6115 {
6116 .pme_name = "W_OUT_IDLE_3@3",
6117 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 3)",
6118 .pme_code = 419,
6119 .pme_flags = 0x0,
6120 .pme_numasks = 0,
6121 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6122 .pme_ctr = 3,
6123 .pme_event = 2,
6124 .pme_chipno = 3,
6125 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6126 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6127 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6128 },
6129 {
6130 .pme_name = "W_OUT_IDLE_3@4",
6131 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 4)",
6132 .pme_code = 420,
6133 .pme_flags = 0x0,
6134 .pme_numasks = 0,
6135 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6136 .pme_ctr = 3,
6137 .pme_event = 2,
6138 .pme_chipno = 4,
6139 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6140 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6141 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6142 },
6143 {
6144 .pme_name = "W_OUT_IDLE_3@5",
6145 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 5)",
6146 .pme_code = 421,
6147 .pme_flags = 0x0,
6148 .pme_numasks = 0,
6149 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6150 .pme_ctr = 3,
6151 .pme_event = 2,
6152 .pme_chipno = 5,
6153 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6154 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6155 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6156 },
6157 {
6158 .pme_name = "W_OUT_IDLE_3@6",
6159 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 6)",
6160 .pme_code = 422,
6161 .pme_flags = 0x0,
6162 .pme_numasks = 0,
6163 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6164 .pme_ctr = 3,
6165 .pme_event = 2,
6166 .pme_chipno = 6,
6167 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6168 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6169 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6170 },
6171 {
6172 .pme_name = "W_OUT_IDLE_3@7",
6173 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 7)",
6174 .pme_code = 423,
6175 .pme_flags = 0x0,
6176 .pme_numasks = 0,
6177 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6178 .pme_ctr = 3,
6179 .pme_event = 2,
6180 .pme_chipno = 7,
6181 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6182 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6183 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6184 },
6185 {
6186 .pme_name = "W_OUT_IDLE_3@8",
6187 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 8)",
6188 .pme_code = 424,
6189 .pme_flags = 0x0,
6190 .pme_numasks = 0,
6191 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6192 .pme_ctr = 3,
6193 .pme_event = 2,
6194 .pme_chipno = 8,
6195 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6196 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6197 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6198 },
6199 {
6200 .pme_name = "W_OUT_IDLE_3@9",
6201 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 9)",
6202 .pme_code = 425,
6203 .pme_flags = 0x0,
6204 .pme_numasks = 0,
6205 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6206 .pme_ctr = 3,
6207 .pme_event = 2,
6208 .pme_chipno = 9,
6209 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6210 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6211 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6212 },
6213 {
6214 .pme_name = "W_OUT_IDLE_3@10",
6215 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 10)",
6216 .pme_code = 426,
6217 .pme_flags = 0x0,
6218 .pme_numasks = 0,
6219 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6220 .pme_ctr = 3,
6221 .pme_event = 2,
6222 .pme_chipno = 10,
6223 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6224 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6225 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6226 },
6227 {
6228 .pme_name = "W_OUT_IDLE_3@11",
6229 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 11)",
6230 .pme_code = 427,
6231 .pme_flags = 0x0,
6232 .pme_numasks = 0,
6233 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6234 .pme_ctr = 3,
6235 .pme_event = 2,
6236 .pme_chipno = 11,
6237 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6238 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6239 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6240 },
6241 {
6242 .pme_name = "W_OUT_IDLE_3@12",
6243 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 12)",
6244 .pme_code = 428,
6245 .pme_flags = 0x0,
6246 .pme_numasks = 0,
6247 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6248 .pme_ctr = 3,
6249 .pme_event = 2,
6250 .pme_chipno = 12,
6251 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6252 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6253 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6254 },
6255 {
6256 .pme_name = "W_OUT_IDLE_3@13",
6257 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 13)",
6258 .pme_code = 429,
6259 .pme_flags = 0x0,
6260 .pme_numasks = 0,
6261 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6262 .pme_ctr = 3,
6263 .pme_event = 2,
6264 .pme_chipno = 13,
6265 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6266 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6267 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6268 },
6269 {
6270 .pme_name = "W_OUT_IDLE_3@14",
6271 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 14)",
6272 .pme_code = 430,
6273 .pme_flags = 0x0,
6274 .pme_numasks = 0,
6275 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6276 .pme_ctr = 3,
6277 .pme_event = 2,
6278 .pme_chipno = 14,
6279 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6280 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6281 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6282 },
6283 {
6284 .pme_name = "W_OUT_IDLE_3@15",
6285 .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 15)",
6286 .pme_code = 431,
6287 .pme_flags = 0x0,
6288 .pme_numasks = 0,
6289 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6290 .pme_ctr = 3,
6291 .pme_event = 2,
6292 .pme_chipno = 15,
6293 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6294 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6295 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6296 },
6297 /* M Counter 3 Event 3 */
6298 {
6299 .pme_name = "W_IN_IDLE_3@0",
6300 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 0)",
6301 .pme_code = 432,
6302 .pme_flags = 0x0,
6303 .pme_numasks = 0,
6304 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6305 .pme_ctr = 3,
6306 .pme_event = 3,
6307 .pme_chipno = 0,
6308 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6309 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6310 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6311 },
6312 {
6313 .pme_name = "W_IN_IDLE_3@1",
6314 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 1)",
6315 .pme_code = 433,
6316 .pme_flags = 0x0,
6317 .pme_numasks = 0,
6318 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6319 .pme_ctr = 3,
6320 .pme_event = 3,
6321 .pme_chipno = 1,
6322 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6323 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6324 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6325 },
6326 {
6327 .pme_name = "W_IN_IDLE_3@2",
6328 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 2)",
6329 .pme_code = 434,
6330 .pme_flags = 0x0,
6331 .pme_numasks = 0,
6332 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6333 .pme_ctr = 3,
6334 .pme_event = 3,
6335 .pme_chipno = 2,
6336 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6337 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6338 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6339 },
6340 {
6341 .pme_name = "W_IN_IDLE_3@3",
6342 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 3)",
6343 .pme_code = 435,
6344 .pme_flags = 0x0,
6345 .pme_numasks = 0,
6346 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6347 .pme_ctr = 3,
6348 .pme_event = 3,
6349 .pme_chipno = 3,
6350 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6351 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6352 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6353 },
6354 {
6355 .pme_name = "W_IN_IDLE_3@4",
6356 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 4)",
6357 .pme_code = 436,
6358 .pme_flags = 0x0,
6359 .pme_numasks = 0,
6360 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6361 .pme_ctr = 3,
6362 .pme_event = 3,
6363 .pme_chipno = 4,
6364 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6365 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6366 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6367 },
6368 {
6369 .pme_name = "W_IN_IDLE_3@5",
6370 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 5)",
6371 .pme_code = 437,
6372 .pme_flags = 0x0,
6373 .pme_numasks = 0,
6374 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6375 .pme_ctr = 3,
6376 .pme_event = 3,
6377 .pme_chipno = 5,
6378 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6379 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6380 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6381 },
6382 {
6383 .pme_name = "W_IN_IDLE_3@6",
6384 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 6)",
6385 .pme_code = 438,
6386 .pme_flags = 0x0,
6387 .pme_numasks = 0,
6388 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6389 .pme_ctr = 3,
6390 .pme_event = 3,
6391 .pme_chipno = 6,
6392 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6393 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6394 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6395 },
6396 {
6397 .pme_name = "W_IN_IDLE_3@7",
6398 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 7)",
6399 .pme_code = 439,
6400 .pme_flags = 0x0,
6401 .pme_numasks = 0,
6402 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6403 .pme_ctr = 3,
6404 .pme_event = 3,
6405 .pme_chipno = 7,
6406 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6407 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6408 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6409 },
6410 {
6411 .pme_name = "W_IN_IDLE_3@8",
6412 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 8)",
6413 .pme_code = 440,
6414 .pme_flags = 0x0,
6415 .pme_numasks = 0,
6416 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6417 .pme_ctr = 3,
6418 .pme_event = 3,
6419 .pme_chipno = 8,
6420 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6421 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6422 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6423 },
6424 {
6425 .pme_name = "W_IN_IDLE_3@9",
6426 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 9)",
6427 .pme_code = 441,
6428 .pme_flags = 0x0,
6429 .pme_numasks = 0,
6430 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6431 .pme_ctr = 3,
6432 .pme_event = 3,
6433 .pme_chipno = 9,
6434 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6435 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6436 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6437 },
6438 {
6439 .pme_name = "W_IN_IDLE_3@10",
6440 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 10)",
6441 .pme_code = 442,
6442 .pme_flags = 0x0,
6443 .pme_numasks = 0,
6444 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6445 .pme_ctr = 3,
6446 .pme_event = 3,
6447 .pme_chipno = 10,
6448 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6449 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6450 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6451 },
6452 {
6453 .pme_name = "W_IN_IDLE_3@11",
6454 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 11)",
6455 .pme_code = 443,
6456 .pme_flags = 0x0,
6457 .pme_numasks = 0,
6458 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6459 .pme_ctr = 3,
6460 .pme_event = 3,
6461 .pme_chipno = 11,
6462 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6463 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6464 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6465 },
6466 {
6467 .pme_name = "W_IN_IDLE_3@12",
6468 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 12)",
6469 .pme_code = 444,
6470 .pme_flags = 0x0,
6471 .pme_numasks = 0,
6472 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6473 .pme_ctr = 3,
6474 .pme_event = 3,
6475 .pme_chipno = 12,
6476 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6477 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6478 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6479 },
6480 {
6481 .pme_name = "W_IN_IDLE_3@13",
6482 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 13)",
6483 .pme_code = 445,
6484 .pme_flags = 0x0,
6485 .pme_numasks = 0,
6486 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6487 .pme_ctr = 3,
6488 .pme_event = 3,
6489 .pme_chipno = 13,
6490 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6491 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6492 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6493 },
6494 {
6495 .pme_name = "W_IN_IDLE_3@14",
6496 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 14)",
6497 .pme_code = 446,
6498 .pme_flags = 0x0,
6499 .pme_numasks = 0,
6500 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6501 .pme_ctr = 3,
6502 .pme_event = 3,
6503 .pme_chipno = 14,
6504 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6505 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6506 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6507 },
6508 {
6509 .pme_name = "W_IN_IDLE_3@15",
6510 .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 15)",
6511 .pme_code = 447,
6512 .pme_flags = 0x0,
6513 .pme_numasks = 0,
6514 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6515 .pme_ctr = 3,
6516 .pme_event = 3,
6517 .pme_chipno = 15,
6518 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6519 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6520 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6521 },
6522 /* M Counter 4 Event 0 */
6523 {
6524 .pme_name = "READ_REQ_SHARED@0",
6525 .pme_desc = "Read requests satisfied from the Shared state. (M chip 0)",
6526 .pme_code = 448,
6527 .pme_flags = 0x0,
6528 .pme_numasks = 0,
6529 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6530 .pme_ctr = 4,
6531 .pme_event = 0,
6532 .pme_chipno = 0,
6533 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6534 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6535 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6536 },
6537 {
6538 .pme_name = "READ_REQ_SHARED@1",
6539 .pme_desc = "Read requests satisfied from the Shared state. (M chip 1)",
6540 .pme_code = 449,
6541 .pme_flags = 0x0,
6542 .pme_numasks = 0,
6543 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6544 .pme_ctr = 4,
6545 .pme_event = 0,
6546 .pme_chipno = 1,
6547 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6548 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6549 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6550 },
6551 {
6552 .pme_name = "READ_REQ_SHARED@2",
6553 .pme_desc = "Read requests satisfied from the Shared state. (M chip 2)",
6554 .pme_code = 450,
6555 .pme_flags = 0x0,
6556 .pme_numasks = 0,
6557 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6558 .pme_ctr = 4,
6559 .pme_event = 0,
6560 .pme_chipno = 2,
6561 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6562 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6563 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6564 },
6565 {
6566 .pme_name = "READ_REQ_SHARED@3",
6567 .pme_desc = "Read requests satisfied from the Shared state. (M chip 3)",
6568 .pme_code = 451,
6569 .pme_flags = 0x0,
6570 .pme_numasks = 0,
6571 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6572 .pme_ctr = 4,
6573 .pme_event = 0,
6574 .pme_chipno = 3,
6575 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6576 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6577 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6578 },
6579 {
6580 .pme_name = "READ_REQ_SHARED@4",
6581 .pme_desc = "Read requests satisfied from the Shared state. (M chip 4)",
6582 .pme_code = 452,
6583 .pme_flags = 0x0,
6584 .pme_numasks = 0,
6585 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6586 .pme_ctr = 4,
6587 .pme_event = 0,
6588 .pme_chipno = 4,
6589 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6590 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6591 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6592 },
6593 {
6594 .pme_name = "READ_REQ_SHARED@5",
6595 .pme_desc = "Read requests satisfied from the Shared state. (M chip 5)",
6596 .pme_code = 453,
6597 .pme_flags = 0x0,
6598 .pme_numasks = 0,
6599 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6600 .pme_ctr = 4,
6601 .pme_event = 0,
6602 .pme_chipno = 5,
6603 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6604 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6605 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6606 },
6607 {
6608 .pme_name = "READ_REQ_SHARED@6",
6609 .pme_desc = "Read requests satisfied from the Shared state. (M chip 6)",
6610 .pme_code = 454,
6611 .pme_flags = 0x0,
6612 .pme_numasks = 0,
6613 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6614 .pme_ctr = 4,
6615 .pme_event = 0,
6616 .pme_chipno = 6,
6617 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6618 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6619 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6620 },
6621 {
6622 .pme_name = "READ_REQ_SHARED@7",
6623 .pme_desc = "Read requests satisfied from the Shared state. (M chip 7)",
6624 .pme_code = 455,
6625 .pme_flags = 0x0,
6626 .pme_numasks = 0,
6627 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6628 .pme_ctr = 4,
6629 .pme_event = 0,
6630 .pme_chipno = 7,
6631 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6632 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6633 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6634 },
6635 {
6636 .pme_name = "READ_REQ_SHARED@8",
6637 .pme_desc = "Read requests satisfied from the Shared state. (M chip 8)",
6638 .pme_code = 456,
6639 .pme_flags = 0x0,
6640 .pme_numasks = 0,
6641 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6642 .pme_ctr = 4,
6643 .pme_event = 0,
6644 .pme_chipno = 8,
6645 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6646 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6647 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6648 },
6649 {
6650 .pme_name = "READ_REQ_SHARED@9",
6651 .pme_desc = "Read requests satisfied from the Shared state. (M chip 9)",
6652 .pme_code = 457,
6653 .pme_flags = 0x0,
6654 .pme_numasks = 0,
6655 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6656 .pme_ctr = 4,
6657 .pme_event = 0,
6658 .pme_chipno = 9,
6659 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6660 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6661 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6662 },
6663 {
6664 .pme_name = "READ_REQ_SHARED@10",
6665 .pme_desc = "Read requests satisfied from the Shared state. (M chip 10)",
6666 .pme_code = 458,
6667 .pme_flags = 0x0,
6668 .pme_numasks = 0,
6669 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6670 .pme_ctr = 4,
6671 .pme_event = 0,
6672 .pme_chipno = 10,
6673 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6674 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6675 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6676 },
6677 {
6678 .pme_name = "READ_REQ_SHARED@11",
6679 .pme_desc = "Read requests satisfied from the Shared state. (M chip 11)",
6680 .pme_code = 459,
6681 .pme_flags = 0x0,
6682 .pme_numasks = 0,
6683 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6684 .pme_ctr = 4,
6685 .pme_event = 0,
6686 .pme_chipno = 11,
6687 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6688 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6689 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6690 },
6691 {
6692 .pme_name = "READ_REQ_SHARED@12",
6693 .pme_desc = "Read requests satisfied from the Shared state. (M chip 12)",
6694 .pme_code = 460,
6695 .pme_flags = 0x0,
6696 .pme_numasks = 0,
6697 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6698 .pme_ctr = 4,
6699 .pme_event = 0,
6700 .pme_chipno = 12,
6701 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6702 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6703 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6704 },
6705 {
6706 .pme_name = "READ_REQ_SHARED@13",
6707 .pme_desc = "Read requests satisfied from the Shared state. (M chip 13)",
6708 .pme_code = 461,
6709 .pme_flags = 0x0,
6710 .pme_numasks = 0,
6711 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6712 .pme_ctr = 4,
6713 .pme_event = 0,
6714 .pme_chipno = 13,
6715 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6716 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6717 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6718 },
6719 {
6720 .pme_name = "READ_REQ_SHARED@14",
6721 .pme_desc = "Read requests satisfied from the Shared state. (M chip 14)",
6722 .pme_code = 462,
6723 .pme_flags = 0x0,
6724 .pme_numasks = 0,
6725 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6726 .pme_ctr = 4,
6727 .pme_event = 0,
6728 .pme_chipno = 14,
6729 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6730 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6731 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6732 },
6733 {
6734 .pme_name = "READ_REQ_SHARED@15",
6735 .pme_desc = "Read requests satisfied from the Shared state. (M chip 15)",
6736 .pme_code = 463,
6737 .pme_flags = 0x0,
6738 .pme_numasks = 0,
6739 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6740 .pme_ctr = 4,
6741 .pme_event = 0,
6742 .pme_chipno = 15,
6743 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6744 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6745 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6746 },
6747 /* M Counter 4 Event 1 */
6748 {
6749 .pme_name = "STALL_VN1_BLOCKED@0",
6750 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 0)",
6751 .pme_code = 464,
6752 .pme_flags = 0x0,
6753 .pme_numasks = 0,
6754 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6755 .pme_ctr = 4,
6756 .pme_event = 1,
6757 .pme_chipno = 0,
6758 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6759 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6760 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6761 },
6762 {
6763 .pme_name = "STALL_VN1_BLOCKED@1",
6764 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 1)",
6765 .pme_code = 465,
6766 .pme_flags = 0x0,
6767 .pme_numasks = 0,
6768 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6769 .pme_ctr = 4,
6770 .pme_event = 1,
6771 .pme_chipno = 1,
6772 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6773 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6774 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6775 },
6776 {
6777 .pme_name = "STALL_VN1_BLOCKED@2",
6778 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 2)",
6779 .pme_code = 466,
6780 .pme_flags = 0x0,
6781 .pme_numasks = 0,
6782 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6783 .pme_ctr = 4,
6784 .pme_event = 1,
6785 .pme_chipno = 2,
6786 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6787 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6788 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6789 },
6790 {
6791 .pme_name = "STALL_VN1_BLOCKED@3",
6792 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 3)",
6793 .pme_code = 467,
6794 .pme_flags = 0x0,
6795 .pme_numasks = 0,
6796 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6797 .pme_ctr = 4,
6798 .pme_event = 1,
6799 .pme_chipno = 3,
6800 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6801 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6802 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6803 },
6804 {
6805 .pme_name = "STALL_VN1_BLOCKED@4",
6806 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 4)",
6807 .pme_code = 468,
6808 .pme_flags = 0x0,
6809 .pme_numasks = 0,
6810 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6811 .pme_ctr = 4,
6812 .pme_event = 1,
6813 .pme_chipno = 4,
6814 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6815 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6816 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6817 },
6818 {
6819 .pme_name = "STALL_VN1_BLOCKED@5",
6820 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 5)",
6821 .pme_code = 469,
6822 .pme_flags = 0x0,
6823 .pme_numasks = 0,
6824 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6825 .pme_ctr = 4,
6826 .pme_event = 1,
6827 .pme_chipno = 5,
6828 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6829 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6830 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6831 },
6832 {
6833 .pme_name = "STALL_VN1_BLOCKED@6",
6834 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 6)",
6835 .pme_code = 470,
6836 .pme_flags = 0x0,
6837 .pme_numasks = 0,
6838 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6839 .pme_ctr = 4,
6840 .pme_event = 1,
6841 .pme_chipno = 6,
6842 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6843 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6844 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6845 },
6846 {
6847 .pme_name = "STALL_VN1_BLOCKED@7",
6848 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 7)",
6849 .pme_code = 471,
6850 .pme_flags = 0x0,
6851 .pme_numasks = 0,
6852 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6853 .pme_ctr = 4,
6854 .pme_event = 1,
6855 .pme_chipno = 7,
6856 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6857 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6858 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6859 },
6860 {
6861 .pme_name = "STALL_VN1_BLOCKED@8",
6862 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 8)",
6863 .pme_code = 472,
6864 .pme_flags = 0x0,
6865 .pme_numasks = 0,
6866 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6867 .pme_ctr = 4,
6868 .pme_event = 1,
6869 .pme_chipno = 8,
6870 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6871 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6872 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6873 },
6874 {
6875 .pme_name = "STALL_VN1_BLOCKED@9",
6876 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 9)",
6877 .pme_code = 473,
6878 .pme_flags = 0x0,
6879 .pme_numasks = 0,
6880 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6881 .pme_ctr = 4,
6882 .pme_event = 1,
6883 .pme_chipno = 9,
6884 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6885 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6886 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6887 },
6888 {
6889 .pme_name = "STALL_VN1_BLOCKED@10",
6890 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 10)",
6891 .pme_code = 474,
6892 .pme_flags = 0x0,
6893 .pme_numasks = 0,
6894 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6895 .pme_ctr = 4,
6896 .pme_event = 1,
6897 .pme_chipno = 10,
6898 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6899 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6900 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6901 },
6902 {
6903 .pme_name = "STALL_VN1_BLOCKED@11",
6904 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 11)",
6905 .pme_code = 475,
6906 .pme_flags = 0x0,
6907 .pme_numasks = 0,
6908 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6909 .pme_ctr = 4,
6910 .pme_event = 1,
6911 .pme_chipno = 11,
6912 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6913 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6914 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6915 },
6916 {
6917 .pme_name = "STALL_VN1_BLOCKED@12",
6918 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 12)",
6919 .pme_code = 476,
6920 .pme_flags = 0x0,
6921 .pme_numasks = 0,
6922 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6923 .pme_ctr = 4,
6924 .pme_event = 1,
6925 .pme_chipno = 12,
6926 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6927 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6928 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6929 },
6930 {
6931 .pme_name = "STALL_VN1_BLOCKED@13",
6932 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 13)",
6933 .pme_code = 477,
6934 .pme_flags = 0x0,
6935 .pme_numasks = 0,
6936 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6937 .pme_ctr = 4,
6938 .pme_event = 1,
6939 .pme_chipno = 13,
6940 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6941 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6942 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6943 },
6944 {
6945 .pme_name = "STALL_VN1_BLOCKED@14",
6946 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 14)",
6947 .pme_code = 478,
6948 .pme_flags = 0x0,
6949 .pme_numasks = 0,
6950 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6951 .pme_ctr = 4,
6952 .pme_event = 1,
6953 .pme_chipno = 14,
6954 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6955 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6956 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6957 },
6958 {
6959 .pme_name = "STALL_VN1_BLOCKED@15",
6960 .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 15)",
6961 .pme_code = 479,
6962 .pme_flags = 0x0,
6963 .pme_numasks = 0,
6964 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6965 .pme_ctr = 4,
6966 .pme_event = 1,
6967 .pme_chipno = 15,
6968 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6969 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6970 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6971 },
6972 /* M Counter 4 Event 2 */
6973 {
6974 .pme_name = "W_IN_FLOWING_0@0",
6975 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 0)",
6976 .pme_code = 480,
6977 .pme_flags = 0x0,
6978 .pme_numasks = 0,
6979 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6980 .pme_ctr = 4,
6981 .pme_event = 2,
6982 .pme_chipno = 0,
6983 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6984 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6985 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
6986 },
6987 {
6988 .pme_name = "W_IN_FLOWING_0@1",
6989 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 1)",
6990 .pme_code = 481,
6991 .pme_flags = 0x0,
6992 .pme_numasks = 0,
6993 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
6994 .pme_ctr = 4,
6995 .pme_event = 2,
6996 .pme_chipno = 1,
6997 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
6998 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
6999 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7000 },
7001 {
7002 .pme_name = "W_IN_FLOWING_0@2",
7003 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 2)",
7004 .pme_code = 482,
7005 .pme_flags = 0x0,
7006 .pme_numasks = 0,
7007 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7008 .pme_ctr = 4,
7009 .pme_event = 2,
7010 .pme_chipno = 2,
7011 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7012 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7013 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7014 },
7015 {
7016 .pme_name = "W_IN_FLOWING_0@3",
7017 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 3)",
7018 .pme_code = 483,
7019 .pme_flags = 0x0,
7020 .pme_numasks = 0,
7021 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7022 .pme_ctr = 4,
7023 .pme_event = 2,
7024 .pme_chipno = 3,
7025 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7026 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7027 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7028 },
7029 {
7030 .pme_name = "W_IN_FLOWING_0@4",
7031 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 4)",
7032 .pme_code = 484,
7033 .pme_flags = 0x0,
7034 .pme_numasks = 0,
7035 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7036 .pme_ctr = 4,
7037 .pme_event = 2,
7038 .pme_chipno = 4,
7039 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7040 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7041 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7042 },
7043 {
7044 .pme_name = "W_IN_FLOWING_0@5",
7045 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 5)",
7046 .pme_code = 485,
7047 .pme_flags = 0x0,
7048 .pme_numasks = 0,
7049 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7050 .pme_ctr = 4,
7051 .pme_event = 2,
7052 .pme_chipno = 5,
7053 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7054 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7055 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7056 },
7057 {
7058 .pme_name = "W_IN_FLOWING_0@6",
7059 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 6)",
7060 .pme_code = 486,
7061 .pme_flags = 0x0,
7062 .pme_numasks = 0,
7063 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7064 .pme_ctr = 4,
7065 .pme_event = 2,
7066 .pme_chipno = 6,
7067 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7068 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7069 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7070 },
7071 {
7072 .pme_name = "W_IN_FLOWING_0@7",
7073 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 7)",
7074 .pme_code = 487,
7075 .pme_flags = 0x0,
7076 .pme_numasks = 0,
7077 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7078 .pme_ctr = 4,
7079 .pme_event = 2,
7080 .pme_chipno = 7,
7081 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7082 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7083 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7084 },
7085 {
7086 .pme_name = "W_IN_FLOWING_0@8",
7087 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 8)",
7088 .pme_code = 488,
7089 .pme_flags = 0x0,
7090 .pme_numasks = 0,
7091 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7092 .pme_ctr = 4,
7093 .pme_event = 2,
7094 .pme_chipno = 8,
7095 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7096 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7097 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7098 },
7099 {
7100 .pme_name = "W_IN_FLOWING_0@9",
7101 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 9)",
7102 .pme_code = 489,
7103 .pme_flags = 0x0,
7104 .pme_numasks = 0,
7105 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7106 .pme_ctr = 4,
7107 .pme_event = 2,
7108 .pme_chipno = 9,
7109 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7110 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7111 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7112 },
7113 {
7114 .pme_name = "W_IN_FLOWING_0@10",
7115 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 10)",
7116 .pme_code = 490,
7117 .pme_flags = 0x0,
7118 .pme_numasks = 0,
7119 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7120 .pme_ctr = 4,
7121 .pme_event = 2,
7122 .pme_chipno = 10,
7123 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7124 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7125 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7126 },
7127 {
7128 .pme_name = "W_IN_FLOWING_0@11",
7129 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 11)",
7130 .pme_code = 491,
7131 .pme_flags = 0x0,
7132 .pme_numasks = 0,
7133 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7134 .pme_ctr = 4,
7135 .pme_event = 2,
7136 .pme_chipno = 11,
7137 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7138 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7139 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7140 },
7141 {
7142 .pme_name = "W_IN_FLOWING_0@12",
7143 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 12)",
7144 .pme_code = 492,
7145 .pme_flags = 0x0,
7146 .pme_numasks = 0,
7147 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7148 .pme_ctr = 4,
7149 .pme_event = 2,
7150 .pme_chipno = 12,
7151 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7152 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7153 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7154 },
7155 {
7156 .pme_name = "W_IN_FLOWING_0@13",
7157 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 13)",
7158 .pme_code = 493,
7159 .pme_flags = 0x0,
7160 .pme_numasks = 0,
7161 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7162 .pme_ctr = 4,
7163 .pme_event = 2,
7164 .pme_chipno = 13,
7165 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7166 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7167 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7168 },
7169 {
7170 .pme_name = "W_IN_FLOWING_0@14",
7171 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 14)",
7172 .pme_code = 494,
7173 .pme_flags = 0x0,
7174 .pme_numasks = 0,
7175 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7176 .pme_ctr = 4,
7177 .pme_event = 2,
7178 .pme_chipno = 14,
7179 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7180 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7181 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7182 },
7183 {
7184 .pme_name = "W_IN_FLOWING_0@15",
7185 .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 15)",
7186 .pme_code = 495,
7187 .pme_flags = 0x0,
7188 .pme_numasks = 0,
7189 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7190 .pme_ctr = 4,
7191 .pme_event = 2,
7192 .pme_chipno = 15,
7193 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7194 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7195 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7196 },
7197 /* M Counter 4 Event 3 */
7198 {
7199 .pme_name = "W_OUT_FLOWING_0@0",
7200 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 0)",
7201 .pme_code = 496,
7202 .pme_flags = 0x0,
7203 .pme_numasks = 0,
7204 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7205 .pme_ctr = 4,
7206 .pme_event = 3,
7207 .pme_chipno = 0,
7208 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7209 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7210 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7211 },
7212 {
7213 .pme_name = "W_OUT_FLOWING_0@1",
7214 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 1)",
7215 .pme_code = 497,
7216 .pme_flags = 0x0,
7217 .pme_numasks = 0,
7218 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7219 .pme_ctr = 4,
7220 .pme_event = 3,
7221 .pme_chipno = 1,
7222 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7223 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7224 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7225 },
7226 {
7227 .pme_name = "W_OUT_FLOWING_0@2",
7228 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 2)",
7229 .pme_code = 498,
7230 .pme_flags = 0x0,
7231 .pme_numasks = 0,
7232 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7233 .pme_ctr = 4,
7234 .pme_event = 3,
7235 .pme_chipno = 2,
7236 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7237 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7238 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7239 },
7240 {
7241 .pme_name = "W_OUT_FLOWING_0@3",
7242 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 3)",
7243 .pme_code = 499,
7244 .pme_flags = 0x0,
7245 .pme_numasks = 0,
7246 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7247 .pme_ctr = 4,
7248 .pme_event = 3,
7249 .pme_chipno = 3,
7250 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7251 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7252 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7253 },
7254 {
7255 .pme_name = "W_OUT_FLOWING_0@4",
7256 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 4)",
7257 .pme_code = 500,
7258 .pme_flags = 0x0,
7259 .pme_numasks = 0,
7260 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7261 .pme_ctr = 4,
7262 .pme_event = 3,
7263 .pme_chipno = 4,
7264 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7265 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7266 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7267 },
7268 {
7269 .pme_name = "W_OUT_FLOWING_0@5",
7270 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 5)",
7271 .pme_code = 501,
7272 .pme_flags = 0x0,
7273 .pme_numasks = 0,
7274 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7275 .pme_ctr = 4,
7276 .pme_event = 3,
7277 .pme_chipno = 5,
7278 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7279 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7280 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7281 },
7282 {
7283 .pme_name = "W_OUT_FLOWING_0@6",
7284 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 6)",
7285 .pme_code = 502,
7286 .pme_flags = 0x0,
7287 .pme_numasks = 0,
7288 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7289 .pme_ctr = 4,
7290 .pme_event = 3,
7291 .pme_chipno = 6,
7292 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7293 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7294 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7295 },
7296 {
7297 .pme_name = "W_OUT_FLOWING_0@7",
7298 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 7)",
7299 .pme_code = 503,
7300 .pme_flags = 0x0,
7301 .pme_numasks = 0,
7302 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7303 .pme_ctr = 4,
7304 .pme_event = 3,
7305 .pme_chipno = 7,
7306 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7307 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7308 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7309 },
7310 {
7311 .pme_name = "W_OUT_FLOWING_0@8",
7312 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 8)",
7313 .pme_code = 504,
7314 .pme_flags = 0x0,
7315 .pme_numasks = 0,
7316 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7317 .pme_ctr = 4,
7318 .pme_event = 3,
7319 .pme_chipno = 8,
7320 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7321 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7322 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7323 },
7324 {
7325 .pme_name = "W_OUT_FLOWING_0@9",
7326 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 9)",
7327 .pme_code = 505,
7328 .pme_flags = 0x0,
7329 .pme_numasks = 0,
7330 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7331 .pme_ctr = 4,
7332 .pme_event = 3,
7333 .pme_chipno = 9,
7334 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7335 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7336 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7337 },
7338 {
7339 .pme_name = "W_OUT_FLOWING_0@10",
7340 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 10)",
7341 .pme_code = 506,
7342 .pme_flags = 0x0,
7343 .pme_numasks = 0,
7344 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7345 .pme_ctr = 4,
7346 .pme_event = 3,
7347 .pme_chipno = 10,
7348 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7349 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7350 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7351 },
7352 {
7353 .pme_name = "W_OUT_FLOWING_0@11",
7354 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 11)",
7355 .pme_code = 507,
7356 .pme_flags = 0x0,
7357 .pme_numasks = 0,
7358 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7359 .pme_ctr = 4,
7360 .pme_event = 3,
7361 .pme_chipno = 11,
7362 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7363 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7364 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7365 },
7366 {
7367 .pme_name = "W_OUT_FLOWING_0@12",
7368 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 12)",
7369 .pme_code = 508,
7370 .pme_flags = 0x0,
7371 .pme_numasks = 0,
7372 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7373 .pme_ctr = 4,
7374 .pme_event = 3,
7375 .pme_chipno = 12,
7376 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7377 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7378 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7379 },
7380 {
7381 .pme_name = "W_OUT_FLOWING_0@13",
7382 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 13)",
7383 .pme_code = 509,
7384 .pme_flags = 0x0,
7385 .pme_numasks = 0,
7386 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7387 .pme_ctr = 4,
7388 .pme_event = 3,
7389 .pme_chipno = 13,
7390 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7391 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7392 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7393 },
7394 {
7395 .pme_name = "W_OUT_FLOWING_0@14",
7396 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 14)",
7397 .pme_code = 510,
7398 .pme_flags = 0x0,
7399 .pme_numasks = 0,
7400 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7401 .pme_ctr = 4,
7402 .pme_event = 3,
7403 .pme_chipno = 14,
7404 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7405 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7406 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7407 },
7408 {
7409 .pme_name = "W_OUT_FLOWING_0@15",
7410 .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 15)",
7411 .pme_code = 511,
7412 .pme_flags = 0x0,
7413 .pme_numasks = 0,
7414 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7415 .pme_ctr = 4,
7416 .pme_event = 3,
7417 .pme_chipno = 15,
7418 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7419 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7420 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7421 },
7422 /* M Counter 5 Event 0 */
7423 {
7424 .pme_name = "FWD_REQ_TO_OWNER@0",
7425 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 0)",
7426 .pme_code = 512,
7427 .pme_flags = 0x0,
7428 .pme_numasks = 0,
7429 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7430 .pme_ctr = 5,
7431 .pme_event = 0,
7432 .pme_chipno = 0,
7433 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7434 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7435 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7436 },
7437 {
7438 .pme_name = "FWD_REQ_TO_OWNER@1",
7439 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 1)",
7440 .pme_code = 513,
7441 .pme_flags = 0x0,
7442 .pme_numasks = 0,
7443 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7444 .pme_ctr = 5,
7445 .pme_event = 0,
7446 .pme_chipno = 1,
7447 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7448 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7449 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7450 },
7451 {
7452 .pme_name = "FWD_REQ_TO_OWNER@2",
7453 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 2)",
7454 .pme_code = 514,
7455 .pme_flags = 0x0,
7456 .pme_numasks = 0,
7457 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7458 .pme_ctr = 5,
7459 .pme_event = 0,
7460 .pme_chipno = 2,
7461 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7462 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7463 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7464 },
7465 {
7466 .pme_name = "FWD_REQ_TO_OWNER@3",
7467 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 3)",
7468 .pme_code = 515,
7469 .pme_flags = 0x0,
7470 .pme_numasks = 0,
7471 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7472 .pme_ctr = 5,
7473 .pme_event = 0,
7474 .pme_chipno = 3,
7475 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7476 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7477 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7478 },
7479 {
7480 .pme_name = "FWD_REQ_TO_OWNER@4",
7481 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 4)",
7482 .pme_code = 516,
7483 .pme_flags = 0x0,
7484 .pme_numasks = 0,
7485 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7486 .pme_ctr = 5,
7487 .pme_event = 0,
7488 .pme_chipno = 4,
7489 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7490 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7491 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7492 },
7493 {
7494 .pme_name = "FWD_REQ_TO_OWNER@5",
7495 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 5)",
7496 .pme_code = 517,
7497 .pme_flags = 0x0,
7498 .pme_numasks = 0,
7499 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7500 .pme_ctr = 5,
7501 .pme_event = 0,
7502 .pme_chipno = 5,
7503 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7504 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7505 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7506 },
7507 {
7508 .pme_name = "FWD_REQ_TO_OWNER@6",
7509 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 6)",
7510 .pme_code = 518,
7511 .pme_flags = 0x0,
7512 .pme_numasks = 0,
7513 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7514 .pme_ctr = 5,
7515 .pme_event = 0,
7516 .pme_chipno = 6,
7517 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7518 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7519 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7520 },
7521 {
7522 .pme_name = "FWD_REQ_TO_OWNER@7",
7523 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 7)",
7524 .pme_code = 519,
7525 .pme_flags = 0x0,
7526 .pme_numasks = 0,
7527 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7528 .pme_ctr = 5,
7529 .pme_event = 0,
7530 .pme_chipno = 7,
7531 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7532 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7533 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7534 },
7535 {
7536 .pme_name = "FWD_REQ_TO_OWNER@8",
7537 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 8)",
7538 .pme_code = 520,
7539 .pme_flags = 0x0,
7540 .pme_numasks = 0,
7541 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7542 .pme_ctr = 5,
7543 .pme_event = 0,
7544 .pme_chipno = 8,
7545 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7546 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7547 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7548 },
7549 {
7550 .pme_name = "FWD_REQ_TO_OWNER@9",
7551 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 9)",
7552 .pme_code = 521,
7553 .pme_flags = 0x0,
7554 .pme_numasks = 0,
7555 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7556 .pme_ctr = 5,
7557 .pme_event = 0,
7558 .pme_chipno = 9,
7559 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7560 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7561 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7562 },
7563 {
7564 .pme_name = "FWD_REQ_TO_OWNER@10",
7565 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 10)",
7566 .pme_code = 522,
7567 .pme_flags = 0x0,
7568 .pme_numasks = 0,
7569 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7570 .pme_ctr = 5,
7571 .pme_event = 0,
7572 .pme_chipno = 10,
7573 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7574 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7575 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7576 },
7577 {
7578 .pme_name = "FWD_REQ_TO_OWNER@11",
7579 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 11)",
7580 .pme_code = 523,
7581 .pme_flags = 0x0,
7582 .pme_numasks = 0,
7583 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7584 .pme_ctr = 5,
7585 .pme_event = 0,
7586 .pme_chipno = 11,
7587 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7588 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7589 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7590 },
7591 {
7592 .pme_name = "FWD_REQ_TO_OWNER@12",
7593 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 12)",
7594 .pme_code = 524,
7595 .pme_flags = 0x0,
7596 .pme_numasks = 0,
7597 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7598 .pme_ctr = 5,
7599 .pme_event = 0,
7600 .pme_chipno = 12,
7601 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7602 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7603 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7604 },
7605 {
7606 .pme_name = "FWD_REQ_TO_OWNER@13",
7607 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 13)",
7608 .pme_code = 525,
7609 .pme_flags = 0x0,
7610 .pme_numasks = 0,
7611 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7612 .pme_ctr = 5,
7613 .pme_event = 0,
7614 .pme_chipno = 13,
7615 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7616 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7617 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7618 },
7619 {
7620 .pme_name = "FWD_REQ_TO_OWNER@14",
7621 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 14)",
7622 .pme_code = 526,
7623 .pme_flags = 0x0,
7624 .pme_numasks = 0,
7625 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7626 .pme_ctr = 5,
7627 .pme_event = 0,
7628 .pme_chipno = 14,
7629 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7630 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7631 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7632 },
7633 {
7634 .pme_name = "FWD_REQ_TO_OWNER@15",
7635 .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 15)",
7636 .pme_code = 527,
7637 .pme_flags = 0x0,
7638 .pme_numasks = 0,
7639 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7640 .pme_ctr = 5,
7641 .pme_event = 0,
7642 .pme_chipno = 15,
7643 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7644 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7645 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7646 },
7647 /* M Counter 5 Event 1 */
7648 {
7649 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@0",
7650 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 0)",
7651 .pme_code = 528,
7652 .pme_flags = 0x0,
7653 .pme_numasks = 0,
7654 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7655 .pme_ctr = 5,
7656 .pme_event = 1,
7657 .pme_chipno = 0,
7658 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7659 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7660 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7661 },
7662 {
7663 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@1",
7664 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 1)",
7665 .pme_code = 529,
7666 .pme_flags = 0x0,
7667 .pme_numasks = 0,
7668 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7669 .pme_ctr = 5,
7670 .pme_event = 1,
7671 .pme_chipno = 1,
7672 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7673 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7674 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7675 },
7676 {
7677 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@2",
7678 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 2)",
7679 .pme_code = 530,
7680 .pme_flags = 0x0,
7681 .pme_numasks = 0,
7682 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7683 .pme_ctr = 5,
7684 .pme_event = 1,
7685 .pme_chipno = 2,
7686 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7687 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7688 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7689 },
7690 {
7691 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@3",
7692 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 3)",
7693 .pme_code = 531,
7694 .pme_flags = 0x0,
7695 .pme_numasks = 0,
7696 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7697 .pme_ctr = 5,
7698 .pme_event = 1,
7699 .pme_chipno = 3,
7700 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7701 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7702 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7703 },
7704 {
7705 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@4",
7706 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 4)",
7707 .pme_code = 532,
7708 .pme_flags = 0x0,
7709 .pme_numasks = 0,
7710 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7711 .pme_ctr = 5,
7712 .pme_event = 1,
7713 .pme_chipno = 4,
7714 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7715 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7716 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7717 },
7718 {
7719 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@5",
7720 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 5)",
7721 .pme_code = 533,
7722 .pme_flags = 0x0,
7723 .pme_numasks = 0,
7724 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7725 .pme_ctr = 5,
7726 .pme_event = 1,
7727 .pme_chipno = 5,
7728 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7729 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7730 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7731 },
7732 {
7733 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@6",
7734 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 6)",
7735 .pme_code = 534,
7736 .pme_flags = 0x0,
7737 .pme_numasks = 0,
7738 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7739 .pme_ctr = 5,
7740 .pme_event = 1,
7741 .pme_chipno = 6,
7742 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7743 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7744 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7745 },
7746 {
7747 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@7",
7748 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 7)",
7749 .pme_code = 535,
7750 .pme_flags = 0x0,
7751 .pme_numasks = 0,
7752 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7753 .pme_ctr = 5,
7754 .pme_event = 1,
7755 .pme_chipno = 7,
7756 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7757 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7758 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7759 },
7760 {
7761 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@8",
7762 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 8)",
7763 .pme_code = 536,
7764 .pme_flags = 0x0,
7765 .pme_numasks = 0,
7766 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7767 .pme_ctr = 5,
7768 .pme_event = 1,
7769 .pme_chipno = 8,
7770 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7771 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7772 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7773 },
7774 {
7775 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@9",
7776 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 9)",
7777 .pme_code = 537,
7778 .pme_flags = 0x0,
7779 .pme_numasks = 0,
7780 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7781 .pme_ctr = 5,
7782 .pme_event = 1,
7783 .pme_chipno = 9,
7784 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7785 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7786 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7787 },
7788 {
7789 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@10",
7790 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 10)",
7791 .pme_code = 538,
7792 .pme_flags = 0x0,
7793 .pme_numasks = 0,
7794 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7795 .pme_ctr = 5,
7796 .pme_event = 1,
7797 .pme_chipno = 10,
7798 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7799 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7800 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7801 },
7802 {
7803 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@11",
7804 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 11)",
7805 .pme_code = 539,
7806 .pme_flags = 0x0,
7807 .pme_numasks = 0,
7808 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7809 .pme_ctr = 5,
7810 .pme_event = 1,
7811 .pme_chipno = 11,
7812 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7813 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7814 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7815 },
7816 {
7817 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@12",
7818 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 12)",
7819 .pme_code = 540,
7820 .pme_flags = 0x0,
7821 .pme_numasks = 0,
7822 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7823 .pme_ctr = 5,
7824 .pme_event = 1,
7825 .pme_chipno = 12,
7826 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7827 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7828 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7829 },
7830 {
7831 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@13",
7832 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 13)",
7833 .pme_code = 541,
7834 .pme_flags = 0x0,
7835 .pme_numasks = 0,
7836 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7837 .pme_ctr = 5,
7838 .pme_event = 1,
7839 .pme_chipno = 13,
7840 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7841 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7842 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7843 },
7844 {
7845 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@14",
7846 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 14)",
7847 .pme_code = 542,
7848 .pme_flags = 0x0,
7849 .pme_numasks = 0,
7850 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7851 .pme_ctr = 5,
7852 .pme_event = 1,
7853 .pme_chipno = 14,
7854 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7855 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7856 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7857 },
7858 {
7859 .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@15",
7860 .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 15)",
7861 .pme_code = 543,
7862 .pme_flags = 0x0,
7863 .pme_numasks = 0,
7864 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7865 .pme_ctr = 5,
7866 .pme_event = 1,
7867 .pme_chipno = 15,
7868 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7869 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7870 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7871 },
7872 /* M Counter 5 Event 2 */
7873 {
7874 .pme_name = "W_IN_FLOWING_1@0",
7875 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 0)",
7876 .pme_code = 544,
7877 .pme_flags = 0x0,
7878 .pme_numasks = 0,
7879 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7880 .pme_ctr = 5,
7881 .pme_event = 2,
7882 .pme_chipno = 0,
7883 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7884 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7885 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7886 },
7887 {
7888 .pme_name = "W_IN_FLOWING_1@1",
7889 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 1)",
7890 .pme_code = 545,
7891 .pme_flags = 0x0,
7892 .pme_numasks = 0,
7893 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7894 .pme_ctr = 5,
7895 .pme_event = 2,
7896 .pme_chipno = 1,
7897 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7898 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7899 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7900 },
7901 {
7902 .pme_name = "W_IN_FLOWING_1@2",
7903 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 2)",
7904 .pme_code = 546,
7905 .pme_flags = 0x0,
7906 .pme_numasks = 0,
7907 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7908 .pme_ctr = 5,
7909 .pme_event = 2,
7910 .pme_chipno = 2,
7911 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7912 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7913 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7914 },
7915 {
7916 .pme_name = "W_IN_FLOWING_1@3",
7917 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 3)",
7918 .pme_code = 547,
7919 .pme_flags = 0x0,
7920 .pme_numasks = 0,
7921 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7922 .pme_ctr = 5,
7923 .pme_event = 2,
7924 .pme_chipno = 3,
7925 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7926 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7927 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7928 },
7929 {
7930 .pme_name = "W_IN_FLOWING_1@4",
7931 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 4)",
7932 .pme_code = 548,
7933 .pme_flags = 0x0,
7934 .pme_numasks = 0,
7935 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7936 .pme_ctr = 5,
7937 .pme_event = 2,
7938 .pme_chipno = 4,
7939 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7940 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7941 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7942 },
7943 {
7944 .pme_name = "W_IN_FLOWING_1@5",
7945 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 5)",
7946 .pme_code = 549,
7947 .pme_flags = 0x0,
7948 .pme_numasks = 0,
7949 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7950 .pme_ctr = 5,
7951 .pme_event = 2,
7952 .pme_chipno = 5,
7953 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7954 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7955 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7956 },
7957 {
7958 .pme_name = "W_IN_FLOWING_1@6",
7959 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 6)",
7960 .pme_code = 550,
7961 .pme_flags = 0x0,
7962 .pme_numasks = 0,
7963 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7964 .pme_ctr = 5,
7965 .pme_event = 2,
7966 .pme_chipno = 6,
7967 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7968 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7969 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7970 },
7971 {
7972 .pme_name = "W_IN_FLOWING_1@7",
7973 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 7)",
7974 .pme_code = 551,
7975 .pme_flags = 0x0,
7976 .pme_numasks = 0,
7977 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7978 .pme_ctr = 5,
7979 .pme_event = 2,
7980 .pme_chipno = 7,
7981 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7982 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7983 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7984 },
7985 {
7986 .pme_name = "W_IN_FLOWING_1@8",
7987 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 8)",
7988 .pme_code = 552,
7989 .pme_flags = 0x0,
7990 .pme_numasks = 0,
7991 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
7992 .pme_ctr = 5,
7993 .pme_event = 2,
7994 .pme_chipno = 8,
7995 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
7996 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
7997 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
7998 },
7999 {
8000 .pme_name = "W_IN_FLOWING_1@9",
8001 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 9)",
8002 .pme_code = 553,
8003 .pme_flags = 0x0,
8004 .pme_numasks = 0,
8005 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8006 .pme_ctr = 5,
8007 .pme_event = 2,
8008 .pme_chipno = 9,
8009 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8010 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8011 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8012 },
8013 {
8014 .pme_name = "W_IN_FLOWING_1@10",
8015 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 10)",
8016 .pme_code = 554,
8017 .pme_flags = 0x0,
8018 .pme_numasks = 0,
8019 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8020 .pme_ctr = 5,
8021 .pme_event = 2,
8022 .pme_chipno = 10,
8023 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8024 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8025 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8026 },
8027 {
8028 .pme_name = "W_IN_FLOWING_1@11",
8029 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 11)",
8030 .pme_code = 555,
8031 .pme_flags = 0x0,
8032 .pme_numasks = 0,
8033 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8034 .pme_ctr = 5,
8035 .pme_event = 2,
8036 .pme_chipno = 11,
8037 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8038 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8039 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8040 },
8041 {
8042 .pme_name = "W_IN_FLOWING_1@12",
8043 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 12)",
8044 .pme_code = 556,
8045 .pme_flags = 0x0,
8046 .pme_numasks = 0,
8047 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8048 .pme_ctr = 5,
8049 .pme_event = 2,
8050 .pme_chipno = 12,
8051 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8052 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8053 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8054 },
8055 {
8056 .pme_name = "W_IN_FLOWING_1@13",
8057 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 13)",
8058 .pme_code = 557,
8059 .pme_flags = 0x0,
8060 .pme_numasks = 0,
8061 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8062 .pme_ctr = 5,
8063 .pme_event = 2,
8064 .pme_chipno = 13,
8065 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8066 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8067 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8068 },
8069 {
8070 .pme_name = "W_IN_FLOWING_1@14",
8071 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 14)",
8072 .pme_code = 558,
8073 .pme_flags = 0x0,
8074 .pme_numasks = 0,
8075 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8076 .pme_ctr = 5,
8077 .pme_event = 2,
8078 .pme_chipno = 14,
8079 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8080 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8081 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8082 },
8083 {
8084 .pme_name = "W_IN_FLOWING_1@15",
8085 .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 15)",
8086 .pme_code = 559,
8087 .pme_flags = 0x0,
8088 .pme_numasks = 0,
8089 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8090 .pme_ctr = 5,
8091 .pme_event = 2,
8092 .pme_chipno = 15,
8093 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8094 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8095 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8096 },
8097 /* M Counter 5 Event 3 */
8098 {
8099 .pme_name = "FWD_READ@0",
8100 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 0)",
8101 .pme_code = 560,
8102 .pme_flags = 0x0,
8103 .pme_numasks = 0,
8104 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8105 .pme_ctr = 5,
8106 .pme_event = 3,
8107 .pme_chipno = 0,
8108 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8109 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8110 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8111 },
8112 {
8113 .pme_name = "FWD_READ@1",
8114 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 1)",
8115 .pme_code = 561,
8116 .pme_flags = 0x0,
8117 .pme_numasks = 0,
8118 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8119 .pme_ctr = 5,
8120 .pme_event = 3,
8121 .pme_chipno = 1,
8122 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8123 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8124 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8125 },
8126 {
8127 .pme_name = "FWD_READ@2",
8128 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 2)",
8129 .pme_code = 562,
8130 .pme_flags = 0x0,
8131 .pme_numasks = 0,
8132 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8133 .pme_ctr = 5,
8134 .pme_event = 3,
8135 .pme_chipno = 2,
8136 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8137 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8138 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8139 },
8140 {
8141 .pme_name = "FWD_READ@3",
8142 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 3)",
8143 .pme_code = 563,
8144 .pme_flags = 0x0,
8145 .pme_numasks = 0,
8146 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8147 .pme_ctr = 5,
8148 .pme_event = 3,
8149 .pme_chipno = 3,
8150 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8151 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8152 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8153 },
8154 {
8155 .pme_name = "FWD_READ@4",
8156 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 4)",
8157 .pme_code = 564,
8158 .pme_flags = 0x0,
8159 .pme_numasks = 0,
8160 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8161 .pme_ctr = 5,
8162 .pme_event = 3,
8163 .pme_chipno = 4,
8164 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8165 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8166 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8167 },
8168 {
8169 .pme_name = "FWD_READ@5",
8170 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 5)",
8171 .pme_code = 565,
8172 .pme_flags = 0x0,
8173 .pme_numasks = 0,
8174 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8175 .pme_ctr = 5,
8176 .pme_event = 3,
8177 .pme_chipno = 5,
8178 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8179 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8180 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8181 },
8182 {
8183 .pme_name = "FWD_READ@6",
8184 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 6)",
8185 .pme_code = 566,
8186 .pme_flags = 0x0,
8187 .pme_numasks = 0,
8188 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8189 .pme_ctr = 5,
8190 .pme_event = 3,
8191 .pme_chipno = 6,
8192 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8193 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8194 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8195 },
8196 {
8197 .pme_name = "FWD_READ@7",
8198 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 7)",
8199 .pme_code = 567,
8200 .pme_flags = 0x0,
8201 .pme_numasks = 0,
8202 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8203 .pme_ctr = 5,
8204 .pme_event = 3,
8205 .pme_chipno = 7,
8206 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8207 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8208 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8209 },
8210 {
8211 .pme_name = "FWD_READ@8",
8212 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 8)",
8213 .pme_code = 568,
8214 .pme_flags = 0x0,
8215 .pme_numasks = 0,
8216 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8217 .pme_ctr = 5,
8218 .pme_event = 3,
8219 .pme_chipno = 8,
8220 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8221 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8222 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8223 },
8224 {
8225 .pme_name = "FWD_READ@9",
8226 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 9)",
8227 .pme_code = 569,
8228 .pme_flags = 0x0,
8229 .pme_numasks = 0,
8230 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8231 .pme_ctr = 5,
8232 .pme_event = 3,
8233 .pme_chipno = 9,
8234 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8235 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8236 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8237 },
8238 {
8239 .pme_name = "FWD_READ@10",
8240 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 10)",
8241 .pme_code = 570,
8242 .pme_flags = 0x0,
8243 .pme_numasks = 0,
8244 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8245 .pme_ctr = 5,
8246 .pme_event = 3,
8247 .pme_chipno = 10,
8248 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8249 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8250 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8251 },
8252 {
8253 .pme_name = "FWD_READ@11",
8254 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 11)",
8255 .pme_code = 571,
8256 .pme_flags = 0x0,
8257 .pme_numasks = 0,
8258 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8259 .pme_ctr = 5,
8260 .pme_event = 3,
8261 .pme_chipno = 11,
8262 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8263 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8264 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8265 },
8266 {
8267 .pme_name = "FWD_READ@12",
8268 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 12)",
8269 .pme_code = 572,
8270 .pme_flags = 0x0,
8271 .pme_numasks = 0,
8272 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8273 .pme_ctr = 5,
8274 .pme_event = 3,
8275 .pme_chipno = 12,
8276 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8277 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8278 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8279 },
8280 {
8281 .pme_name = "FWD_READ@13",
8282 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 13)",
8283 .pme_code = 573,
8284 .pme_flags = 0x0,
8285 .pme_numasks = 0,
8286 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8287 .pme_ctr = 5,
8288 .pme_event = 3,
8289 .pme_chipno = 13,
8290 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8291 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8292 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8293 },
8294 {
8295 .pme_name = "FWD_READ@14",
8296 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 14)",
8297 .pme_code = 574,
8298 .pme_flags = 0x0,
8299 .pme_numasks = 0,
8300 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8301 .pme_ctr = 5,
8302 .pme_event = 3,
8303 .pme_chipno = 14,
8304 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8305 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8306 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8307 },
8308 {
8309 .pme_name = "FWD_READ@15",
8310 .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 15)",
8311 .pme_code = 575,
8312 .pme_flags = 0x0,
8313 .pme_numasks = 0,
8314 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8315 .pme_ctr = 5,
8316 .pme_event = 3,
8317 .pme_chipno = 15,
8318 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8319 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8320 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8321 },
8322 /* M Counter 6 Event 0 */
8323 {
8324 .pme_name = "SUPPLY_INV@0",
8325 .pme_desc = "SupplyInv packets received. (M chip 0)",
8326 .pme_code = 576,
8327 .pme_flags = 0x0,
8328 .pme_numasks = 0,
8329 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8330 .pme_ctr = 6,
8331 .pme_event = 0,
8332 .pme_chipno = 0,
8333 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8334 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8335 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8336 },
8337 {
8338 .pme_name = "SUPPLY_INV@1",
8339 .pme_desc = "SupplyInv packets received. (M chip 1)",
8340 .pme_code = 577,
8341 .pme_flags = 0x0,
8342 .pme_numasks = 0,
8343 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8344 .pme_ctr = 6,
8345 .pme_event = 0,
8346 .pme_chipno = 1,
8347 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8348 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8349 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8350 },
8351 {
8352 .pme_name = "SUPPLY_INV@2",
8353 .pme_desc = "SupplyInv packets received. (M chip 2)",
8354 .pme_code = 578,
8355 .pme_flags = 0x0,
8356 .pme_numasks = 0,
8357 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8358 .pme_ctr = 6,
8359 .pme_event = 0,
8360 .pme_chipno = 2,
8361 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8362 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8363 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8364 },
8365 {
8366 .pme_name = "SUPPLY_INV@3",
8367 .pme_desc = "SupplyInv packets received. (M chip 3)",
8368 .pme_code = 579,
8369 .pme_flags = 0x0,
8370 .pme_numasks = 0,
8371 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8372 .pme_ctr = 6,
8373 .pme_event = 0,
8374 .pme_chipno = 3,
8375 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8376 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8377 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8378 },
8379 {
8380 .pme_name = "SUPPLY_INV@4",
8381 .pme_desc = "SupplyInv packets received. (M chip 4)",
8382 .pme_code = 580,
8383 .pme_flags = 0x0,
8384 .pme_numasks = 0,
8385 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8386 .pme_ctr = 6,
8387 .pme_event = 0,
8388 .pme_chipno = 4,
8389 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8390 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8391 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8392 },
8393 {
8394 .pme_name = "SUPPLY_INV@5",
8395 .pme_desc = "SupplyInv packets received. (M chip 5)",
8396 .pme_code = 581,
8397 .pme_flags = 0x0,
8398 .pme_numasks = 0,
8399 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8400 .pme_ctr = 6,
8401 .pme_event = 0,
8402 .pme_chipno = 5,
8403 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8404 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8405 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8406 },
8407 {
8408 .pme_name = "SUPPLY_INV@6",
8409 .pme_desc = "SupplyInv packets received. (M chip 6)",
8410 .pme_code = 582,
8411 .pme_flags = 0x0,
8412 .pme_numasks = 0,
8413 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8414 .pme_ctr = 6,
8415 .pme_event = 0,
8416 .pme_chipno = 6,
8417 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8418 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8419 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8420 },
8421 {
8422 .pme_name = "SUPPLY_INV@7",
8423 .pme_desc = "SupplyInv packets received. (M chip 7)",
8424 .pme_code = 583,
8425 .pme_flags = 0x0,
8426 .pme_numasks = 0,
8427 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8428 .pme_ctr = 6,
8429 .pme_event = 0,
8430 .pme_chipno = 7,
8431 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8432 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8433 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8434 },
8435 {
8436 .pme_name = "SUPPLY_INV@8",
8437 .pme_desc = "SupplyInv packets received. (M chip 8)",
8438 .pme_code = 584,
8439 .pme_flags = 0x0,
8440 .pme_numasks = 0,
8441 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8442 .pme_ctr = 6,
8443 .pme_event = 0,
8444 .pme_chipno = 8,
8445 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8446 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8447 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8448 },
8449 {
8450 .pme_name = "SUPPLY_INV@9",
8451 .pme_desc = "SupplyInv packets received. (M chip 9)",
8452 .pme_code = 585,
8453 .pme_flags = 0x0,
8454 .pme_numasks = 0,
8455 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8456 .pme_ctr = 6,
8457 .pme_event = 0,
8458 .pme_chipno = 9,
8459 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8460 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8461 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8462 },
8463 {
8464 .pme_name = "SUPPLY_INV@10",
8465 .pme_desc = "SupplyInv packets received. (M chip 10)",
8466 .pme_code = 586,
8467 .pme_flags = 0x0,
8468 .pme_numasks = 0,
8469 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8470 .pme_ctr = 6,
8471 .pme_event = 0,
8472 .pme_chipno = 10,
8473 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8474 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8475 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8476 },
8477 {
8478 .pme_name = "SUPPLY_INV@11",
8479 .pme_desc = "SupplyInv packets received. (M chip 11)",
8480 .pme_code = 587,
8481 .pme_flags = 0x0,
8482 .pme_numasks = 0,
8483 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8484 .pme_ctr = 6,
8485 .pme_event = 0,
8486 .pme_chipno = 11,
8487 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8488 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8489 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8490 },
8491 {
8492 .pme_name = "SUPPLY_INV@12",
8493 .pme_desc = "SupplyInv packets received. (M chip 12)",
8494 .pme_code = 588,
8495 .pme_flags = 0x0,
8496 .pme_numasks = 0,
8497 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8498 .pme_ctr = 6,
8499 .pme_event = 0,
8500 .pme_chipno = 12,
8501 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8502 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8503 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8504 },
8505 {
8506 .pme_name = "SUPPLY_INV@13",
8507 .pme_desc = "SupplyInv packets received. (M chip 13)",
8508 .pme_code = 589,
8509 .pme_flags = 0x0,
8510 .pme_numasks = 0,
8511 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8512 .pme_ctr = 6,
8513 .pme_event = 0,
8514 .pme_chipno = 13,
8515 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8516 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8517 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8518 },
8519 {
8520 .pme_name = "SUPPLY_INV@14",
8521 .pme_desc = "SupplyInv packets received. (M chip 14)",
8522 .pme_code = 590,
8523 .pme_flags = 0x0,
8524 .pme_numasks = 0,
8525 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8526 .pme_ctr = 6,
8527 .pme_event = 0,
8528 .pme_chipno = 14,
8529 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8530 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8531 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8532 },
8533 {
8534 .pme_name = "SUPPLY_INV@15",
8535 .pme_desc = "SupplyInv packets received. (M chip 15)",
8536 .pme_code = 591,
8537 .pme_flags = 0x0,
8538 .pme_numasks = 0,
8539 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8540 .pme_ctr = 6,
8541 .pme_event = 0,
8542 .pme_chipno = 15,
8543 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8544 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8545 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8546 },
8547 /* M Counter 6 Event 1 */
8548 {
8549 .pme_name = "NUM_REPLAY@0",
8550 .pme_desc = "Requests sent through replay queue. (M chip 0)",
8551 .pme_code = 592,
8552 .pme_flags = 0x0,
8553 .pme_numasks = 0,
8554 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8555 .pme_ctr = 6,
8556 .pme_event = 1,
8557 .pme_chipno = 0,
8558 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8559 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8560 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8561 },
8562 {
8563 .pme_name = "NUM_REPLAY@1",
8564 .pme_desc = "Requests sent through replay queue. (M chip 1)",
8565 .pme_code = 593,
8566 .pme_flags = 0x0,
8567 .pme_numasks = 0,
8568 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8569 .pme_ctr = 6,
8570 .pme_event = 1,
8571 .pme_chipno = 1,
8572 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8573 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8574 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8575 },
8576 {
8577 .pme_name = "NUM_REPLAY@2",
8578 .pme_desc = "Requests sent through replay queue. (M chip 2)",
8579 .pme_code = 594,
8580 .pme_flags = 0x0,
8581 .pme_numasks = 0,
8582 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8583 .pme_ctr = 6,
8584 .pme_event = 1,
8585 .pme_chipno = 2,
8586 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8587 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8588 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8589 },
8590 {
8591 .pme_name = "NUM_REPLAY@3",
8592 .pme_desc = "Requests sent through replay queue. (M chip 3)",
8593 .pme_code = 595,
8594 .pme_flags = 0x0,
8595 .pme_numasks = 0,
8596 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8597 .pme_ctr = 6,
8598 .pme_event = 1,
8599 .pme_chipno = 3,
8600 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8601 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8602 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8603 },
8604 {
8605 .pme_name = "NUM_REPLAY@4",
8606 .pme_desc = "Requests sent through replay queue. (M chip 4)",
8607 .pme_code = 596,
8608 .pme_flags = 0x0,
8609 .pme_numasks = 0,
8610 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8611 .pme_ctr = 6,
8612 .pme_event = 1,
8613 .pme_chipno = 4,
8614 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8615 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8616 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8617 },
8618 {
8619 .pme_name = "NUM_REPLAY@5",
8620 .pme_desc = "Requests sent through replay queue. (M chip 5)",
8621 .pme_code = 597,
8622 .pme_flags = 0x0,
8623 .pme_numasks = 0,
8624 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8625 .pme_ctr = 6,
8626 .pme_event = 1,
8627 .pme_chipno = 5,
8628 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8629 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8630 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8631 },
8632 {
8633 .pme_name = "NUM_REPLAY@6",
8634 .pme_desc = "Requests sent through replay queue. (M chip 6)",
8635 .pme_code = 598,
8636 .pme_flags = 0x0,
8637 .pme_numasks = 0,
8638 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8639 .pme_ctr = 6,
8640 .pme_event = 1,
8641 .pme_chipno = 6,
8642 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8643 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8644 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8645 },
8646 {
8647 .pme_name = "NUM_REPLAY@7",
8648 .pme_desc = "Requests sent through replay queue. (M chip 7)",
8649 .pme_code = 599,
8650 .pme_flags = 0x0,
8651 .pme_numasks = 0,
8652 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8653 .pme_ctr = 6,
8654 .pme_event = 1,
8655 .pme_chipno = 7,
8656 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8657 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8658 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8659 },
8660 {
8661 .pme_name = "NUM_REPLAY@8",
8662 .pme_desc = "Requests sent through replay queue. (M chip 8)",
8663 .pme_code = 600,
8664 .pme_flags = 0x0,
8665 .pme_numasks = 0,
8666 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8667 .pme_ctr = 6,
8668 .pme_event = 1,
8669 .pme_chipno = 8,
8670 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8671 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8672 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8673 },
8674 {
8675 .pme_name = "NUM_REPLAY@9",
8676 .pme_desc = "Requests sent through replay queue. (M chip 9)",
8677 .pme_code = 601,
8678 .pme_flags = 0x0,
8679 .pme_numasks = 0,
8680 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8681 .pme_ctr = 6,
8682 .pme_event = 1,
8683 .pme_chipno = 9,
8684 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8685 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8686 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8687 },
8688 {
8689 .pme_name = "NUM_REPLAY@10",
8690 .pme_desc = "Requests sent through replay queue. (M chip 10)",
8691 .pme_code = 602,
8692 .pme_flags = 0x0,
8693 .pme_numasks = 0,
8694 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8695 .pme_ctr = 6,
8696 .pme_event = 1,
8697 .pme_chipno = 10,
8698 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8699 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8700 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8701 },
8702 {
8703 .pme_name = "NUM_REPLAY@11",
8704 .pme_desc = "Requests sent through replay queue. (M chip 11)",
8705 .pme_code = 603,
8706 .pme_flags = 0x0,
8707 .pme_numasks = 0,
8708 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8709 .pme_ctr = 6,
8710 .pme_event = 1,
8711 .pme_chipno = 11,
8712 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8713 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8714 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8715 },
8716 {
8717 .pme_name = "NUM_REPLAY@12",
8718 .pme_desc = "Requests sent through replay queue. (M chip 12)",
8719 .pme_code = 604,
8720 .pme_flags = 0x0,
8721 .pme_numasks = 0,
8722 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8723 .pme_ctr = 6,
8724 .pme_event = 1,
8725 .pme_chipno = 12,
8726 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8727 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8728 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8729 },
8730 {
8731 .pme_name = "NUM_REPLAY@13",
8732 .pme_desc = "Requests sent through replay queue. (M chip 13)",
8733 .pme_code = 605,
8734 .pme_flags = 0x0,
8735 .pme_numasks = 0,
8736 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8737 .pme_ctr = 6,
8738 .pme_event = 1,
8739 .pme_chipno = 13,
8740 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8741 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8742 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8743 },
8744 {
8745 .pme_name = "NUM_REPLAY@14",
8746 .pme_desc = "Requests sent through replay queue. (M chip 14)",
8747 .pme_code = 606,
8748 .pme_flags = 0x0,
8749 .pme_numasks = 0,
8750 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8751 .pme_ctr = 6,
8752 .pme_event = 1,
8753 .pme_chipno = 14,
8754 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8755 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8756 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8757 },
8758 {
8759 .pme_name = "NUM_REPLAY@15",
8760 .pme_desc = "Requests sent through replay queue. (M chip 15)",
8761 .pme_code = 607,
8762 .pme_flags = 0x0,
8763 .pme_numasks = 0,
8764 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8765 .pme_ctr = 6,
8766 .pme_event = 1,
8767 .pme_chipno = 15,
8768 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8769 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8770 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8771 },
8772 /* M Counter 6 Event 2 */
8773 {
8774 .pme_name = "W_IN_FLOWING_2@0",
8775 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 0)",
8776 .pme_code = 608,
8777 .pme_flags = 0x0,
8778 .pme_numasks = 0,
8779 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8780 .pme_ctr = 6,
8781 .pme_event = 2,
8782 .pme_chipno = 0,
8783 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8784 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8785 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8786 },
8787 {
8788 .pme_name = "W_IN_FLOWING_2@1",
8789 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 1)",
8790 .pme_code = 609,
8791 .pme_flags = 0x0,
8792 .pme_numasks = 0,
8793 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8794 .pme_ctr = 6,
8795 .pme_event = 2,
8796 .pme_chipno = 1,
8797 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8798 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8799 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8800 },
8801 {
8802 .pme_name = "W_IN_FLOWING_2@2",
8803 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 2)",
8804 .pme_code = 610,
8805 .pme_flags = 0x0,
8806 .pme_numasks = 0,
8807 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8808 .pme_ctr = 6,
8809 .pme_event = 2,
8810 .pme_chipno = 2,
8811 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8812 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8813 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8814 },
8815 {
8816 .pme_name = "W_IN_FLOWING_2@3",
8817 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 3)",
8818 .pme_code = 611,
8819 .pme_flags = 0x0,
8820 .pme_numasks = 0,
8821 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8822 .pme_ctr = 6,
8823 .pme_event = 2,
8824 .pme_chipno = 3,
8825 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8826 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8827 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8828 },
8829 {
8830 .pme_name = "W_IN_FLOWING_2@4",
8831 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 4)",
8832 .pme_code = 612,
8833 .pme_flags = 0x0,
8834 .pme_numasks = 0,
8835 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8836 .pme_ctr = 6,
8837 .pme_event = 2,
8838 .pme_chipno = 4,
8839 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8840 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8841 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8842 },
8843 {
8844 .pme_name = "W_IN_FLOWING_2@5",
8845 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 5)",
8846 .pme_code = 613,
8847 .pme_flags = 0x0,
8848 .pme_numasks = 0,
8849 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8850 .pme_ctr = 6,
8851 .pme_event = 2,
8852 .pme_chipno = 5,
8853 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8854 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8855 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8856 },
8857 {
8858 .pme_name = "W_IN_FLOWING_2@6",
8859 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 6)",
8860 .pme_code = 614,
8861 .pme_flags = 0x0,
8862 .pme_numasks = 0,
8863 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8864 .pme_ctr = 6,
8865 .pme_event = 2,
8866 .pme_chipno = 6,
8867 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8868 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8869 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8870 },
8871 {
8872 .pme_name = "W_IN_FLOWING_2@7",
8873 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 7)",
8874 .pme_code = 615,
8875 .pme_flags = 0x0,
8876 .pme_numasks = 0,
8877 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8878 .pme_ctr = 6,
8879 .pme_event = 2,
8880 .pme_chipno = 7,
8881 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8882 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8883 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8884 },
8885 {
8886 .pme_name = "W_IN_FLOWING_2@8",
8887 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 8)",
8888 .pme_code = 616,
8889 .pme_flags = 0x0,
8890 .pme_numasks = 0,
8891 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8892 .pme_ctr = 6,
8893 .pme_event = 2,
8894 .pme_chipno = 8,
8895 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8896 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8897 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8898 },
8899 {
8900 .pme_name = "W_IN_FLOWING_2@9",
8901 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 9)",
8902 .pme_code = 617,
8903 .pme_flags = 0x0,
8904 .pme_numasks = 0,
8905 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8906 .pme_ctr = 6,
8907 .pme_event = 2,
8908 .pme_chipno = 9,
8909 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8910 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8911 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8912 },
8913 {
8914 .pme_name = "W_IN_FLOWING_2@10",
8915 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 10)",
8916 .pme_code = 618,
8917 .pme_flags = 0x0,
8918 .pme_numasks = 0,
8919 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8920 .pme_ctr = 6,
8921 .pme_event = 2,
8922 .pme_chipno = 10,
8923 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8924 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8925 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8926 },
8927 {
8928 .pme_name = "W_IN_FLOWING_2@11",
8929 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 11)",
8930 .pme_code = 619,
8931 .pme_flags = 0x0,
8932 .pme_numasks = 0,
8933 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8934 .pme_ctr = 6,
8935 .pme_event = 2,
8936 .pme_chipno = 11,
8937 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8938 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8939 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8940 },
8941 {
8942 .pme_name = "W_IN_FLOWING_2@12",
8943 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 12)",
8944 .pme_code = 620,
8945 .pme_flags = 0x0,
8946 .pme_numasks = 0,
8947 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8948 .pme_ctr = 6,
8949 .pme_event = 2,
8950 .pme_chipno = 12,
8951 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8952 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8953 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8954 },
8955 {
8956 .pme_name = "W_IN_FLOWING_2@13",
8957 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 13)",
8958 .pme_code = 621,
8959 .pme_flags = 0x0,
8960 .pme_numasks = 0,
8961 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8962 .pme_ctr = 6,
8963 .pme_event = 2,
8964 .pme_chipno = 13,
8965 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8966 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8967 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8968 },
8969 {
8970 .pme_name = "W_IN_FLOWING_2@14",
8971 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 14)",
8972 .pme_code = 622,
8973 .pme_flags = 0x0,
8974 .pme_numasks = 0,
8975 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8976 .pme_ctr = 6,
8977 .pme_event = 2,
8978 .pme_chipno = 14,
8979 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8980 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8981 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8982 },
8983 {
8984 .pme_name = "W_IN_FLOWING_2@15",
8985 .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 15)",
8986 .pme_code = 623,
8987 .pme_flags = 0x0,
8988 .pme_numasks = 0,
8989 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
8990 .pme_ctr = 6,
8991 .pme_event = 2,
8992 .pme_chipno = 15,
8993 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
8994 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
8995 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
8996 },
8997 /* M Counter 6 Event 3 */
8998 {
8999 .pme_name = "INVAL_1@0",
9000 .pme_desc = "Invalidations sent to a single BW. (M chip 0)",
9001 .pme_code = 624,
9002 .pme_flags = 0x0,
9003 .pme_numasks = 0,
9004 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9005 .pme_ctr = 6,
9006 .pme_event = 3,
9007 .pme_chipno = 0,
9008 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9009 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9010 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9011 },
9012 {
9013 .pme_name = "INVAL_1@1",
9014 .pme_desc = "Invalidations sent to a single BW. (M chip 1)",
9015 .pme_code = 625,
9016 .pme_flags = 0x0,
9017 .pme_numasks = 0,
9018 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9019 .pme_ctr = 6,
9020 .pme_event = 3,
9021 .pme_chipno = 1,
9022 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9023 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9024 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9025 },
9026 {
9027 .pme_name = "INVAL_1@2",
9028 .pme_desc = "Invalidations sent to a single BW. (M chip 2)",
9029 .pme_code = 626,
9030 .pme_flags = 0x0,
9031 .pme_numasks = 0,
9032 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9033 .pme_ctr = 6,
9034 .pme_event = 3,
9035 .pme_chipno = 2,
9036 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9037 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9038 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9039 },
9040 {
9041 .pme_name = "INVAL_1@3",
9042 .pme_desc = "Invalidations sent to a single BW. (M chip 3)",
9043 .pme_code = 627,
9044 .pme_flags = 0x0,
9045 .pme_numasks = 0,
9046 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9047 .pme_ctr = 6,
9048 .pme_event = 3,
9049 .pme_chipno = 3,
9050 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9051 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9052 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9053 },
9054 {
9055 .pme_name = "INVAL_1@4",
9056 .pme_desc = "Invalidations sent to a single BW. (M chip 4)",
9057 .pme_code = 628,
9058 .pme_flags = 0x0,
9059 .pme_numasks = 0,
9060 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9061 .pme_ctr = 6,
9062 .pme_event = 3,
9063 .pme_chipno = 4,
9064 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9065 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9066 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9067 },
9068 {
9069 .pme_name = "INVAL_1@5",
9070 .pme_desc = "Invalidations sent to a single BW. (M chip 5)",
9071 .pme_code = 629,
9072 .pme_flags = 0x0,
9073 .pme_numasks = 0,
9074 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9075 .pme_ctr = 6,
9076 .pme_event = 3,
9077 .pme_chipno = 5,
9078 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9079 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9080 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9081 },
9082 {
9083 .pme_name = "INVAL_1@6",
9084 .pme_desc = "Invalidations sent to a single BW. (M chip 6)",
9085 .pme_code = 630,
9086 .pme_flags = 0x0,
9087 .pme_numasks = 0,
9088 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9089 .pme_ctr = 6,
9090 .pme_event = 3,
9091 .pme_chipno = 6,
9092 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9093 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9094 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9095 },
9096 {
9097 .pme_name = "INVAL_1@7",
9098 .pme_desc = "Invalidations sent to a single BW. (M chip 7)",
9099 .pme_code = 631,
9100 .pme_flags = 0x0,
9101 .pme_numasks = 0,
9102 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9103 .pme_ctr = 6,
9104 .pme_event = 3,
9105 .pme_chipno = 7,
9106 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9107 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9108 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9109 },
9110 {
9111 .pme_name = "INVAL_1@8",
9112 .pme_desc = "Invalidations sent to a single BW. (M chip 8)",
9113 .pme_code = 632,
9114 .pme_flags = 0x0,
9115 .pme_numasks = 0,
9116 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9117 .pme_ctr = 6,
9118 .pme_event = 3,
9119 .pme_chipno = 8,
9120 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9121 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9122 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9123 },
9124 {
9125 .pme_name = "INVAL_1@9",
9126 .pme_desc = "Invalidations sent to a single BW. (M chip 9)",
9127 .pme_code = 633,
9128 .pme_flags = 0x0,
9129 .pme_numasks = 0,
9130 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9131 .pme_ctr = 6,
9132 .pme_event = 3,
9133 .pme_chipno = 9,
9134 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9135 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9136 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9137 },
9138 {
9139 .pme_name = "INVAL_1@10",
9140 .pme_desc = "Invalidations sent to a single BW. (M chip 10)",
9141 .pme_code = 634,
9142 .pme_flags = 0x0,
9143 .pme_numasks = 0,
9144 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9145 .pme_ctr = 6,
9146 .pme_event = 3,
9147 .pme_chipno = 10,
9148 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9149 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9150 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9151 },
9152 {
9153 .pme_name = "INVAL_1@11",
9154 .pme_desc = "Invalidations sent to a single BW. (M chip 11)",
9155 .pme_code = 635,
9156 .pme_flags = 0x0,
9157 .pme_numasks = 0,
9158 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9159 .pme_ctr = 6,
9160 .pme_event = 3,
9161 .pme_chipno = 11,
9162 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9163 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9164 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9165 },
9166 {
9167 .pme_name = "INVAL_1@12",
9168 .pme_desc = "Invalidations sent to a single BW. (M chip 12)",
9169 .pme_code = 636,
9170 .pme_flags = 0x0,
9171 .pme_numasks = 0,
9172 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9173 .pme_ctr = 6,
9174 .pme_event = 3,
9175 .pme_chipno = 12,
9176 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9177 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9178 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9179 },
9180 {
9181 .pme_name = "INVAL_1@13",
9182 .pme_desc = "Invalidations sent to a single BW. (M chip 13)",
9183 .pme_code = 637,
9184 .pme_flags = 0x0,
9185 .pme_numasks = 0,
9186 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9187 .pme_ctr = 6,
9188 .pme_event = 3,
9189 .pme_chipno = 13,
9190 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9191 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9192 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9193 },
9194 {
9195 .pme_name = "INVAL_1@14",
9196 .pme_desc = "Invalidations sent to a single BW. (M chip 14)",
9197 .pme_code = 638,
9198 .pme_flags = 0x0,
9199 .pme_numasks = 0,
9200 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9201 .pme_ctr = 6,
9202 .pme_event = 3,
9203 .pme_chipno = 14,
9204 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9205 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9206 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9207 },
9208 {
9209 .pme_name = "INVAL_1@15",
9210 .pme_desc = "Invalidations sent to a single BW. (M chip 15)",
9211 .pme_code = 639,
9212 .pme_flags = 0x0,
9213 .pme_numasks = 0,
9214 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9215 .pme_ctr = 6,
9216 .pme_event = 3,
9217 .pme_chipno = 15,
9218 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9219 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9220 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9221 },
9222 /* M Counter 7 Event 0 */
9223 {
9224 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@0",
9225 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 0)",
9226 .pme_code = 640,
9227 .pme_flags = 0x0,
9228 .pme_numasks = 0,
9229 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9230 .pme_ctr = 7,
9231 .pme_event = 0,
9232 .pme_chipno = 0,
9233 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9234 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9235 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9236 },
9237 {
9238 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@1",
9239 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 1)",
9240 .pme_code = 641,
9241 .pme_flags = 0x0,
9242 .pme_numasks = 0,
9243 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9244 .pme_ctr = 7,
9245 .pme_event = 0,
9246 .pme_chipno = 1,
9247 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9248 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9249 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9250 },
9251 {
9252 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@2",
9253 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 2)",
9254 .pme_code = 642,
9255 .pme_flags = 0x0,
9256 .pme_numasks = 0,
9257 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9258 .pme_ctr = 7,
9259 .pme_event = 0,
9260 .pme_chipno = 2,
9261 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9262 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9263 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9264 },
9265 {
9266 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@3",
9267 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 3)",
9268 .pme_code = 643,
9269 .pme_flags = 0x0,
9270 .pme_numasks = 0,
9271 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9272 .pme_ctr = 7,
9273 .pme_event = 0,
9274 .pme_chipno = 3,
9275 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9276 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9277 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9278 },
9279 {
9280 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@4",
9281 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 4)",
9282 .pme_code = 644,
9283 .pme_flags = 0x0,
9284 .pme_numasks = 0,
9285 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9286 .pme_ctr = 7,
9287 .pme_event = 0,
9288 .pme_chipno = 4,
9289 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9290 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9291 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9292 },
9293 {
9294 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@5",
9295 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 5)",
9296 .pme_code = 645,
9297 .pme_flags = 0x0,
9298 .pme_numasks = 0,
9299 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9300 .pme_ctr = 7,
9301 .pme_event = 0,
9302 .pme_chipno = 5,
9303 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9304 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9305 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9306 },
9307 {
9308 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@6",
9309 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 6)",
9310 .pme_code = 646,
9311 .pme_flags = 0x0,
9312 .pme_numasks = 0,
9313 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9314 .pme_ctr = 7,
9315 .pme_event = 0,
9316 .pme_chipno = 6,
9317 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9318 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9319 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9320 },
9321 {
9322 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@7",
9323 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 7)",
9324 .pme_code = 647,
9325 .pme_flags = 0x0,
9326 .pme_numasks = 0,
9327 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9328 .pme_ctr = 7,
9329 .pme_event = 0,
9330 .pme_chipno = 7,
9331 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9332 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9333 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9334 },
9335 {
9336 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@8",
9337 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 8)",
9338 .pme_code = 648,
9339 .pme_flags = 0x0,
9340 .pme_numasks = 0,
9341 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9342 .pme_ctr = 7,
9343 .pme_event = 0,
9344 .pme_chipno = 8,
9345 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9346 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9347 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9348 },
9349 {
9350 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@9",
9351 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 9)",
9352 .pme_code = 649,
9353 .pme_flags = 0x0,
9354 .pme_numasks = 0,
9355 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9356 .pme_ctr = 7,
9357 .pme_event = 0,
9358 .pme_chipno = 9,
9359 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9360 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9361 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9362 },
9363 {
9364 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@10",
9365 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 10)",
9366 .pme_code = 650,
9367 .pme_flags = 0x0,
9368 .pme_numasks = 0,
9369 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9370 .pme_ctr = 7,
9371 .pme_event = 0,
9372 .pme_chipno = 10,
9373 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9374 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9375 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9376 },
9377 {
9378 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@11",
9379 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 11)",
9380 .pme_code = 651,
9381 .pme_flags = 0x0,
9382 .pme_numasks = 0,
9383 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9384 .pme_ctr = 7,
9385 .pme_event = 0,
9386 .pme_chipno = 11,
9387 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9388 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9389 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9390 },
9391 {
9392 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@12",
9393 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 12)",
9394 .pme_code = 652,
9395 .pme_flags = 0x0,
9396 .pme_numasks = 0,
9397 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9398 .pme_ctr = 7,
9399 .pme_event = 0,
9400 .pme_chipno = 12,
9401 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9402 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9403 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9404 },
9405 {
9406 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@13",
9407 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 13)",
9408 .pme_code = 653,
9409 .pme_flags = 0x0,
9410 .pme_numasks = 0,
9411 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9412 .pme_ctr = 7,
9413 .pme_event = 0,
9414 .pme_chipno = 13,
9415 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9416 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9417 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9418 },
9419 {
9420 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@14",
9421 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 14)",
9422 .pme_code = 654,
9423 .pme_flags = 0x0,
9424 .pme_numasks = 0,
9425 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9426 .pme_ctr = 7,
9427 .pme_event = 0,
9428 .pme_chipno = 14,
9429 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9430 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9431 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9432 },
9433 {
9434 .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@15",
9435 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 15)",
9436 .pme_code = 655,
9437 .pme_flags = 0x0,
9438 .pme_numasks = 0,
9439 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9440 .pme_ctr = 7,
9441 .pme_event = 0,
9442 .pme_chipno = 15,
9443 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9444 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9445 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9446 },
9447 /* M Counter 7 Event 1 */
9448 {
9449 .pme_name = "<M:7:1>@0",
9450 .pme_desc = "<NA>",
9451 .pme_code = 656,
9452 .pme_flags = 0x0,
9453 .pme_numasks = 0,
9454 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9455 .pme_ctr = 7,
9456 .pme_event = 1,
9457 .pme_chipno = 0,
9458 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9459 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9460 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9461 },
9462 {
9463 .pme_name = "<M:7:1>@1",
9464 .pme_desc = "<NA>",
9465 .pme_code = 657,
9466 .pme_flags = 0x0,
9467 .pme_numasks = 0,
9468 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9469 .pme_ctr = 7,
9470 .pme_event = 1,
9471 .pme_chipno = 1,
9472 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9473 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9474 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9475 },
9476 {
9477 .pme_name = "<M:7:1>@2",
9478 .pme_desc = "<NA>",
9479 .pme_code = 658,
9480 .pme_flags = 0x0,
9481 .pme_numasks = 0,
9482 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9483 .pme_ctr = 7,
9484 .pme_event = 1,
9485 .pme_chipno = 2,
9486 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9487 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9488 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9489 },
9490 {
9491 .pme_name = "<M:7:1>@3",
9492 .pme_desc = "<NA>",
9493 .pme_code = 659,
9494 .pme_flags = 0x0,
9495 .pme_numasks = 0,
9496 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9497 .pme_ctr = 7,
9498 .pme_event = 1,
9499 .pme_chipno = 3,
9500 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9501 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9502 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9503 },
9504 {
9505 .pme_name = "<M:7:1>@4",
9506 .pme_desc = "<NA>",
9507 .pme_code = 660,
9508 .pme_flags = 0x0,
9509 .pme_numasks = 0,
9510 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9511 .pme_ctr = 7,
9512 .pme_event = 1,
9513 .pme_chipno = 4,
9514 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9515 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9516 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9517 },
9518 {
9519 .pme_name = "<M:7:1>@5",
9520 .pme_desc = "<NA>",
9521 .pme_code = 661,
9522 .pme_flags = 0x0,
9523 .pme_numasks = 0,
9524 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9525 .pme_ctr = 7,
9526 .pme_event = 1,
9527 .pme_chipno = 5,
9528 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9529 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9530 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9531 },
9532 {
9533 .pme_name = "<M:7:1>@6",
9534 .pme_desc = "<NA>",
9535 .pme_code = 662,
9536 .pme_flags = 0x0,
9537 .pme_numasks = 0,
9538 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9539 .pme_ctr = 7,
9540 .pme_event = 1,
9541 .pme_chipno = 6,
9542 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9543 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9544 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9545 },
9546 {
9547 .pme_name = "<M:7:1>@7",
9548 .pme_desc = "<NA>",
9549 .pme_code = 663,
9550 .pme_flags = 0x0,
9551 .pme_numasks = 0,
9552 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9553 .pme_ctr = 7,
9554 .pme_event = 1,
9555 .pme_chipno = 7,
9556 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9557 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9558 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9559 },
9560 {
9561 .pme_name = "<M:7:1>@8",
9562 .pme_desc = "<NA>",
9563 .pme_code = 664,
9564 .pme_flags = 0x0,
9565 .pme_numasks = 0,
9566 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9567 .pme_ctr = 7,
9568 .pme_event = 1,
9569 .pme_chipno = 8,
9570 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9571 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9572 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9573 },
9574 {
9575 .pme_name = "<M:7:1>@9",
9576 .pme_desc = "<NA>",
9577 .pme_code = 665,
9578 .pme_flags = 0x0,
9579 .pme_numasks = 0,
9580 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9581 .pme_ctr = 7,
9582 .pme_event = 1,
9583 .pme_chipno = 9,
9584 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9585 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9586 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9587 },
9588 {
9589 .pme_name = "<M:7:1>@10",
9590 .pme_desc = "<NA>",
9591 .pme_code = 666,
9592 .pme_flags = 0x0,
9593 .pme_numasks = 0,
9594 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9595 .pme_ctr = 7,
9596 .pme_event = 1,
9597 .pme_chipno = 10,
9598 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9599 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9600 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9601 },
9602 {
9603 .pme_name = "<M:7:1>@11",
9604 .pme_desc = "<NA>",
9605 .pme_code = 667,
9606 .pme_flags = 0x0,
9607 .pme_numasks = 0,
9608 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9609 .pme_ctr = 7,
9610 .pme_event = 1,
9611 .pme_chipno = 11,
9612 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9613 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9614 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9615 },
9616 {
9617 .pme_name = "<M:7:1>@12",
9618 .pme_desc = "<NA>",
9619 .pme_code = 668,
9620 .pme_flags = 0x0,
9621 .pme_numasks = 0,
9622 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9623 .pme_ctr = 7,
9624 .pme_event = 1,
9625 .pme_chipno = 12,
9626 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9627 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9628 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9629 },
9630 {
9631 .pme_name = "<M:7:1>@13",
9632 .pme_desc = "<NA>",
9633 .pme_code = 669,
9634 .pme_flags = 0x0,
9635 .pme_numasks = 0,
9636 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9637 .pme_ctr = 7,
9638 .pme_event = 1,
9639 .pme_chipno = 13,
9640 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9641 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9642 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9643 },
9644 {
9645 .pme_name = "<M:7:1>@14",
9646 .pme_desc = "<NA>",
9647 .pme_code = 670,
9648 .pme_flags = 0x0,
9649 .pme_numasks = 0,
9650 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9651 .pme_ctr = 7,
9652 .pme_event = 1,
9653 .pme_chipno = 14,
9654 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9655 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9656 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9657 },
9658 {
9659 .pme_name = "<M:7:1>@15",
9660 .pme_desc = "<NA>",
9661 .pme_code = 671,
9662 .pme_flags = 0x0,
9663 .pme_numasks = 0,
9664 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9665 .pme_ctr = 7,
9666 .pme_event = 1,
9667 .pme_chipno = 15,
9668 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9669 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9670 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9671 },
9672 /* M Counter 7 Event 2 */
9673 {
9674 .pme_name = "W_IN_FLOWING_3@0",
9675 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 0)",
9676 .pme_code = 672,
9677 .pme_flags = 0x0,
9678 .pme_numasks = 0,
9679 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9680 .pme_ctr = 7,
9681 .pme_event = 2,
9682 .pme_chipno = 0,
9683 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9684 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9685 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9686 },
9687 {
9688 .pme_name = "W_IN_FLOWING_3@1",
9689 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 1)",
9690 .pme_code = 673,
9691 .pme_flags = 0x0,
9692 .pme_numasks = 0,
9693 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9694 .pme_ctr = 7,
9695 .pme_event = 2,
9696 .pme_chipno = 1,
9697 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9698 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9699 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9700 },
9701 {
9702 .pme_name = "W_IN_FLOWING_3@2",
9703 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 2)",
9704 .pme_code = 674,
9705 .pme_flags = 0x0,
9706 .pme_numasks = 0,
9707 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9708 .pme_ctr = 7,
9709 .pme_event = 2,
9710 .pme_chipno = 2,
9711 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9712 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9713 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9714 },
9715 {
9716 .pme_name = "W_IN_FLOWING_3@3",
9717 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 3)",
9718 .pme_code = 675,
9719 .pme_flags = 0x0,
9720 .pme_numasks = 0,
9721 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9722 .pme_ctr = 7,
9723 .pme_event = 2,
9724 .pme_chipno = 3,
9725 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9726 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9727 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9728 },
9729 {
9730 .pme_name = "W_IN_FLOWING_3@4",
9731 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 4)",
9732 .pme_code = 676,
9733 .pme_flags = 0x0,
9734 .pme_numasks = 0,
9735 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9736 .pme_ctr = 7,
9737 .pme_event = 2,
9738 .pme_chipno = 4,
9739 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9740 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9741 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9742 },
9743 {
9744 .pme_name = "W_IN_FLOWING_3@5",
9745 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 5)",
9746 .pme_code = 677,
9747 .pme_flags = 0x0,
9748 .pme_numasks = 0,
9749 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9750 .pme_ctr = 7,
9751 .pme_event = 2,
9752 .pme_chipno = 5,
9753 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9754 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9755 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9756 },
9757 {
9758 .pme_name = "W_IN_FLOWING_3@6",
9759 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 6)",
9760 .pme_code = 678,
9761 .pme_flags = 0x0,
9762 .pme_numasks = 0,
9763 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9764 .pme_ctr = 7,
9765 .pme_event = 2,
9766 .pme_chipno = 6,
9767 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9768 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9769 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9770 },
9771 {
9772 .pme_name = "W_IN_FLOWING_3@7",
9773 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 7)",
9774 .pme_code = 679,
9775 .pme_flags = 0x0,
9776 .pme_numasks = 0,
9777 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9778 .pme_ctr = 7,
9779 .pme_event = 2,
9780 .pme_chipno = 7,
9781 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9782 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9783 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9784 },
9785 {
9786 .pme_name = "W_IN_FLOWING_3@8",
9787 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 8)",
9788 .pme_code = 680,
9789 .pme_flags = 0x0,
9790 .pme_numasks = 0,
9791 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9792 .pme_ctr = 7,
9793 .pme_event = 2,
9794 .pme_chipno = 8,
9795 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9796 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9797 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9798 },
9799 {
9800 .pme_name = "W_IN_FLOWING_3@9",
9801 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 9)",
9802 .pme_code = 681,
9803 .pme_flags = 0x0,
9804 .pme_numasks = 0,
9805 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9806 .pme_ctr = 7,
9807 .pme_event = 2,
9808 .pme_chipno = 9,
9809 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9810 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9811 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9812 },
9813 {
9814 .pme_name = "W_IN_FLOWING_3@10",
9815 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 10)",
9816 .pme_code = 682,
9817 .pme_flags = 0x0,
9818 .pme_numasks = 0,
9819 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9820 .pme_ctr = 7,
9821 .pme_event = 2,
9822 .pme_chipno = 10,
9823 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9824 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9825 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9826 },
9827 {
9828 .pme_name = "W_IN_FLOWING_3@11",
9829 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 11)",
9830 .pme_code = 683,
9831 .pme_flags = 0x0,
9832 .pme_numasks = 0,
9833 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9834 .pme_ctr = 7,
9835 .pme_event = 2,
9836 .pme_chipno = 11,
9837 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9838 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9839 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9840 },
9841 {
9842 .pme_name = "W_IN_FLOWING_3@12",
9843 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 12)",
9844 .pme_code = 684,
9845 .pme_flags = 0x0,
9846 .pme_numasks = 0,
9847 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9848 .pme_ctr = 7,
9849 .pme_event = 2,
9850 .pme_chipno = 12,
9851 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9852 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9853 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9854 },
9855 {
9856 .pme_name = "W_IN_FLOWING_3@13",
9857 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 13)",
9858 .pme_code = 685,
9859 .pme_flags = 0x0,
9860 .pme_numasks = 0,
9861 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9862 .pme_ctr = 7,
9863 .pme_event = 2,
9864 .pme_chipno = 13,
9865 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9866 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9867 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9868 },
9869 {
9870 .pme_name = "W_IN_FLOWING_3@14",
9871 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 14)",
9872 .pme_code = 686,
9873 .pme_flags = 0x0,
9874 .pme_numasks = 0,
9875 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9876 .pme_ctr = 7,
9877 .pme_event = 2,
9878 .pme_chipno = 14,
9879 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9880 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9881 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9882 },
9883 {
9884 .pme_name = "W_IN_FLOWING_3@15",
9885 .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 15)",
9886 .pme_code = 687,
9887 .pme_flags = 0x0,
9888 .pme_numasks = 0,
9889 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9890 .pme_ctr = 7,
9891 .pme_event = 2,
9892 .pme_chipno = 15,
9893 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9894 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9895 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9896 },
9897 /* M Counter 7 Event 3 */
9898 {
9899 .pme_name = "INVAL_2@0",
9900 .pme_desc = "Invalidations sent to two BWs. (M chip 0)",
9901 .pme_code = 688,
9902 .pme_flags = 0x0,
9903 .pme_numasks = 0,
9904 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9905 .pme_ctr = 7,
9906 .pme_event = 3,
9907 .pme_chipno = 0,
9908 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9909 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9910 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9911 },
9912 {
9913 .pme_name = "INVAL_2@1",
9914 .pme_desc = "Invalidations sent to two BWs. (M chip 1)",
9915 .pme_code = 689,
9916 .pme_flags = 0x0,
9917 .pme_numasks = 0,
9918 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9919 .pme_ctr = 7,
9920 .pme_event = 3,
9921 .pme_chipno = 1,
9922 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9923 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9924 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9925 },
9926 {
9927 .pme_name = "INVAL_2@2",
9928 .pme_desc = "Invalidations sent to two BWs. (M chip 2)",
9929 .pme_code = 690,
9930 .pme_flags = 0x0,
9931 .pme_numasks = 0,
9932 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9933 .pme_ctr = 7,
9934 .pme_event = 3,
9935 .pme_chipno = 2,
9936 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9937 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9938 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9939 },
9940 {
9941 .pme_name = "INVAL_2@3",
9942 .pme_desc = "Invalidations sent to two BWs. (M chip 3)",
9943 .pme_code = 691,
9944 .pme_flags = 0x0,
9945 .pme_numasks = 0,
9946 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9947 .pme_ctr = 7,
9948 .pme_event = 3,
9949 .pme_chipno = 3,
9950 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9951 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9952 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9953 },
9954 {
9955 .pme_name = "INVAL_2@4",
9956 .pme_desc = "Invalidations sent to two BWs. (M chip 4)",
9957 .pme_code = 692,
9958 .pme_flags = 0x0,
9959 .pme_numasks = 0,
9960 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9961 .pme_ctr = 7,
9962 .pme_event = 3,
9963 .pme_chipno = 4,
9964 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9965 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9966 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9967 },
9968 {
9969 .pme_name = "INVAL_2@5",
9970 .pme_desc = "Invalidations sent to two BWs. (M chip 5)",
9971 .pme_code = 693,
9972 .pme_flags = 0x0,
9973 .pme_numasks = 0,
9974 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9975 .pme_ctr = 7,
9976 .pme_event = 3,
9977 .pme_chipno = 5,
9978 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9979 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9980 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9981 },
9982 {
9983 .pme_name = "INVAL_2@6",
9984 .pme_desc = "Invalidations sent to two BWs. (M chip 6)",
9985 .pme_code = 694,
9986 .pme_flags = 0x0,
9987 .pme_numasks = 0,
9988 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
9989 .pme_ctr = 7,
9990 .pme_event = 3,
9991 .pme_chipno = 6,
9992 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
9993 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
9994 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
9995 },
9996 {
9997 .pme_name = "INVAL_2@7",
9998 .pme_desc = "Invalidations sent to two BWs. (M chip 7)",
9999 .pme_code = 695,
10000 .pme_flags = 0x0,
10001 .pme_numasks = 0,
10002 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10003 .pme_ctr = 7,
10004 .pme_event = 3,
10005 .pme_chipno = 7,
10006 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10007 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10008 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10009 },
10010 {
10011 .pme_name = "INVAL_2@8",
10012 .pme_desc = "Invalidations sent to two BWs. (M chip 8)",
10013 .pme_code = 696,
10014 .pme_flags = 0x0,
10015 .pme_numasks = 0,
10016 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10017 .pme_ctr = 7,
10018 .pme_event = 3,
10019 .pme_chipno = 8,
10020 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10021 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10022 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10023 },
10024 {
10025 .pme_name = "INVAL_2@9",
10026 .pme_desc = "Invalidations sent to two BWs. (M chip 9)",
10027 .pme_code = 697,
10028 .pme_flags = 0x0,
10029 .pme_numasks = 0,
10030 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10031 .pme_ctr = 7,
10032 .pme_event = 3,
10033 .pme_chipno = 9,
10034 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10035 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10036 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10037 },
10038 {
10039 .pme_name = "INVAL_2@10",
10040 .pme_desc = "Invalidations sent to two BWs. (M chip 10)",
10041 .pme_code = 698,
10042 .pme_flags = 0x0,
10043 .pme_numasks = 0,
10044 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10045 .pme_ctr = 7,
10046 .pme_event = 3,
10047 .pme_chipno = 10,
10048 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10049 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10050 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10051 },
10052 {
10053 .pme_name = "INVAL_2@11",
10054 .pme_desc = "Invalidations sent to two BWs. (M chip 11)",
10055 .pme_code = 699,
10056 .pme_flags = 0x0,
10057 .pme_numasks = 0,
10058 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10059 .pme_ctr = 7,
10060 .pme_event = 3,
10061 .pme_chipno = 11,
10062 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10063 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10064 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10065 },
10066 {
10067 .pme_name = "INVAL_2@12",
10068 .pme_desc = "Invalidations sent to two BWs. (M chip 12)",
10069 .pme_code = 700,
10070 .pme_flags = 0x0,
10071 .pme_numasks = 0,
10072 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10073 .pme_ctr = 7,
10074 .pme_event = 3,
10075 .pme_chipno = 12,
10076 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10077 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10078 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10079 },
10080 {
10081 .pme_name = "INVAL_2@13",
10082 .pme_desc = "Invalidations sent to two BWs. (M chip 13)",
10083 .pme_code = 701,
10084 .pme_flags = 0x0,
10085 .pme_numasks = 0,
10086 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10087 .pme_ctr = 7,
10088 .pme_event = 3,
10089 .pme_chipno = 13,
10090 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10091 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10092 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10093 },
10094 {
10095 .pme_name = "INVAL_2@14",
10096 .pme_desc = "Invalidations sent to two BWs. (M chip 14)",
10097 .pme_code = 702,
10098 .pme_flags = 0x0,
10099 .pme_numasks = 0,
10100 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10101 .pme_ctr = 7,
10102 .pme_event = 3,
10103 .pme_chipno = 14,
10104 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10105 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10106 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10107 },
10108 {
10109 .pme_name = "INVAL_2@15",
10110 .pme_desc = "Invalidations sent to two BWs. (M chip 15)",
10111 .pme_code = 703,
10112 .pme_flags = 0x0,
10113 .pme_numasks = 0,
10114 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10115 .pme_ctr = 7,
10116 .pme_event = 3,
10117 .pme_chipno = 15,
10118 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10119 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10120 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10121 },
10122 /* M Counter 8 Event 0 */
10123 {
10124 .pme_name = "SUPPLY_SH@0",
10125 .pme_desc = "SupplySh packets received. (M chip 0)",
10126 .pme_code = 704,
10127 .pme_flags = 0x0,
10128 .pme_numasks = 0,
10129 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10130 .pme_ctr = 8,
10131 .pme_event = 0,
10132 .pme_chipno = 0,
10133 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10134 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10135 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10136 },
10137 {
10138 .pme_name = "SUPPLY_SH@1",
10139 .pme_desc = "SupplySh packets received. (M chip 1)",
10140 .pme_code = 705,
10141 .pme_flags = 0x0,
10142 .pme_numasks = 0,
10143 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10144 .pme_ctr = 8,
10145 .pme_event = 0,
10146 .pme_chipno = 1,
10147 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10148 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10149 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10150 },
10151 {
10152 .pme_name = "SUPPLY_SH@2",
10153 .pme_desc = "SupplySh packets received. (M chip 2)",
10154 .pme_code = 706,
10155 .pme_flags = 0x0,
10156 .pme_numasks = 0,
10157 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10158 .pme_ctr = 8,
10159 .pme_event = 0,
10160 .pme_chipno = 2,
10161 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10162 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10163 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10164 },
10165 {
10166 .pme_name = "SUPPLY_SH@3",
10167 .pme_desc = "SupplySh packets received. (M chip 3)",
10168 .pme_code = 707,
10169 .pme_flags = 0x0,
10170 .pme_numasks = 0,
10171 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10172 .pme_ctr = 8,
10173 .pme_event = 0,
10174 .pme_chipno = 3,
10175 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10176 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10177 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10178 },
10179 {
10180 .pme_name = "SUPPLY_SH@4",
10181 .pme_desc = "SupplySh packets received. (M chip 4)",
10182 .pme_code = 708,
10183 .pme_flags = 0x0,
10184 .pme_numasks = 0,
10185 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10186 .pme_ctr = 8,
10187 .pme_event = 0,
10188 .pme_chipno = 4,
10189 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10190 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10191 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10192 },
10193 {
10194 .pme_name = "SUPPLY_SH@5",
10195 .pme_desc = "SupplySh packets received. (M chip 5)",
10196 .pme_code = 709,
10197 .pme_flags = 0x0,
10198 .pme_numasks = 0,
10199 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10200 .pme_ctr = 8,
10201 .pme_event = 0,
10202 .pme_chipno = 5,
10203 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10204 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10205 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10206 },
10207 {
10208 .pme_name = "SUPPLY_SH@6",
10209 .pme_desc = "SupplySh packets received. (M chip 6)",
10210 .pme_code = 710,
10211 .pme_flags = 0x0,
10212 .pme_numasks = 0,
10213 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10214 .pme_ctr = 8,
10215 .pme_event = 0,
10216 .pme_chipno = 6,
10217 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10218 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10219 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10220 },
10221 {
10222 .pme_name = "SUPPLY_SH@7",
10223 .pme_desc = "SupplySh packets received. (M chip 7)",
10224 .pme_code = 711,
10225 .pme_flags = 0x0,
10226 .pme_numasks = 0,
10227 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10228 .pme_ctr = 8,
10229 .pme_event = 0,
10230 .pme_chipno = 7,
10231 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10232 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10233 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10234 },
10235 {
10236 .pme_name = "SUPPLY_SH@8",
10237 .pme_desc = "SupplySh packets received. (M chip 8)",
10238 .pme_code = 712,
10239 .pme_flags = 0x0,
10240 .pme_numasks = 0,
10241 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10242 .pme_ctr = 8,
10243 .pme_event = 0,
10244 .pme_chipno = 8,
10245 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10246 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10247 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10248 },
10249 {
10250 .pme_name = "SUPPLY_SH@9",
10251 .pme_desc = "SupplySh packets received. (M chip 9)",
10252 .pme_code = 713,
10253 .pme_flags = 0x0,
10254 .pme_numasks = 0,
10255 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10256 .pme_ctr = 8,
10257 .pme_event = 0,
10258 .pme_chipno = 9,
10259 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10260 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10261 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10262 },
10263 {
10264 .pme_name = "SUPPLY_SH@10",
10265 .pme_desc = "SupplySh packets received. (M chip 10)",
10266 .pme_code = 714,
10267 .pme_flags = 0x0,
10268 .pme_numasks = 0,
10269 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10270 .pme_ctr = 8,
10271 .pme_event = 0,
10272 .pme_chipno = 10,
10273 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10274 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10275 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10276 },
10277 {
10278 .pme_name = "SUPPLY_SH@11",
10279 .pme_desc = "SupplySh packets received. (M chip 11)",
10280 .pme_code = 715,
10281 .pme_flags = 0x0,
10282 .pme_numasks = 0,
10283 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10284 .pme_ctr = 8,
10285 .pme_event = 0,
10286 .pme_chipno = 11,
10287 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10288 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10289 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10290 },
10291 {
10292 .pme_name = "SUPPLY_SH@12",
10293 .pme_desc = "SupplySh packets received. (M chip 12)",
10294 .pme_code = 716,
10295 .pme_flags = 0x0,
10296 .pme_numasks = 0,
10297 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10298 .pme_ctr = 8,
10299 .pme_event = 0,
10300 .pme_chipno = 12,
10301 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10302 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10303 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10304 },
10305 {
10306 .pme_name = "SUPPLY_SH@13",
10307 .pme_desc = "SupplySh packets received. (M chip 13)",
10308 .pme_code = 717,
10309 .pme_flags = 0x0,
10310 .pme_numasks = 0,
10311 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10312 .pme_ctr = 8,
10313 .pme_event = 0,
10314 .pme_chipno = 13,
10315 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10316 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10317 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10318 },
10319 {
10320 .pme_name = "SUPPLY_SH@14",
10321 .pme_desc = "SupplySh packets received. (M chip 14)",
10322 .pme_code = 718,
10323 .pme_flags = 0x0,
10324 .pme_numasks = 0,
10325 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10326 .pme_ctr = 8,
10327 .pme_event = 0,
10328 .pme_chipno = 14,
10329 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10330 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10331 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10332 },
10333 {
10334 .pme_name = "SUPPLY_SH@15",
10335 .pme_desc = "SupplySh packets received. (M chip 15)",
10336 .pme_code = 719,
10337 .pme_flags = 0x0,
10338 .pme_numasks = 0,
10339 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10340 .pme_ctr = 8,
10341 .pme_event = 0,
10342 .pme_chipno = 15,
10343 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10344 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10345 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10346 },
10347 /* M Counter 8 Event 1 */
10348 {
10349 .pme_name = "STALL_MM@0",
10350 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 0)",
10351 .pme_code = 720,
10352 .pme_flags = 0x0,
10353 .pme_numasks = 0,
10354 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10355 .pme_ctr = 8,
10356 .pme_event = 1,
10357 .pme_chipno = 0,
10358 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10359 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10360 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10361 },
10362 {
10363 .pme_name = "STALL_MM@1",
10364 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 1)",
10365 .pme_code = 721,
10366 .pme_flags = 0x0,
10367 .pme_numasks = 0,
10368 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10369 .pme_ctr = 8,
10370 .pme_event = 1,
10371 .pme_chipno = 1,
10372 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10373 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10374 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10375 },
10376 {
10377 .pme_name = "STALL_MM@2",
10378 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 2)",
10379 .pme_code = 722,
10380 .pme_flags = 0x0,
10381 .pme_numasks = 0,
10382 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10383 .pme_ctr = 8,
10384 .pme_event = 1,
10385 .pme_chipno = 2,
10386 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10387 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10388 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10389 },
10390 {
10391 .pme_name = "STALL_MM@3",
10392 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 3)",
10393 .pme_code = 723,
10394 .pme_flags = 0x0,
10395 .pme_numasks = 0,
10396 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10397 .pme_ctr = 8,
10398 .pme_event = 1,
10399 .pme_chipno = 3,
10400 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10401 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10402 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10403 },
10404 {
10405 .pme_name = "STALL_MM@4",
10406 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 4)",
10407 .pme_code = 724,
10408 .pme_flags = 0x0,
10409 .pme_numasks = 0,
10410 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10411 .pme_ctr = 8,
10412 .pme_event = 1,
10413 .pme_chipno = 4,
10414 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10415 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10416 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10417 },
10418 {
10419 .pme_name = "STALL_MM@5",
10420 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 5)",
10421 .pme_code = 725,
10422 .pme_flags = 0x0,
10423 .pme_numasks = 0,
10424 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10425 .pme_ctr = 8,
10426 .pme_event = 1,
10427 .pme_chipno = 5,
10428 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10429 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10430 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10431 },
10432 {
10433 .pme_name = "STALL_MM@6",
10434 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 6)",
10435 .pme_code = 726,
10436 .pme_flags = 0x0,
10437 .pme_numasks = 0,
10438 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10439 .pme_ctr = 8,
10440 .pme_event = 1,
10441 .pme_chipno = 6,
10442 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10443 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10444 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10445 },
10446 {
10447 .pme_name = "STALL_MM@7",
10448 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 7)",
10449 .pme_code = 727,
10450 .pme_flags = 0x0,
10451 .pme_numasks = 0,
10452 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10453 .pme_ctr = 8,
10454 .pme_event = 1,
10455 .pme_chipno = 7,
10456 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10457 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10458 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10459 },
10460 {
10461 .pme_name = "STALL_MM@8",
10462 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 8)",
10463 .pme_code = 728,
10464 .pme_flags = 0x0,
10465 .pme_numasks = 0,
10466 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10467 .pme_ctr = 8,
10468 .pme_event = 1,
10469 .pme_chipno = 8,
10470 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10471 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10472 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10473 },
10474 {
10475 .pme_name = "STALL_MM@9",
10476 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 9)",
10477 .pme_code = 729,
10478 .pme_flags = 0x0,
10479 .pme_numasks = 0,
10480 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10481 .pme_ctr = 8,
10482 .pme_event = 1,
10483 .pme_chipno = 9,
10484 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10485 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10486 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10487 },
10488 {
10489 .pme_name = "STALL_MM@10",
10490 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 10)",
10491 .pme_code = 730,
10492 .pme_flags = 0x0,
10493 .pme_numasks = 0,
10494 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10495 .pme_ctr = 8,
10496 .pme_event = 1,
10497 .pme_chipno = 10,
10498 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10499 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10500 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10501 },
10502 {
10503 .pme_name = "STALL_MM@11",
10504 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 11)",
10505 .pme_code = 731,
10506 .pme_flags = 0x0,
10507 .pme_numasks = 0,
10508 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10509 .pme_ctr = 8,
10510 .pme_event = 1,
10511 .pme_chipno = 11,
10512 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10513 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10514 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10515 },
10516 {
10517 .pme_name = "STALL_MM@12",
10518 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 12)",
10519 .pme_code = 732,
10520 .pme_flags = 0x0,
10521 .pme_numasks = 0,
10522 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10523 .pme_ctr = 8,
10524 .pme_event = 1,
10525 .pme_chipno = 12,
10526 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10527 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10528 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10529 },
10530 {
10531 .pme_name = "STALL_MM@13",
10532 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 13)",
10533 .pme_code = 733,
10534 .pme_flags = 0x0,
10535 .pme_numasks = 0,
10536 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10537 .pme_ctr = 8,
10538 .pme_event = 1,
10539 .pme_chipno = 13,
10540 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10541 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10542 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10543 },
10544 {
10545 .pme_name = "STALL_MM@14",
10546 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 14)",
10547 .pme_code = 734,
10548 .pme_flags = 0x0,
10549 .pme_numasks = 0,
10550 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10551 .pme_ctr = 8,
10552 .pme_event = 1,
10553 .pme_chipno = 14,
10554 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10555 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10556 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10557 },
10558 {
10559 .pme_name = "STALL_MM@15",
10560 .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 15)",
10561 .pme_code = 735,
10562 .pme_flags = 0x0,
10563 .pme_numasks = 0,
10564 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10565 .pme_ctr = 8,
10566 .pme_event = 1,
10567 .pme_chipno = 15,
10568 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10569 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10570 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10571 },
10572 /* M Counter 8 Event 2 */
10573 {
10574 .pme_name = "W_IN_WAITING_0@0",
10575 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)",
10576 .pme_code = 736,
10577 .pme_flags = 0x0,
10578 .pme_numasks = 0,
10579 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10580 .pme_ctr = 8,
10581 .pme_event = 2,
10582 .pme_chipno = 0,
10583 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10584 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10585 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10586 },
10587 {
10588 .pme_name = "W_IN_WAITING_0@1",
10589 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)",
10590 .pme_code = 737,
10591 .pme_flags = 0x0,
10592 .pme_numasks = 0,
10593 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10594 .pme_ctr = 8,
10595 .pme_event = 2,
10596 .pme_chipno = 1,
10597 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10598 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10599 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10600 },
10601 {
10602 .pme_name = "W_IN_WAITING_0@2",
10603 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)",
10604 .pme_code = 738,
10605 .pme_flags = 0x0,
10606 .pme_numasks = 0,
10607 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10608 .pme_ctr = 8,
10609 .pme_event = 2,
10610 .pme_chipno = 2,
10611 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10612 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10613 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10614 },
10615 {
10616 .pme_name = "W_IN_WAITING_0@3",
10617 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)",
10618 .pme_code = 739,
10619 .pme_flags = 0x0,
10620 .pme_numasks = 0,
10621 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10622 .pme_ctr = 8,
10623 .pme_event = 2,
10624 .pme_chipno = 3,
10625 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10626 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10627 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10628 },
10629 {
10630 .pme_name = "W_IN_WAITING_0@4",
10631 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)",
10632 .pme_code = 740,
10633 .pme_flags = 0x0,
10634 .pme_numasks = 0,
10635 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10636 .pme_ctr = 8,
10637 .pme_event = 2,
10638 .pme_chipno = 4,
10639 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10640 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10641 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10642 },
10643 {
10644 .pme_name = "W_IN_WAITING_0@5",
10645 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)",
10646 .pme_code = 741,
10647 .pme_flags = 0x0,
10648 .pme_numasks = 0,
10649 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10650 .pme_ctr = 8,
10651 .pme_event = 2,
10652 .pme_chipno = 5,
10653 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10654 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10655 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10656 },
10657 {
10658 .pme_name = "W_IN_WAITING_0@6",
10659 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)",
10660 .pme_code = 742,
10661 .pme_flags = 0x0,
10662 .pme_numasks = 0,
10663 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10664 .pme_ctr = 8,
10665 .pme_event = 2,
10666 .pme_chipno = 6,
10667 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10668 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10669 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10670 },
10671 {
10672 .pme_name = "W_IN_WAITING_0@7",
10673 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)",
10674 .pme_code = 743,
10675 .pme_flags = 0x0,
10676 .pme_numasks = 0,
10677 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10678 .pme_ctr = 8,
10679 .pme_event = 2,
10680 .pme_chipno = 7,
10681 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10682 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10683 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10684 },
10685 {
10686 .pme_name = "W_IN_WAITING_0@8",
10687 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)",
10688 .pme_code = 744,
10689 .pme_flags = 0x0,
10690 .pme_numasks = 0,
10691 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10692 .pme_ctr = 8,
10693 .pme_event = 2,
10694 .pme_chipno = 8,
10695 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10696 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10697 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10698 },
10699 {
10700 .pme_name = "W_IN_WAITING_0@9",
10701 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)",
10702 .pme_code = 745,
10703 .pme_flags = 0x0,
10704 .pme_numasks = 0,
10705 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10706 .pme_ctr = 8,
10707 .pme_event = 2,
10708 .pme_chipno = 9,
10709 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10710 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10711 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10712 },
10713 {
10714 .pme_name = "W_IN_WAITING_0@10",
10715 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)",
10716 .pme_code = 746,
10717 .pme_flags = 0x0,
10718 .pme_numasks = 0,
10719 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10720 .pme_ctr = 8,
10721 .pme_event = 2,
10722 .pme_chipno = 10,
10723 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10724 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10725 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10726 },
10727 {
10728 .pme_name = "W_IN_WAITING_0@11",
10729 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)",
10730 .pme_code = 747,
10731 .pme_flags = 0x0,
10732 .pme_numasks = 0,
10733 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10734 .pme_ctr = 8,
10735 .pme_event = 2,
10736 .pme_chipno = 11,
10737 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10738 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10739 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10740 },
10741 {
10742 .pme_name = "W_IN_WAITING_0@12",
10743 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)",
10744 .pme_code = 748,
10745 .pme_flags = 0x0,
10746 .pme_numasks = 0,
10747 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10748 .pme_ctr = 8,
10749 .pme_event = 2,
10750 .pme_chipno = 12,
10751 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10752 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10753 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10754 },
10755 {
10756 .pme_name = "W_IN_WAITING_0@13",
10757 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)",
10758 .pme_code = 749,
10759 .pme_flags = 0x0,
10760 .pme_numasks = 0,
10761 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10762 .pme_ctr = 8,
10763 .pme_event = 2,
10764 .pme_chipno = 13,
10765 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10766 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10767 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10768 },
10769 {
10770 .pme_name = "W_IN_WAITING_0@14",
10771 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)",
10772 .pme_code = 750,
10773 .pme_flags = 0x0,
10774 .pme_numasks = 0,
10775 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10776 .pme_ctr = 8,
10777 .pme_event = 2,
10778 .pme_chipno = 14,
10779 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10780 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10781 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10782 },
10783 {
10784 .pme_name = "W_IN_WAITING_0@15",
10785 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)",
10786 .pme_code = 751,
10787 .pme_flags = 0x0,
10788 .pme_numasks = 0,
10789 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10790 .pme_ctr = 8,
10791 .pme_event = 2,
10792 .pme_chipno = 15,
10793 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10794 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10795 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10796 },
10797 /* M Counter 8 Event 3 */
10798 {
10799 .pme_name = "W_OUT_FLOWING_1@0",
10800 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 0)",
10801 .pme_code = 752,
10802 .pme_flags = 0x0,
10803 .pme_numasks = 0,
10804 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10805 .pme_ctr = 8,
10806 .pme_event = 3,
10807 .pme_chipno = 0,
10808 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10809 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10810 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10811 },
10812 {
10813 .pme_name = "W_OUT_FLOWING_1@1",
10814 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 1)",
10815 .pme_code = 753,
10816 .pme_flags = 0x0,
10817 .pme_numasks = 0,
10818 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10819 .pme_ctr = 8,
10820 .pme_event = 3,
10821 .pme_chipno = 1,
10822 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10823 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10824 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10825 },
10826 {
10827 .pme_name = "W_OUT_FLOWING_1@2",
10828 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 2)",
10829 .pme_code = 754,
10830 .pme_flags = 0x0,
10831 .pme_numasks = 0,
10832 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10833 .pme_ctr = 8,
10834 .pme_event = 3,
10835 .pme_chipno = 2,
10836 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10837 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10838 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10839 },
10840 {
10841 .pme_name = "W_OUT_FLOWING_1@3",
10842 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 3)",
10843 .pme_code = 755,
10844 .pme_flags = 0x0,
10845 .pme_numasks = 0,
10846 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10847 .pme_ctr = 8,
10848 .pme_event = 3,
10849 .pme_chipno = 3,
10850 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10851 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10852 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10853 },
10854 {
10855 .pme_name = "W_OUT_FLOWING_1@4",
10856 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 4)",
10857 .pme_code = 756,
10858 .pme_flags = 0x0,
10859 .pme_numasks = 0,
10860 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10861 .pme_ctr = 8,
10862 .pme_event = 3,
10863 .pme_chipno = 4,
10864 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10865 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10866 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10867 },
10868 {
10869 .pme_name = "W_OUT_FLOWING_1@5",
10870 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 5)",
10871 .pme_code = 757,
10872 .pme_flags = 0x0,
10873 .pme_numasks = 0,
10874 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10875 .pme_ctr = 8,
10876 .pme_event = 3,
10877 .pme_chipno = 5,
10878 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10879 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10880 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10881 },
10882 {
10883 .pme_name = "W_OUT_FLOWING_1@6",
10884 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 6)",
10885 .pme_code = 758,
10886 .pme_flags = 0x0,
10887 .pme_numasks = 0,
10888 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10889 .pme_ctr = 8,
10890 .pme_event = 3,
10891 .pme_chipno = 6,
10892 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10893 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10894 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10895 },
10896 {
10897 .pme_name = "W_OUT_FLOWING_1@7",
10898 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 7)",
10899 .pme_code = 759,
10900 .pme_flags = 0x0,
10901 .pme_numasks = 0,
10902 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10903 .pme_ctr = 8,
10904 .pme_event = 3,
10905 .pme_chipno = 7,
10906 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10907 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10908 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10909 },
10910 {
10911 .pme_name = "W_OUT_FLOWING_1@8",
10912 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 8)",
10913 .pme_code = 760,
10914 .pme_flags = 0x0,
10915 .pme_numasks = 0,
10916 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10917 .pme_ctr = 8,
10918 .pme_event = 3,
10919 .pme_chipno = 8,
10920 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10921 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10922 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10923 },
10924 {
10925 .pme_name = "W_OUT_FLOWING_1@9",
10926 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 9)",
10927 .pme_code = 761,
10928 .pme_flags = 0x0,
10929 .pme_numasks = 0,
10930 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10931 .pme_ctr = 8,
10932 .pme_event = 3,
10933 .pme_chipno = 9,
10934 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10935 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10936 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10937 },
10938 {
10939 .pme_name = "W_OUT_FLOWING_1@10",
10940 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 10)",
10941 .pme_code = 762,
10942 .pme_flags = 0x0,
10943 .pme_numasks = 0,
10944 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10945 .pme_ctr = 8,
10946 .pme_event = 3,
10947 .pme_chipno = 10,
10948 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10949 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10950 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10951 },
10952 {
10953 .pme_name = "W_OUT_FLOWING_1@11",
10954 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 11)",
10955 .pme_code = 763,
10956 .pme_flags = 0x0,
10957 .pme_numasks = 0,
10958 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10959 .pme_ctr = 8,
10960 .pme_event = 3,
10961 .pme_chipno = 11,
10962 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10963 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10964 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10965 },
10966 {
10967 .pme_name = "W_OUT_FLOWING_1@12",
10968 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 12)",
10969 .pme_code = 764,
10970 .pme_flags = 0x0,
10971 .pme_numasks = 0,
10972 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10973 .pme_ctr = 8,
10974 .pme_event = 3,
10975 .pme_chipno = 12,
10976 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10977 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10978 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10979 },
10980 {
10981 .pme_name = "W_OUT_FLOWING_1@13",
10982 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 13)",
10983 .pme_code = 765,
10984 .pme_flags = 0x0,
10985 .pme_numasks = 0,
10986 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
10987 .pme_ctr = 8,
10988 .pme_event = 3,
10989 .pme_chipno = 13,
10990 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
10991 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
10992 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
10993 },
10994 {
10995 .pme_name = "W_OUT_FLOWING_1@14",
10996 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 14)",
10997 .pme_code = 766,
10998 .pme_flags = 0x0,
10999 .pme_numasks = 0,
11000 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11001 .pme_ctr = 8,
11002 .pme_event = 3,
11003 .pme_chipno = 14,
11004 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11005 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11006 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11007 },
11008 {
11009 .pme_name = "W_OUT_FLOWING_1@15",
11010 .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 15)",
11011 .pme_code = 767,
11012 .pme_flags = 0x0,
11013 .pme_numasks = 0,
11014 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11015 .pme_ctr = 8,
11016 .pme_event = 3,
11017 .pme_chipno = 15,
11018 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11019 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11020 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11021 },
11022 /* M Counter 9 Event 0 */
11023 {
11024 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@0",
11025 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 0)",
11026 .pme_code = 768,
11027 .pme_flags = 0x0,
11028 .pme_numasks = 0,
11029 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11030 .pme_ctr = 9,
11031 .pme_event = 0,
11032 .pme_chipno = 0,
11033 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11034 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11035 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11036 },
11037 {
11038 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@1",
11039 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 1)",
11040 .pme_code = 769,
11041 .pme_flags = 0x0,
11042 .pme_numasks = 0,
11043 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11044 .pme_ctr = 9,
11045 .pme_event = 0,
11046 .pme_chipno = 1,
11047 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11048 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11049 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11050 },
11051 {
11052 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@2",
11053 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 2)",
11054 .pme_code = 770,
11055 .pme_flags = 0x0,
11056 .pme_numasks = 0,
11057 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11058 .pme_ctr = 9,
11059 .pme_event = 0,
11060 .pme_chipno = 2,
11061 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11062 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11063 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11064 },
11065 {
11066 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@3",
11067 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 3)",
11068 .pme_code = 771,
11069 .pme_flags = 0x0,
11070 .pme_numasks = 0,
11071 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11072 .pme_ctr = 9,
11073 .pme_event = 0,
11074 .pme_chipno = 3,
11075 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11076 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11077 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11078 },
11079 {
11080 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@4",
11081 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 4)",
11082 .pme_code = 772,
11083 .pme_flags = 0x0,
11084 .pme_numasks = 0,
11085 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11086 .pme_ctr = 9,
11087 .pme_event = 0,
11088 .pme_chipno = 4,
11089 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11090 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11091 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11092 },
11093 {
11094 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@5",
11095 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 5)",
11096 .pme_code = 773,
11097 .pme_flags = 0x0,
11098 .pme_numasks = 0,
11099 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11100 .pme_ctr = 9,
11101 .pme_event = 0,
11102 .pme_chipno = 5,
11103 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11104 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11105 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11106 },
11107 {
11108 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@6",
11109 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 6)",
11110 .pme_code = 774,
11111 .pme_flags = 0x0,
11112 .pme_numasks = 0,
11113 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11114 .pme_ctr = 9,
11115 .pme_event = 0,
11116 .pme_chipno = 6,
11117 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11118 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11119 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11120 },
11121 {
11122 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@7",
11123 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 7)",
11124 .pme_code = 775,
11125 .pme_flags = 0x0,
11126 .pme_numasks = 0,
11127 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11128 .pme_ctr = 9,
11129 .pme_event = 0,
11130 .pme_chipno = 7,
11131 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11132 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11133 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11134 },
11135 {
11136 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@8",
11137 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 8)",
11138 .pme_code = 776,
11139 .pme_flags = 0x0,
11140 .pme_numasks = 0,
11141 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11142 .pme_ctr = 9,
11143 .pme_event = 0,
11144 .pme_chipno = 8,
11145 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11146 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11147 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11148 },
11149 {
11150 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@9",
11151 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 9)",
11152 .pme_code = 777,
11153 .pme_flags = 0x0,
11154 .pme_numasks = 0,
11155 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11156 .pme_ctr = 9,
11157 .pme_event = 0,
11158 .pme_chipno = 9,
11159 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11160 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11161 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11162 },
11163 {
11164 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@10",
11165 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 10)",
11166 .pme_code = 778,
11167 .pme_flags = 0x0,
11168 .pme_numasks = 0,
11169 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11170 .pme_ctr = 9,
11171 .pme_event = 0,
11172 .pme_chipno = 10,
11173 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11174 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11175 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11176 },
11177 {
11178 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@11",
11179 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 11)",
11180 .pme_code = 779,
11181 .pme_flags = 0x0,
11182 .pme_numasks = 0,
11183 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11184 .pme_ctr = 9,
11185 .pme_event = 0,
11186 .pme_chipno = 11,
11187 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11188 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11189 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11190 },
11191 {
11192 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@12",
11193 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 12)",
11194 .pme_code = 780,
11195 .pme_flags = 0x0,
11196 .pme_numasks = 0,
11197 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11198 .pme_ctr = 9,
11199 .pme_event = 0,
11200 .pme_chipno = 12,
11201 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11202 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11203 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11204 },
11205 {
11206 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@13",
11207 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 13)",
11208 .pme_code = 781,
11209 .pme_flags = 0x0,
11210 .pme_numasks = 0,
11211 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11212 .pme_ctr = 9,
11213 .pme_event = 0,
11214 .pme_chipno = 13,
11215 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11216 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11217 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11218 },
11219 {
11220 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@14",
11221 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 14)",
11222 .pme_code = 782,
11223 .pme_flags = 0x0,
11224 .pme_numasks = 0,
11225 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11226 .pme_ctr = 9,
11227 .pme_event = 0,
11228 .pme_chipno = 14,
11229 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11230 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11231 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11232 },
11233 {
11234 .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@15",
11235 .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 15)",
11236 .pme_code = 783,
11237 .pme_flags = 0x0,
11238 .pme_numasks = 0,
11239 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11240 .pme_ctr = 9,
11241 .pme_event = 0,
11242 .pme_chipno = 15,
11243 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11244 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11245 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11246 },
11247 /* M Counter 9 Event 1 */
11248 {
11249 .pme_name = "SECTION_BUSY@0",
11250 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 0)",
11251 .pme_code = 784,
11252 .pme_flags = 0x0,
11253 .pme_numasks = 0,
11254 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11255 .pme_ctr = 9,
11256 .pme_event = 1,
11257 .pme_chipno = 0,
11258 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11259 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11260 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11261 },
11262 {
11263 .pme_name = "SECTION_BUSY@1",
11264 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 1)",
11265 .pme_code = 785,
11266 .pme_flags = 0x0,
11267 .pme_numasks = 0,
11268 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11269 .pme_ctr = 9,
11270 .pme_event = 1,
11271 .pme_chipno = 1,
11272 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11273 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11274 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11275 },
11276 {
11277 .pme_name = "SECTION_BUSY@2",
11278 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 2)",
11279 .pme_code = 786,
11280 .pme_flags = 0x0,
11281 .pme_numasks = 0,
11282 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11283 .pme_ctr = 9,
11284 .pme_event = 1,
11285 .pme_chipno = 2,
11286 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11287 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11288 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11289 },
11290 {
11291 .pme_name = "SECTION_BUSY@3",
11292 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 3)",
11293 .pme_code = 787,
11294 .pme_flags = 0x0,
11295 .pme_numasks = 0,
11296 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11297 .pme_ctr = 9,
11298 .pme_event = 1,
11299 .pme_chipno = 3,
11300 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11301 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11302 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11303 },
11304 {
11305 .pme_name = "SECTION_BUSY@4",
11306 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 4)",
11307 .pme_code = 788,
11308 .pme_flags = 0x0,
11309 .pme_numasks = 0,
11310 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11311 .pme_ctr = 9,
11312 .pme_event = 1,
11313 .pme_chipno = 4,
11314 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11315 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11316 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11317 },
11318 {
11319 .pme_name = "SECTION_BUSY@5",
11320 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 5)",
11321 .pme_code = 789,
11322 .pme_flags = 0x0,
11323 .pme_numasks = 0,
11324 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11325 .pme_ctr = 9,
11326 .pme_event = 1,
11327 .pme_chipno = 5,
11328 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11329 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11330 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11331 },
11332 {
11333 .pme_name = "SECTION_BUSY@6",
11334 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 6)",
11335 .pme_code = 790,
11336 .pme_flags = 0x0,
11337 .pme_numasks = 0,
11338 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11339 .pme_ctr = 9,
11340 .pme_event = 1,
11341 .pme_chipno = 6,
11342 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11343 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11344 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11345 },
11346 {
11347 .pme_name = "SECTION_BUSY@7",
11348 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 7)",
11349 .pme_code = 791,
11350 .pme_flags = 0x0,
11351 .pme_numasks = 0,
11352 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11353 .pme_ctr = 9,
11354 .pme_event = 1,
11355 .pme_chipno = 7,
11356 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11357 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11358 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11359 },
11360 {
11361 .pme_name = "SECTION_BUSY@8",
11362 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 8)",
11363 .pme_code = 792,
11364 .pme_flags = 0x0,
11365 .pme_numasks = 0,
11366 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11367 .pme_ctr = 9,
11368 .pme_event = 1,
11369 .pme_chipno = 8,
11370 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11371 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11372 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11373 },
11374 {
11375 .pme_name = "SECTION_BUSY@9",
11376 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 9)",
11377 .pme_code = 793,
11378 .pme_flags = 0x0,
11379 .pme_numasks = 0,
11380 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11381 .pme_ctr = 9,
11382 .pme_event = 1,
11383 .pme_chipno = 9,
11384 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11385 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11386 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11387 },
11388 {
11389 .pme_name = "SECTION_BUSY@10",
11390 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 10)",
11391 .pme_code = 794,
11392 .pme_flags = 0x0,
11393 .pme_numasks = 0,
11394 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11395 .pme_ctr = 9,
11396 .pme_event = 1,
11397 .pme_chipno = 10,
11398 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11399 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11400 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11401 },
11402 {
11403 .pme_name = "SECTION_BUSY@11",
11404 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 11)",
11405 .pme_code = 795,
11406 .pme_flags = 0x0,
11407 .pme_numasks = 0,
11408 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11409 .pme_ctr = 9,
11410 .pme_event = 1,
11411 .pme_chipno = 11,
11412 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11413 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11414 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11415 },
11416 {
11417 .pme_name = "SECTION_BUSY@12",
11418 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 12)",
11419 .pme_code = 796,
11420 .pme_flags = 0x0,
11421 .pme_numasks = 0,
11422 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11423 .pme_ctr = 9,
11424 .pme_event = 1,
11425 .pme_chipno = 12,
11426 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11427 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11428 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11429 },
11430 {
11431 .pme_name = "SECTION_BUSY@13",
11432 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 13)",
11433 .pme_code = 797,
11434 .pme_flags = 0x0,
11435 .pme_numasks = 0,
11436 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11437 .pme_ctr = 9,
11438 .pme_event = 1,
11439 .pme_chipno = 13,
11440 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11441 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11442 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11443 },
11444 {
11445 .pme_name = "SECTION_BUSY@14",
11446 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 14)",
11447 .pme_code = 798,
11448 .pme_flags = 0x0,
11449 .pme_numasks = 0,
11450 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11451 .pme_ctr = 9,
11452 .pme_event = 1,
11453 .pme_chipno = 14,
11454 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11455 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11456 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11457 },
11458 {
11459 .pme_name = "SECTION_BUSY@15",
11460 .pme_desc = "Wclk cycles MD pipeline busy. (M chip 15)",
11461 .pme_code = 799,
11462 .pme_flags = 0x0,
11463 .pme_numasks = 0,
11464 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11465 .pme_ctr = 9,
11466 .pme_event = 1,
11467 .pme_chipno = 15,
11468 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11469 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11470 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11471 },
11472 /* M Counter 9 Event 2 */
11473 {
11474 .pme_name = "W_IN_WAITING_1@0",
11475 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)",
11476 .pme_code = 800,
11477 .pme_flags = 0x0,
11478 .pme_numasks = 0,
11479 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11480 .pme_ctr = 9,
11481 .pme_event = 2,
11482 .pme_chipno = 0,
11483 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11484 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11485 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11486 },
11487 {
11488 .pme_name = "W_IN_WAITING_1@1",
11489 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)",
11490 .pme_code = 801,
11491 .pme_flags = 0x0,
11492 .pme_numasks = 0,
11493 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11494 .pme_ctr = 9,
11495 .pme_event = 2,
11496 .pme_chipno = 1,
11497 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11498 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11499 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11500 },
11501 {
11502 .pme_name = "W_IN_WAITING_1@2",
11503 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)",
11504 .pme_code = 802,
11505 .pme_flags = 0x0,
11506 .pme_numasks = 0,
11507 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11508 .pme_ctr = 9,
11509 .pme_event = 2,
11510 .pme_chipno = 2,
11511 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11512 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11513 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11514 },
11515 {
11516 .pme_name = "W_IN_WAITING_1@3",
11517 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)",
11518 .pme_code = 803,
11519 .pme_flags = 0x0,
11520 .pme_numasks = 0,
11521 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11522 .pme_ctr = 9,
11523 .pme_event = 2,
11524 .pme_chipno = 3,
11525 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11526 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11527 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11528 },
11529 {
11530 .pme_name = "W_IN_WAITING_1@4",
11531 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)",
11532 .pme_code = 804,
11533 .pme_flags = 0x0,
11534 .pme_numasks = 0,
11535 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11536 .pme_ctr = 9,
11537 .pme_event = 2,
11538 .pme_chipno = 4,
11539 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11540 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11541 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11542 },
11543 {
11544 .pme_name = "W_IN_WAITING_1@5",
11545 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)",
11546 .pme_code = 805,
11547 .pme_flags = 0x0,
11548 .pme_numasks = 0,
11549 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11550 .pme_ctr = 9,
11551 .pme_event = 2,
11552 .pme_chipno = 5,
11553 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11554 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11555 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11556 },
11557 {
11558 .pme_name = "W_IN_WAITING_1@6",
11559 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)",
11560 .pme_code = 806,
11561 .pme_flags = 0x0,
11562 .pme_numasks = 0,
11563 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11564 .pme_ctr = 9,
11565 .pme_event = 2,
11566 .pme_chipno = 6,
11567 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11568 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11569 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11570 },
11571 {
11572 .pme_name = "W_IN_WAITING_1@7",
11573 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)",
11574 .pme_code = 807,
11575 .pme_flags = 0x0,
11576 .pme_numasks = 0,
11577 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11578 .pme_ctr = 9,
11579 .pme_event = 2,
11580 .pme_chipno = 7,
11581 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11582 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11583 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11584 },
11585 {
11586 .pme_name = "W_IN_WAITING_1@8",
11587 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)",
11588 .pme_code = 808,
11589 .pme_flags = 0x0,
11590 .pme_numasks = 0,
11591 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11592 .pme_ctr = 9,
11593 .pme_event = 2,
11594 .pme_chipno = 8,
11595 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11596 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11597 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11598 },
11599 {
11600 .pme_name = "W_IN_WAITING_1@9",
11601 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)",
11602 .pme_code = 809,
11603 .pme_flags = 0x0,
11604 .pme_numasks = 0,
11605 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11606 .pme_ctr = 9,
11607 .pme_event = 2,
11608 .pme_chipno = 9,
11609 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11610 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11611 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11612 },
11613 {
11614 .pme_name = "W_IN_WAITING_1@10",
11615 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)",
11616 .pme_code = 810,
11617 .pme_flags = 0x0,
11618 .pme_numasks = 0,
11619 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11620 .pme_ctr = 9,
11621 .pme_event = 2,
11622 .pme_chipno = 10,
11623 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11624 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11625 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11626 },
11627 {
11628 .pme_name = "W_IN_WAITING_1@11",
11629 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)",
11630 .pme_code = 811,
11631 .pme_flags = 0x0,
11632 .pme_numasks = 0,
11633 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11634 .pme_ctr = 9,
11635 .pme_event = 2,
11636 .pme_chipno = 11,
11637 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11638 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11639 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11640 },
11641 {
11642 .pme_name = "W_IN_WAITING_1@12",
11643 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)",
11644 .pme_code = 812,
11645 .pme_flags = 0x0,
11646 .pme_numasks = 0,
11647 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11648 .pme_ctr = 9,
11649 .pme_event = 2,
11650 .pme_chipno = 12,
11651 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11652 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11653 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11654 },
11655 {
11656 .pme_name = "W_IN_WAITING_1@13",
11657 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)",
11658 .pme_code = 813,
11659 .pme_flags = 0x0,
11660 .pme_numasks = 0,
11661 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11662 .pme_ctr = 9,
11663 .pme_event = 2,
11664 .pme_chipno = 13,
11665 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11666 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11667 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11668 },
11669 {
11670 .pme_name = "W_IN_WAITING_1@14",
11671 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)",
11672 .pme_code = 814,
11673 .pme_flags = 0x0,
11674 .pme_numasks = 0,
11675 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11676 .pme_ctr = 9,
11677 .pme_event = 2,
11678 .pme_chipno = 14,
11679 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11680 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11681 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11682 },
11683 {
11684 .pme_name = "W_IN_WAITING_1@15",
11685 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)",
11686 .pme_code = 815,
11687 .pme_flags = 0x0,
11688 .pme_numasks = 0,
11689 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11690 .pme_ctr = 9,
11691 .pme_event = 2,
11692 .pme_chipno = 15,
11693 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11694 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11695 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11696 },
11697 /* M Counter 9 Event 3 */
11698 {
11699 .pme_name = "W_OUT_FLOWING_2@0",
11700 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 0)",
11701 .pme_code = 816,
11702 .pme_flags = 0x0,
11703 .pme_numasks = 0,
11704 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11705 .pme_ctr = 9,
11706 .pme_event = 3,
11707 .pme_chipno = 0,
11708 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11709 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11710 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11711 },
11712 {
11713 .pme_name = "W_OUT_FLOWING_2@1",
11714 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 1)",
11715 .pme_code = 817,
11716 .pme_flags = 0x0,
11717 .pme_numasks = 0,
11718 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11719 .pme_ctr = 9,
11720 .pme_event = 3,
11721 .pme_chipno = 1,
11722 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11723 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11724 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11725 },
11726 {
11727 .pme_name = "W_OUT_FLOWING_2@2",
11728 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 2)",
11729 .pme_code = 818,
11730 .pme_flags = 0x0,
11731 .pme_numasks = 0,
11732 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11733 .pme_ctr = 9,
11734 .pme_event = 3,
11735 .pme_chipno = 2,
11736 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11737 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11738 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11739 },
11740 {
11741 .pme_name = "W_OUT_FLOWING_2@3",
11742 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 3)",
11743 .pme_code = 819,
11744 .pme_flags = 0x0,
11745 .pme_numasks = 0,
11746 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11747 .pme_ctr = 9,
11748 .pme_event = 3,
11749 .pme_chipno = 3,
11750 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11751 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11752 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11753 },
11754 {
11755 .pme_name = "W_OUT_FLOWING_2@4",
11756 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 4)",
11757 .pme_code = 820,
11758 .pme_flags = 0x0,
11759 .pme_numasks = 0,
11760 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11761 .pme_ctr = 9,
11762 .pme_event = 3,
11763 .pme_chipno = 4,
11764 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11765 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11766 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11767 },
11768 {
11769 .pme_name = "W_OUT_FLOWING_2@5",
11770 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 5)",
11771 .pme_code = 821,
11772 .pme_flags = 0x0,
11773 .pme_numasks = 0,
11774 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11775 .pme_ctr = 9,
11776 .pme_event = 3,
11777 .pme_chipno = 5,
11778 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11779 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11780 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11781 },
11782 {
11783 .pme_name = "W_OUT_FLOWING_2@6",
11784 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 6)",
11785 .pme_code = 822,
11786 .pme_flags = 0x0,
11787 .pme_numasks = 0,
11788 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11789 .pme_ctr = 9,
11790 .pme_event = 3,
11791 .pme_chipno = 6,
11792 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11793 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11794 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11795 },
11796 {
11797 .pme_name = "W_OUT_FLOWING_2@7",
11798 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 7)",
11799 .pme_code = 823,
11800 .pme_flags = 0x0,
11801 .pme_numasks = 0,
11802 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11803 .pme_ctr = 9,
11804 .pme_event = 3,
11805 .pme_chipno = 7,
11806 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11807 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11808 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11809 },
11810 {
11811 .pme_name = "W_OUT_FLOWING_2@8",
11812 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 8)",
11813 .pme_code = 824,
11814 .pme_flags = 0x0,
11815 .pme_numasks = 0,
11816 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11817 .pme_ctr = 9,
11818 .pme_event = 3,
11819 .pme_chipno = 8,
11820 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11821 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11822 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11823 },
11824 {
11825 .pme_name = "W_OUT_FLOWING_2@9",
11826 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 9)",
11827 .pme_code = 825,
11828 .pme_flags = 0x0,
11829 .pme_numasks = 0,
11830 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11831 .pme_ctr = 9,
11832 .pme_event = 3,
11833 .pme_chipno = 9,
11834 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11835 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11836 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11837 },
11838 {
11839 .pme_name = "W_OUT_FLOWING_2@10",
11840 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 10)",
11841 .pme_code = 826,
11842 .pme_flags = 0x0,
11843 .pme_numasks = 0,
11844 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11845 .pme_ctr = 9,
11846 .pme_event = 3,
11847 .pme_chipno = 10,
11848 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11849 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11850 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11851 },
11852 {
11853 .pme_name = "W_OUT_FLOWING_2@11",
11854 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 11)",
11855 .pme_code = 827,
11856 .pme_flags = 0x0,
11857 .pme_numasks = 0,
11858 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11859 .pme_ctr = 9,
11860 .pme_event = 3,
11861 .pme_chipno = 11,
11862 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11863 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11864 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11865 },
11866 {
11867 .pme_name = "W_OUT_FLOWING_2@12",
11868 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 12)",
11869 .pme_code = 828,
11870 .pme_flags = 0x0,
11871 .pme_numasks = 0,
11872 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11873 .pme_ctr = 9,
11874 .pme_event = 3,
11875 .pme_chipno = 12,
11876 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11877 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11878 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11879 },
11880 {
11881 .pme_name = "W_OUT_FLOWING_2@13",
11882 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 13)",
11883 .pme_code = 829,
11884 .pme_flags = 0x0,
11885 .pme_numasks = 0,
11886 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11887 .pme_ctr = 9,
11888 .pme_event = 3,
11889 .pme_chipno = 13,
11890 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11891 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11892 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11893 },
11894 {
11895 .pme_name = "W_OUT_FLOWING_2@14",
11896 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 14)",
11897 .pme_code = 830,
11898 .pme_flags = 0x0,
11899 .pme_numasks = 0,
11900 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11901 .pme_ctr = 9,
11902 .pme_event = 3,
11903 .pme_chipno = 14,
11904 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11905 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11906 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11907 },
11908 {
11909 .pme_name = "W_OUT_FLOWING_2@15",
11910 .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 15)",
11911 .pme_code = 831,
11912 .pme_flags = 0x0,
11913 .pme_numasks = 0,
11914 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11915 .pme_ctr = 9,
11916 .pme_event = 3,
11917 .pme_chipno = 15,
11918 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11919 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11920 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11921 },
11922 /* M Counter 10 Event 0 */
11923 {
11924 .pme_name = "SUPPLY_EXCL@0",
11925 .pme_desc = "SupplyExcl packets received. (M chip 0)",
11926 .pme_code = 832,
11927 .pme_flags = 0x0,
11928 .pme_numasks = 0,
11929 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11930 .pme_ctr = 10,
11931 .pme_event = 0,
11932 .pme_chipno = 0,
11933 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11934 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11935 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11936 },
11937 {
11938 .pme_name = "SUPPLY_EXCL@1",
11939 .pme_desc = "SupplyExcl packets received. (M chip 1)",
11940 .pme_code = 833,
11941 .pme_flags = 0x0,
11942 .pme_numasks = 0,
11943 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11944 .pme_ctr = 10,
11945 .pme_event = 0,
11946 .pme_chipno = 1,
11947 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11948 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11949 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11950 },
11951 {
11952 .pme_name = "SUPPLY_EXCL@2",
11953 .pme_desc = "SupplyExcl packets received. (M chip 2)",
11954 .pme_code = 834,
11955 .pme_flags = 0x0,
11956 .pme_numasks = 0,
11957 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11958 .pme_ctr = 10,
11959 .pme_event = 0,
11960 .pme_chipno = 2,
11961 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11962 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11963 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11964 },
11965 {
11966 .pme_name = "SUPPLY_EXCL@3",
11967 .pme_desc = "SupplyExcl packets received. (M chip 3)",
11968 .pme_code = 835,
11969 .pme_flags = 0x0,
11970 .pme_numasks = 0,
11971 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11972 .pme_ctr = 10,
11973 .pme_event = 0,
11974 .pme_chipno = 3,
11975 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11976 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11977 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11978 },
11979 {
11980 .pme_name = "SUPPLY_EXCL@4",
11981 .pme_desc = "SupplyExcl packets received. (M chip 4)",
11982 .pme_code = 836,
11983 .pme_flags = 0x0,
11984 .pme_numasks = 0,
11985 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
11986 .pme_ctr = 10,
11987 .pme_event = 0,
11988 .pme_chipno = 4,
11989 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
11990 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
11991 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
11992 },
11993 {
11994 .pme_name = "SUPPLY_EXCL@5",
11995 .pme_desc = "SupplyExcl packets received. (M chip 5)",
11996 .pme_code = 837,
11997 .pme_flags = 0x0,
11998 .pme_numasks = 0,
11999 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12000 .pme_ctr = 10,
12001 .pme_event = 0,
12002 .pme_chipno = 5,
12003 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12004 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12005 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12006 },
12007 {
12008 .pme_name = "SUPPLY_EXCL@6",
12009 .pme_desc = "SupplyExcl packets received. (M chip 6)",
12010 .pme_code = 838,
12011 .pme_flags = 0x0,
12012 .pme_numasks = 0,
12013 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12014 .pme_ctr = 10,
12015 .pme_event = 0,
12016 .pme_chipno = 6,
12017 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12018 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12019 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12020 },
12021 {
12022 .pme_name = "SUPPLY_EXCL@7",
12023 .pme_desc = "SupplyExcl packets received. (M chip 7)",
12024 .pme_code = 839,
12025 .pme_flags = 0x0,
12026 .pme_numasks = 0,
12027 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12028 .pme_ctr = 10,
12029 .pme_event = 0,
12030 .pme_chipno = 7,
12031 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12032 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12033 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12034 },
12035 {
12036 .pme_name = "SUPPLY_EXCL@8",
12037 .pme_desc = "SupplyExcl packets received. (M chip 8)",
12038 .pme_code = 840,
12039 .pme_flags = 0x0,
12040 .pme_numasks = 0,
12041 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12042 .pme_ctr = 10,
12043 .pme_event = 0,
12044 .pme_chipno = 8,
12045 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12046 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12047 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12048 },
12049 {
12050 .pme_name = "SUPPLY_EXCL@9",
12051 .pme_desc = "SupplyExcl packets received. (M chip 9)",
12052 .pme_code = 841,
12053 .pme_flags = 0x0,
12054 .pme_numasks = 0,
12055 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12056 .pme_ctr = 10,
12057 .pme_event = 0,
12058 .pme_chipno = 9,
12059 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12060 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12061 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12062 },
12063 {
12064 .pme_name = "SUPPLY_EXCL@10",
12065 .pme_desc = "SupplyExcl packets received. (M chip 10)",
12066 .pme_code = 842,
12067 .pme_flags = 0x0,
12068 .pme_numasks = 0,
12069 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12070 .pme_ctr = 10,
12071 .pme_event = 0,
12072 .pme_chipno = 10,
12073 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12074 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12075 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12076 },
12077 {
12078 .pme_name = "SUPPLY_EXCL@11",
12079 .pme_desc = "SupplyExcl packets received. (M chip 11)",
12080 .pme_code = 843,
12081 .pme_flags = 0x0,
12082 .pme_numasks = 0,
12083 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12084 .pme_ctr = 10,
12085 .pme_event = 0,
12086 .pme_chipno = 11,
12087 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12088 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12089 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12090 },
12091 {
12092 .pme_name = "SUPPLY_EXCL@12",
12093 .pme_desc = "SupplyExcl packets received. (M chip 12)",
12094 .pme_code = 844,
12095 .pme_flags = 0x0,
12096 .pme_numasks = 0,
12097 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12098 .pme_ctr = 10,
12099 .pme_event = 0,
12100 .pme_chipno = 12,
12101 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12102 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12103 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12104 },
12105 {
12106 .pme_name = "SUPPLY_EXCL@13",
12107 .pme_desc = "SupplyExcl packets received. (M chip 13)",
12108 .pme_code = 845,
12109 .pme_flags = 0x0,
12110 .pme_numasks = 0,
12111 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12112 .pme_ctr = 10,
12113 .pme_event = 0,
12114 .pme_chipno = 13,
12115 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12116 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12117 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12118 },
12119 {
12120 .pme_name = "SUPPLY_EXCL@14",
12121 .pme_desc = "SupplyExcl packets received. (M chip 14)",
12122 .pme_code = 846,
12123 .pme_flags = 0x0,
12124 .pme_numasks = 0,
12125 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12126 .pme_ctr = 10,
12127 .pme_event = 0,
12128 .pme_chipno = 14,
12129 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12130 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12131 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12132 },
12133 {
12134 .pme_name = "SUPPLY_EXCL@15",
12135 .pme_desc = "SupplyExcl packets received. (M chip 15)",
12136 .pme_code = 847,
12137 .pme_flags = 0x0,
12138 .pme_numasks = 0,
12139 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12140 .pme_ctr = 10,
12141 .pme_event = 0,
12142 .pme_chipno = 15,
12143 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12144 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12145 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12146 },
12147 /* M Counter 10 Event 1 */
12148 {
12149 .pme_name = "W_OUT_FLOWING_3@0",
12150 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 0)",
12151 .pme_code = 848,
12152 .pme_flags = 0x0,
12153 .pme_numasks = 0,
12154 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12155 .pme_ctr = 10,
12156 .pme_event = 1,
12157 .pme_chipno = 0,
12158 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12159 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12160 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12161 },
12162 {
12163 .pme_name = "W_OUT_FLOWING_3@1",
12164 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 1)",
12165 .pme_code = 849,
12166 .pme_flags = 0x0,
12167 .pme_numasks = 0,
12168 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12169 .pme_ctr = 10,
12170 .pme_event = 1,
12171 .pme_chipno = 1,
12172 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12173 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12174 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12175 },
12176 {
12177 .pme_name = "W_OUT_FLOWING_3@2",
12178 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 2)",
12179 .pme_code = 850,
12180 .pme_flags = 0x0,
12181 .pme_numasks = 0,
12182 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12183 .pme_ctr = 10,
12184 .pme_event = 1,
12185 .pme_chipno = 2,
12186 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12187 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12188 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12189 },
12190 {
12191 .pme_name = "W_OUT_FLOWING_3@3",
12192 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 3)",
12193 .pme_code = 851,
12194 .pme_flags = 0x0,
12195 .pme_numasks = 0,
12196 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12197 .pme_ctr = 10,
12198 .pme_event = 1,
12199 .pme_chipno = 3,
12200 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12201 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12202 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12203 },
12204 {
12205 .pme_name = "W_OUT_FLOWING_3@4",
12206 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 4)",
12207 .pme_code = 852,
12208 .pme_flags = 0x0,
12209 .pme_numasks = 0,
12210 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12211 .pme_ctr = 10,
12212 .pme_event = 1,
12213 .pme_chipno = 4,
12214 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12215 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12216 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12217 },
12218 {
12219 .pme_name = "W_OUT_FLOWING_3@5",
12220 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 5)",
12221 .pme_code = 853,
12222 .pme_flags = 0x0,
12223 .pme_numasks = 0,
12224 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12225 .pme_ctr = 10,
12226 .pme_event = 1,
12227 .pme_chipno = 5,
12228 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12229 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12230 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12231 },
12232 {
12233 .pme_name = "W_OUT_FLOWING_3@6",
12234 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 6)",
12235 .pme_code = 854,
12236 .pme_flags = 0x0,
12237 .pme_numasks = 0,
12238 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12239 .pme_ctr = 10,
12240 .pme_event = 1,
12241 .pme_chipno = 6,
12242 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12243 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12244 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12245 },
12246 {
12247 .pme_name = "W_OUT_FLOWING_3@7",
12248 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 7)",
12249 .pme_code = 855,
12250 .pme_flags = 0x0,
12251 .pme_numasks = 0,
12252 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12253 .pme_ctr = 10,
12254 .pme_event = 1,
12255 .pme_chipno = 7,
12256 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12257 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12258 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12259 },
12260 {
12261 .pme_name = "W_OUT_FLOWING_3@8",
12262 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 8)",
12263 .pme_code = 856,
12264 .pme_flags = 0x0,
12265 .pme_numasks = 0,
12266 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12267 .pme_ctr = 10,
12268 .pme_event = 1,
12269 .pme_chipno = 8,
12270 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12271 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12272 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12273 },
12274 {
12275 .pme_name = "W_OUT_FLOWING_3@9",
12276 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 9)",
12277 .pme_code = 857,
12278 .pme_flags = 0x0,
12279 .pme_numasks = 0,
12280 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12281 .pme_ctr = 10,
12282 .pme_event = 1,
12283 .pme_chipno = 9,
12284 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12285 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12286 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12287 },
12288 {
12289 .pme_name = "W_OUT_FLOWING_3@10",
12290 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 10)",
12291 .pme_code = 858,
12292 .pme_flags = 0x0,
12293 .pme_numasks = 0,
12294 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12295 .pme_ctr = 10,
12296 .pme_event = 1,
12297 .pme_chipno = 10,
12298 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12299 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12300 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12301 },
12302 {
12303 .pme_name = "W_OUT_FLOWING_3@11",
12304 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 11)",
12305 .pme_code = 859,
12306 .pme_flags = 0x0,
12307 .pme_numasks = 0,
12308 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12309 .pme_ctr = 10,
12310 .pme_event = 1,
12311 .pme_chipno = 11,
12312 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12313 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12314 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12315 },
12316 {
12317 .pme_name = "W_OUT_FLOWING_3@12",
12318 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 12)",
12319 .pme_code = 860,
12320 .pme_flags = 0x0,
12321 .pme_numasks = 0,
12322 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12323 .pme_ctr = 10,
12324 .pme_event = 1,
12325 .pme_chipno = 12,
12326 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12327 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12328 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12329 },
12330 {
12331 .pme_name = "W_OUT_FLOWING_3@13",
12332 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 13)",
12333 .pme_code = 861,
12334 .pme_flags = 0x0,
12335 .pme_numasks = 0,
12336 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12337 .pme_ctr = 10,
12338 .pme_event = 1,
12339 .pme_chipno = 13,
12340 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12341 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12342 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12343 },
12344 {
12345 .pme_name = "W_OUT_FLOWING_3@14",
12346 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 14)",
12347 .pme_code = 862,
12348 .pme_flags = 0x0,
12349 .pme_numasks = 0,
12350 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12351 .pme_ctr = 10,
12352 .pme_event = 1,
12353 .pme_chipno = 14,
12354 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12355 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12356 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12357 },
12358 {
12359 .pme_name = "W_OUT_FLOWING_3@15",
12360 .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 15)",
12361 .pme_code = 863,
12362 .pme_flags = 0x0,
12363 .pme_numasks = 0,
12364 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12365 .pme_ctr = 10,
12366 .pme_event = 1,
12367 .pme_chipno = 15,
12368 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12369 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12370 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12371 },
12372 /* M Counter 10 Event 2 */
12373 {
12374 .pme_name = "W_IN_WAITING_2@0",
12375 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)",
12376 .pme_code = 864,
12377 .pme_flags = 0x0,
12378 .pme_numasks = 0,
12379 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12380 .pme_ctr = 10,
12381 .pme_event = 2,
12382 .pme_chipno = 0,
12383 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12384 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12385 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12386 },
12387 {
12388 .pme_name = "W_IN_WAITING_2@1",
12389 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)",
12390 .pme_code = 865,
12391 .pme_flags = 0x0,
12392 .pme_numasks = 0,
12393 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12394 .pme_ctr = 10,
12395 .pme_event = 2,
12396 .pme_chipno = 1,
12397 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12398 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12399 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12400 },
12401 {
12402 .pme_name = "W_IN_WAITING_2@2",
12403 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)",
12404 .pme_code = 866,
12405 .pme_flags = 0x0,
12406 .pme_numasks = 0,
12407 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12408 .pme_ctr = 10,
12409 .pme_event = 2,
12410 .pme_chipno = 2,
12411 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12412 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12413 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12414 },
12415 {
12416 .pme_name = "W_IN_WAITING_2@3",
12417 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)",
12418 .pme_code = 867,
12419 .pme_flags = 0x0,
12420 .pme_numasks = 0,
12421 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12422 .pme_ctr = 10,
12423 .pme_event = 2,
12424 .pme_chipno = 3,
12425 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12426 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12427 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12428 },
12429 {
12430 .pme_name = "W_IN_WAITING_2@4",
12431 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)",
12432 .pme_code = 868,
12433 .pme_flags = 0x0,
12434 .pme_numasks = 0,
12435 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12436 .pme_ctr = 10,
12437 .pme_event = 2,
12438 .pme_chipno = 4,
12439 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12440 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12441 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12442 },
12443 {
12444 .pme_name = "W_IN_WAITING_2@5",
12445 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)",
12446 .pme_code = 869,
12447 .pme_flags = 0x0,
12448 .pme_numasks = 0,
12449 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12450 .pme_ctr = 10,
12451 .pme_event = 2,
12452 .pme_chipno = 5,
12453 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12454 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12455 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12456 },
12457 {
12458 .pme_name = "W_IN_WAITING_2@6",
12459 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)",
12460 .pme_code = 870,
12461 .pme_flags = 0x0,
12462 .pme_numasks = 0,
12463 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12464 .pme_ctr = 10,
12465 .pme_event = 2,
12466 .pme_chipno = 6,
12467 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12468 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12469 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12470 },
12471 {
12472 .pme_name = "W_IN_WAITING_2@7",
12473 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)",
12474 .pme_code = 871,
12475 .pme_flags = 0x0,
12476 .pme_numasks = 0,
12477 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12478 .pme_ctr = 10,
12479 .pme_event = 2,
12480 .pme_chipno = 7,
12481 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12482 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12483 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12484 },
12485 {
12486 .pme_name = "W_IN_WAITING_2@8",
12487 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)",
12488 .pme_code = 872,
12489 .pme_flags = 0x0,
12490 .pme_numasks = 0,
12491 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12492 .pme_ctr = 10,
12493 .pme_event = 2,
12494 .pme_chipno = 8,
12495 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12496 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12497 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12498 },
12499 {
12500 .pme_name = "W_IN_WAITING_2@9",
12501 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)",
12502 .pme_code = 873,
12503 .pme_flags = 0x0,
12504 .pme_numasks = 0,
12505 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12506 .pme_ctr = 10,
12507 .pme_event = 2,
12508 .pme_chipno = 9,
12509 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12510 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12511 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12512 },
12513 {
12514 .pme_name = "W_IN_WAITING_2@10",
12515 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)",
12516 .pme_code = 874,
12517 .pme_flags = 0x0,
12518 .pme_numasks = 0,
12519 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12520 .pme_ctr = 10,
12521 .pme_event = 2,
12522 .pme_chipno = 10,
12523 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12524 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12525 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12526 },
12527 {
12528 .pme_name = "W_IN_WAITING_2@11",
12529 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)",
12530 .pme_code = 875,
12531 .pme_flags = 0x0,
12532 .pme_numasks = 0,
12533 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12534 .pme_ctr = 10,
12535 .pme_event = 2,
12536 .pme_chipno = 11,
12537 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12538 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12539 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12540 },
12541 {
12542 .pme_name = "W_IN_WAITING_2@12",
12543 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)",
12544 .pme_code = 876,
12545 .pme_flags = 0x0,
12546 .pme_numasks = 0,
12547 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12548 .pme_ctr = 10,
12549 .pme_event = 2,
12550 .pme_chipno = 12,
12551 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12552 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12553 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12554 },
12555 {
12556 .pme_name = "W_IN_WAITING_2@13",
12557 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)",
12558 .pme_code = 877,
12559 .pme_flags = 0x0,
12560 .pme_numasks = 0,
12561 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12562 .pme_ctr = 10,
12563 .pme_event = 2,
12564 .pme_chipno = 13,
12565 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12566 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12567 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12568 },
12569 {
12570 .pme_name = "W_IN_WAITING_2@14",
12571 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)",
12572 .pme_code = 878,
12573 .pme_flags = 0x0,
12574 .pme_numasks = 0,
12575 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12576 .pme_ctr = 10,
12577 .pme_event = 2,
12578 .pme_chipno = 14,
12579 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12580 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12581 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12582 },
12583 {
12584 .pme_name = "W_IN_WAITING_2@15",
12585 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)",
12586 .pme_code = 879,
12587 .pme_flags = 0x0,
12588 .pme_numasks = 0,
12589 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12590 .pme_ctr = 10,
12591 .pme_event = 2,
12592 .pme_chipno = 15,
12593 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12594 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12595 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12596 },
12597 /* M Counter 10 Event 3 */
12598 {
12599 .pme_name = "INVAL_3@0",
12600 .pme_desc = "Invalidations sent to three BWs. (M chip 0)",
12601 .pme_code = 880,
12602 .pme_flags = 0x0,
12603 .pme_numasks = 0,
12604 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12605 .pme_ctr = 10,
12606 .pme_event = 3,
12607 .pme_chipno = 0,
12608 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12609 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12610 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12611 },
12612 {
12613 .pme_name = "INVAL_3@1",
12614 .pme_desc = "Invalidations sent to three BWs. (M chip 1)",
12615 .pme_code = 881,
12616 .pme_flags = 0x0,
12617 .pme_numasks = 0,
12618 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12619 .pme_ctr = 10,
12620 .pme_event = 3,
12621 .pme_chipno = 1,
12622 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12623 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12624 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12625 },
12626 {
12627 .pme_name = "INVAL_3@2",
12628 .pme_desc = "Invalidations sent to three BWs. (M chip 2)",
12629 .pme_code = 882,
12630 .pme_flags = 0x0,
12631 .pme_numasks = 0,
12632 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12633 .pme_ctr = 10,
12634 .pme_event = 3,
12635 .pme_chipno = 2,
12636 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12637 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12638 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12639 },
12640 {
12641 .pme_name = "INVAL_3@3",
12642 .pme_desc = "Invalidations sent to three BWs. (M chip 3)",
12643 .pme_code = 883,
12644 .pme_flags = 0x0,
12645 .pme_numasks = 0,
12646 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12647 .pme_ctr = 10,
12648 .pme_event = 3,
12649 .pme_chipno = 3,
12650 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12651 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12652 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12653 },
12654 {
12655 .pme_name = "INVAL_3@4",
12656 .pme_desc = "Invalidations sent to three BWs. (M chip 4)",
12657 .pme_code = 884,
12658 .pme_flags = 0x0,
12659 .pme_numasks = 0,
12660 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12661 .pme_ctr = 10,
12662 .pme_event = 3,
12663 .pme_chipno = 4,
12664 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12665 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12666 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12667 },
12668 {
12669 .pme_name = "INVAL_3@5",
12670 .pme_desc = "Invalidations sent to three BWs. (M chip 5)",
12671 .pme_code = 885,
12672 .pme_flags = 0x0,
12673 .pme_numasks = 0,
12674 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12675 .pme_ctr = 10,
12676 .pme_event = 3,
12677 .pme_chipno = 5,
12678 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12679 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12680 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12681 },
12682 {
12683 .pme_name = "INVAL_3@6",
12684 .pme_desc = "Invalidations sent to three BWs. (M chip 6)",
12685 .pme_code = 886,
12686 .pme_flags = 0x0,
12687 .pme_numasks = 0,
12688 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12689 .pme_ctr = 10,
12690 .pme_event = 3,
12691 .pme_chipno = 6,
12692 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12693 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12694 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12695 },
12696 {
12697 .pme_name = "INVAL_3@7",
12698 .pme_desc = "Invalidations sent to three BWs. (M chip 7)",
12699 .pme_code = 887,
12700 .pme_flags = 0x0,
12701 .pme_numasks = 0,
12702 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12703 .pme_ctr = 10,
12704 .pme_event = 3,
12705 .pme_chipno = 7,
12706 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12707 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12708 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12709 },
12710 {
12711 .pme_name = "INVAL_3@8",
12712 .pme_desc = "Invalidations sent to three BWs. (M chip 8)",
12713 .pme_code = 888,
12714 .pme_flags = 0x0,
12715 .pme_numasks = 0,
12716 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12717 .pme_ctr = 10,
12718 .pme_event = 3,
12719 .pme_chipno = 8,
12720 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12721 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12722 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12723 },
12724 {
12725 .pme_name = "INVAL_3@9",
12726 .pme_desc = "Invalidations sent to three BWs. (M chip 9)",
12727 .pme_code = 889,
12728 .pme_flags = 0x0,
12729 .pme_numasks = 0,
12730 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12731 .pme_ctr = 10,
12732 .pme_event = 3,
12733 .pme_chipno = 9,
12734 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12735 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12736 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12737 },
12738 {
12739 .pme_name = "INVAL_3@10",
12740 .pme_desc = "Invalidations sent to three BWs. (M chip 10)",
12741 .pme_code = 890,
12742 .pme_flags = 0x0,
12743 .pme_numasks = 0,
12744 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12745 .pme_ctr = 10,
12746 .pme_event = 3,
12747 .pme_chipno = 10,
12748 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12749 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12750 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12751 },
12752 {
12753 .pme_name = "INVAL_3@11",
12754 .pme_desc = "Invalidations sent to three BWs. (M chip 11)",
12755 .pme_code = 891,
12756 .pme_flags = 0x0,
12757 .pme_numasks = 0,
12758 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12759 .pme_ctr = 10,
12760 .pme_event = 3,
12761 .pme_chipno = 11,
12762 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12763 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12764 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12765 },
12766 {
12767 .pme_name = "INVAL_3@12",
12768 .pme_desc = "Invalidations sent to three BWs. (M chip 12)",
12769 .pme_code = 892,
12770 .pme_flags = 0x0,
12771 .pme_numasks = 0,
12772 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12773 .pme_ctr = 10,
12774 .pme_event = 3,
12775 .pme_chipno = 12,
12776 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12777 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12778 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12779 },
12780 {
12781 .pme_name = "INVAL_3@13",
12782 .pme_desc = "Invalidations sent to three BWs. (M chip 13)",
12783 .pme_code = 893,
12784 .pme_flags = 0x0,
12785 .pme_numasks = 0,
12786 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12787 .pme_ctr = 10,
12788 .pme_event = 3,
12789 .pme_chipno = 13,
12790 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12791 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12792 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12793 },
12794 {
12795 .pme_name = "INVAL_3@14",
12796 .pme_desc = "Invalidations sent to three BWs. (M chip 14)",
12797 .pme_code = 894,
12798 .pme_flags = 0x0,
12799 .pme_numasks = 0,
12800 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12801 .pme_ctr = 10,
12802 .pme_event = 3,
12803 .pme_chipno = 14,
12804 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12805 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12806 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12807 },
12808 {
12809 .pme_name = "INVAL_3@15",
12810 .pme_desc = "Invalidations sent to three BWs. (M chip 15)",
12811 .pme_code = 895,
12812 .pme_flags = 0x0,
12813 .pme_numasks = 0,
12814 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12815 .pme_ctr = 10,
12816 .pme_event = 3,
12817 .pme_chipno = 15,
12818 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12819 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12820 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12821 },
12822 /* M Counter 11 Event 0 */
12823 {
12824 .pme_name = "NACKS_RECV@0",
12825 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 0)",
12826 .pme_code = 896,
12827 .pme_flags = 0x0,
12828 .pme_numasks = 0,
12829 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12830 .pme_ctr = 11,
12831 .pme_event = 0,
12832 .pme_chipno = 0,
12833 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12834 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12835 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12836 },
12837 {
12838 .pme_name = "NACKS_RECV@1",
12839 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 1)",
12840 .pme_code = 897,
12841 .pme_flags = 0x0,
12842 .pme_numasks = 0,
12843 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12844 .pme_ctr = 11,
12845 .pme_event = 0,
12846 .pme_chipno = 1,
12847 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12848 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12849 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12850 },
12851 {
12852 .pme_name = "NACKS_RECV@2",
12853 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 2)",
12854 .pme_code = 898,
12855 .pme_flags = 0x0,
12856 .pme_numasks = 0,
12857 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12858 .pme_ctr = 11,
12859 .pme_event = 0,
12860 .pme_chipno = 2,
12861 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12862 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12863 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12864 },
12865 {
12866 .pme_name = "NACKS_RECV@3",
12867 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 3)",
12868 .pme_code = 899,
12869 .pme_flags = 0x0,
12870 .pme_numasks = 0,
12871 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12872 .pme_ctr = 11,
12873 .pme_event = 0,
12874 .pme_chipno = 3,
12875 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12876 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12877 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12878 },
12879 {
12880 .pme_name = "NACKS_RECV@4",
12881 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 4)",
12882 .pme_code = 900,
12883 .pme_flags = 0x0,
12884 .pme_numasks = 0,
12885 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12886 .pme_ctr = 11,
12887 .pme_event = 0,
12888 .pme_chipno = 4,
12889 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12890 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12891 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12892 },
12893 {
12894 .pme_name = "NACKS_RECV@5",
12895 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 5)",
12896 .pme_code = 901,
12897 .pme_flags = 0x0,
12898 .pme_numasks = 0,
12899 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12900 .pme_ctr = 11,
12901 .pme_event = 0,
12902 .pme_chipno = 5,
12903 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12904 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12905 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12906 },
12907 {
12908 .pme_name = "NACKS_RECV@6",
12909 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 6)",
12910 .pme_code = 902,
12911 .pme_flags = 0x0,
12912 .pme_numasks = 0,
12913 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12914 .pme_ctr = 11,
12915 .pme_event = 0,
12916 .pme_chipno = 6,
12917 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12918 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12919 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12920 },
12921 {
12922 .pme_name = "NACKS_RECV@7",
12923 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 7)",
12924 .pme_code = 903,
12925 .pme_flags = 0x0,
12926 .pme_numasks = 0,
12927 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12928 .pme_ctr = 11,
12929 .pme_event = 0,
12930 .pme_chipno = 7,
12931 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12932 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12933 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12934 },
12935 {
12936 .pme_name = "NACKS_RECV@8",
12937 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 8)",
12938 .pme_code = 904,
12939 .pme_flags = 0x0,
12940 .pme_numasks = 0,
12941 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12942 .pme_ctr = 11,
12943 .pme_event = 0,
12944 .pme_chipno = 8,
12945 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12946 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12947 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12948 },
12949 {
12950 .pme_name = "NACKS_RECV@9",
12951 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 9)",
12952 .pme_code = 905,
12953 .pme_flags = 0x0,
12954 .pme_numasks = 0,
12955 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12956 .pme_ctr = 11,
12957 .pme_event = 0,
12958 .pme_chipno = 9,
12959 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12960 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12961 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12962 },
12963 {
12964 .pme_name = "NACKS_RECV@10",
12965 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 10)",
12966 .pme_code = 906,
12967 .pme_flags = 0x0,
12968 .pme_numasks = 0,
12969 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12970 .pme_ctr = 11,
12971 .pme_event = 0,
12972 .pme_chipno = 10,
12973 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12974 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12975 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12976 },
12977 {
12978 .pme_name = "NACKS_RECV@11",
12979 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 11)",
12980 .pme_code = 907,
12981 .pme_flags = 0x0,
12982 .pme_numasks = 0,
12983 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12984 .pme_ctr = 11,
12985 .pme_event = 0,
12986 .pme_chipno = 11,
12987 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
12988 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
12989 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
12990 },
12991 {
12992 .pme_name = "NACKS_RECV@12",
12993 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 12)",
12994 .pme_code = 908,
12995 .pme_flags = 0x0,
12996 .pme_numasks = 0,
12997 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
12998 .pme_ctr = 11,
12999 .pme_event = 0,
13000 .pme_chipno = 12,
13001 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13002 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13003 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13004 },
13005 {
13006 .pme_name = "NACKS_RECV@13",
13007 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 13)",
13008 .pme_code = 909,
13009 .pme_flags = 0x0,
13010 .pme_numasks = 0,
13011 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13012 .pme_ctr = 11,
13013 .pme_event = 0,
13014 .pme_chipno = 13,
13015 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13016 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13017 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13018 },
13019 {
13020 .pme_name = "NACKS_RECV@14",
13021 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 14)",
13022 .pme_code = 910,
13023 .pme_flags = 0x0,
13024 .pme_numasks = 0,
13025 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13026 .pme_ctr = 11,
13027 .pme_event = 0,
13028 .pme_chipno = 14,
13029 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13030 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13031 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13032 },
13033 {
13034 .pme_name = "NACKS_RECV@15",
13035 .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 15)",
13036 .pme_code = 911,
13037 .pme_flags = 0x0,
13038 .pme_numasks = 0,
13039 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13040 .pme_ctr = 11,
13041 .pme_event = 0,
13042 .pme_chipno = 15,
13043 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13044 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13045 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13046 },
13047 /* M Counter 11 Event 1 */
13048 {
13049 .pme_name = "W_OUT_BLOCK_CRED_0@0",
13050 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 0)",
13051 .pme_code = 912,
13052 .pme_flags = 0x0,
13053 .pme_numasks = 0,
13054 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13055 .pme_ctr = 11,
13056 .pme_event = 1,
13057 .pme_chipno = 0,
13058 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13059 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13060 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13061 },
13062 {
13063 .pme_name = "W_OUT_BLOCK_CRED_0@1",
13064 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 1)",
13065 .pme_code = 913,
13066 .pme_flags = 0x0,
13067 .pme_numasks = 0,
13068 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13069 .pme_ctr = 11,
13070 .pme_event = 1,
13071 .pme_chipno = 1,
13072 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13073 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13074 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13075 },
13076 {
13077 .pme_name = "W_OUT_BLOCK_CRED_0@2",
13078 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 2)",
13079 .pme_code = 914,
13080 .pme_flags = 0x0,
13081 .pme_numasks = 0,
13082 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13083 .pme_ctr = 11,
13084 .pme_event = 1,
13085 .pme_chipno = 2,
13086 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13087 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13088 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13089 },
13090 {
13091 .pme_name = "W_OUT_BLOCK_CRED_0@3",
13092 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 3)",
13093 .pme_code = 915,
13094 .pme_flags = 0x0,
13095 .pme_numasks = 0,
13096 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13097 .pme_ctr = 11,
13098 .pme_event = 1,
13099 .pme_chipno = 3,
13100 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13101 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13102 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13103 },
13104 {
13105 .pme_name = "W_OUT_BLOCK_CRED_0@4",
13106 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 4)",
13107 .pme_code = 916,
13108 .pme_flags = 0x0,
13109 .pme_numasks = 0,
13110 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13111 .pme_ctr = 11,
13112 .pme_event = 1,
13113 .pme_chipno = 4,
13114 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13115 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13116 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13117 },
13118 {
13119 .pme_name = "W_OUT_BLOCK_CRED_0@5",
13120 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 5)",
13121 .pme_code = 917,
13122 .pme_flags = 0x0,
13123 .pme_numasks = 0,
13124 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13125 .pme_ctr = 11,
13126 .pme_event = 1,
13127 .pme_chipno = 5,
13128 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13129 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13130 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13131 },
13132 {
13133 .pme_name = "W_OUT_BLOCK_CRED_0@6",
13134 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 6)",
13135 .pme_code = 918,
13136 .pme_flags = 0x0,
13137 .pme_numasks = 0,
13138 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13139 .pme_ctr = 11,
13140 .pme_event = 1,
13141 .pme_chipno = 6,
13142 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13143 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13144 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13145 },
13146 {
13147 .pme_name = "W_OUT_BLOCK_CRED_0@7",
13148 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 7)",
13149 .pme_code = 919,
13150 .pme_flags = 0x0,
13151 .pme_numasks = 0,
13152 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13153 .pme_ctr = 11,
13154 .pme_event = 1,
13155 .pme_chipno = 7,
13156 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13157 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13158 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13159 },
13160 {
13161 .pme_name = "W_OUT_BLOCK_CRED_0@8",
13162 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 8)",
13163 .pme_code = 920,
13164 .pme_flags = 0x0,
13165 .pme_numasks = 0,
13166 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13167 .pme_ctr = 11,
13168 .pme_event = 1,
13169 .pme_chipno = 8,
13170 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13171 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13172 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13173 },
13174 {
13175 .pme_name = "W_OUT_BLOCK_CRED_0@9",
13176 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 9)",
13177 .pme_code = 921,
13178 .pme_flags = 0x0,
13179 .pme_numasks = 0,
13180 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13181 .pme_ctr = 11,
13182 .pme_event = 1,
13183 .pme_chipno = 9,
13184 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13185 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13186 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13187 },
13188 {
13189 .pme_name = "W_OUT_BLOCK_CRED_0@10",
13190 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 10)",
13191 .pme_code = 922,
13192 .pme_flags = 0x0,
13193 .pme_numasks = 0,
13194 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13195 .pme_ctr = 11,
13196 .pme_event = 1,
13197 .pme_chipno = 10,
13198 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13199 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13200 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13201 },
13202 {
13203 .pme_name = "W_OUT_BLOCK_CRED_0@11",
13204 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 11)",
13205 .pme_code = 923,
13206 .pme_flags = 0x0,
13207 .pme_numasks = 0,
13208 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13209 .pme_ctr = 11,
13210 .pme_event = 1,
13211 .pme_chipno = 11,
13212 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13213 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13214 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13215 },
13216 {
13217 .pme_name = "W_OUT_BLOCK_CRED_0@12",
13218 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 12)",
13219 .pme_code = 924,
13220 .pme_flags = 0x0,
13221 .pme_numasks = 0,
13222 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13223 .pme_ctr = 11,
13224 .pme_event = 1,
13225 .pme_chipno = 12,
13226 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13227 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13228 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13229 },
13230 {
13231 .pme_name = "W_OUT_BLOCK_CRED_0@13",
13232 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 13)",
13233 .pme_code = 925,
13234 .pme_flags = 0x0,
13235 .pme_numasks = 0,
13236 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13237 .pme_ctr = 11,
13238 .pme_event = 1,
13239 .pme_chipno = 13,
13240 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13241 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13242 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13243 },
13244 {
13245 .pme_name = "W_OUT_BLOCK_CRED_0@14",
13246 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 14)",
13247 .pme_code = 926,
13248 .pme_flags = 0x0,
13249 .pme_numasks = 0,
13250 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13251 .pme_ctr = 11,
13252 .pme_event = 1,
13253 .pme_chipno = 14,
13254 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13255 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13256 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13257 },
13258 {
13259 .pme_name = "W_OUT_BLOCK_CRED_0@15",
13260 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 15)",
13261 .pme_code = 927,
13262 .pme_flags = 0x0,
13263 .pme_numasks = 0,
13264 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13265 .pme_ctr = 11,
13266 .pme_event = 1,
13267 .pme_chipno = 15,
13268 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13269 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13270 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13271 },
13272 /* M Counter 11 Event 2 */
13273 {
13274 .pme_name = "W_IN_WAITING_3@0",
13275 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)",
13276 .pme_code = 928,
13277 .pme_flags = 0x0,
13278 .pme_numasks = 0,
13279 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13280 .pme_ctr = 11,
13281 .pme_event = 2,
13282 .pme_chipno = 0,
13283 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13284 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13285 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13286 },
13287 {
13288 .pme_name = "W_IN_WAITING_3@1",
13289 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)",
13290 .pme_code = 929,
13291 .pme_flags = 0x0,
13292 .pme_numasks = 0,
13293 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13294 .pme_ctr = 11,
13295 .pme_event = 2,
13296 .pme_chipno = 1,
13297 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13298 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13299 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13300 },
13301 {
13302 .pme_name = "W_IN_WAITING_3@2",
13303 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)",
13304 .pme_code = 930,
13305 .pme_flags = 0x0,
13306 .pme_numasks = 0,
13307 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13308 .pme_ctr = 11,
13309 .pme_event = 2,
13310 .pme_chipno = 2,
13311 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13312 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13313 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13314 },
13315 {
13316 .pme_name = "W_IN_WAITING_3@3",
13317 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)",
13318 .pme_code = 931,
13319 .pme_flags = 0x0,
13320 .pme_numasks = 0,
13321 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13322 .pme_ctr = 11,
13323 .pme_event = 2,
13324 .pme_chipno = 3,
13325 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13326 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13327 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13328 },
13329 {
13330 .pme_name = "W_IN_WAITING_3@4",
13331 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)",
13332 .pme_code = 932,
13333 .pme_flags = 0x0,
13334 .pme_numasks = 0,
13335 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13336 .pme_ctr = 11,
13337 .pme_event = 2,
13338 .pme_chipno = 4,
13339 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13340 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13341 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13342 },
13343 {
13344 .pme_name = "W_IN_WAITING_3@5",
13345 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)",
13346 .pme_code = 933,
13347 .pme_flags = 0x0,
13348 .pme_numasks = 0,
13349 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13350 .pme_ctr = 11,
13351 .pme_event = 2,
13352 .pme_chipno = 5,
13353 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13354 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13355 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13356 },
13357 {
13358 .pme_name = "W_IN_WAITING_3@6",
13359 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)",
13360 .pme_code = 934,
13361 .pme_flags = 0x0,
13362 .pme_numasks = 0,
13363 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13364 .pme_ctr = 11,
13365 .pme_event = 2,
13366 .pme_chipno = 6,
13367 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13368 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13369 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13370 },
13371 {
13372 .pme_name = "W_IN_WAITING_3@7",
13373 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)",
13374 .pme_code = 935,
13375 .pme_flags = 0x0,
13376 .pme_numasks = 0,
13377 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13378 .pme_ctr = 11,
13379 .pme_event = 2,
13380 .pme_chipno = 7,
13381 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13382 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13383 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13384 },
13385 {
13386 .pme_name = "W_IN_WAITING_3@8",
13387 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)",
13388 .pme_code = 936,
13389 .pme_flags = 0x0,
13390 .pme_numasks = 0,
13391 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13392 .pme_ctr = 11,
13393 .pme_event = 2,
13394 .pme_chipno = 8,
13395 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13396 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13397 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13398 },
13399 {
13400 .pme_name = "W_IN_WAITING_3@9",
13401 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)",
13402 .pme_code = 937,
13403 .pme_flags = 0x0,
13404 .pme_numasks = 0,
13405 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13406 .pme_ctr = 11,
13407 .pme_event = 2,
13408 .pme_chipno = 9,
13409 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13410 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13411 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13412 },
13413 {
13414 .pme_name = "W_IN_WAITING_3@10",
13415 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)",
13416 .pme_code = 938,
13417 .pme_flags = 0x0,
13418 .pme_numasks = 0,
13419 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13420 .pme_ctr = 11,
13421 .pme_event = 2,
13422 .pme_chipno = 10,
13423 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13424 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13425 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13426 },
13427 {
13428 .pme_name = "W_IN_WAITING_3@11",
13429 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)",
13430 .pme_code = 939,
13431 .pme_flags = 0x0,
13432 .pme_numasks = 0,
13433 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13434 .pme_ctr = 11,
13435 .pme_event = 2,
13436 .pme_chipno = 11,
13437 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13438 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13439 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13440 },
13441 {
13442 .pme_name = "W_IN_WAITING_3@12",
13443 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)",
13444 .pme_code = 940,
13445 .pme_flags = 0x0,
13446 .pme_numasks = 0,
13447 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13448 .pme_ctr = 11,
13449 .pme_event = 2,
13450 .pme_chipno = 12,
13451 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13452 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13453 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13454 },
13455 {
13456 .pme_name = "W_IN_WAITING_3@13",
13457 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)",
13458 .pme_code = 941,
13459 .pme_flags = 0x0,
13460 .pme_numasks = 0,
13461 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13462 .pme_ctr = 11,
13463 .pme_event = 2,
13464 .pme_chipno = 13,
13465 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13466 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13467 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13468 },
13469 {
13470 .pme_name = "W_IN_WAITING_3@14",
13471 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)",
13472 .pme_code = 942,
13473 .pme_flags = 0x0,
13474 .pme_numasks = 0,
13475 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13476 .pme_ctr = 11,
13477 .pme_event = 2,
13478 .pme_chipno = 14,
13479 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13480 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13481 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13482 },
13483 {
13484 .pme_name = "W_IN_WAITING_3@15",
13485 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)",
13486 .pme_code = 943,
13487 .pme_flags = 0x0,
13488 .pme_numasks = 0,
13489 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13490 .pme_ctr = 11,
13491 .pme_event = 2,
13492 .pme_chipno = 15,
13493 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13494 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13495 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13496 },
13497 /* M Counter 11 Event 3 */
13498 {
13499 .pme_name = "INVAL_4@0",
13500 .pme_desc = "Invalidations sent to four BWs. (M chip 0)",
13501 .pme_code = 944,
13502 .pme_flags = 0x0,
13503 .pme_numasks = 0,
13504 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13505 .pme_ctr = 11,
13506 .pme_event = 3,
13507 .pme_chipno = 0,
13508 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13509 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13510 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13511 },
13512 {
13513 .pme_name = "INVAL_4@1",
13514 .pme_desc = "Invalidations sent to four BWs. (M chip 1)",
13515 .pme_code = 945,
13516 .pme_flags = 0x0,
13517 .pme_numasks = 0,
13518 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13519 .pme_ctr = 11,
13520 .pme_event = 3,
13521 .pme_chipno = 1,
13522 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13523 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13524 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13525 },
13526 {
13527 .pme_name = "INVAL_4@2",
13528 .pme_desc = "Invalidations sent to four BWs. (M chip 2)",
13529 .pme_code = 946,
13530 .pme_flags = 0x0,
13531 .pme_numasks = 0,
13532 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13533 .pme_ctr = 11,
13534 .pme_event = 3,
13535 .pme_chipno = 2,
13536 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13537 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13538 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13539 },
13540 {
13541 .pme_name = "INVAL_4@3",
13542 .pme_desc = "Invalidations sent to four BWs. (M chip 3)",
13543 .pme_code = 947,
13544 .pme_flags = 0x0,
13545 .pme_numasks = 0,
13546 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13547 .pme_ctr = 11,
13548 .pme_event = 3,
13549 .pme_chipno = 3,
13550 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13551 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13552 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13553 },
13554 {
13555 .pme_name = "INVAL_4@4",
13556 .pme_desc = "Invalidations sent to four BWs. (M chip 4)",
13557 .pme_code = 948,
13558 .pme_flags = 0x0,
13559 .pme_numasks = 0,
13560 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13561 .pme_ctr = 11,
13562 .pme_event = 3,
13563 .pme_chipno = 4,
13564 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13565 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13566 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13567 },
13568 {
13569 .pme_name = "INVAL_4@5",
13570 .pme_desc = "Invalidations sent to four BWs. (M chip 5)",
13571 .pme_code = 949,
13572 .pme_flags = 0x0,
13573 .pme_numasks = 0,
13574 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13575 .pme_ctr = 11,
13576 .pme_event = 3,
13577 .pme_chipno = 5,
13578 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13579 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13580 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13581 },
13582 {
13583 .pme_name = "INVAL_4@6",
13584 .pme_desc = "Invalidations sent to four BWs. (M chip 6)",
13585 .pme_code = 950,
13586 .pme_flags = 0x0,
13587 .pme_numasks = 0,
13588 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13589 .pme_ctr = 11,
13590 .pme_event = 3,
13591 .pme_chipno = 6,
13592 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13593 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13594 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13595 },
13596 {
13597 .pme_name = "INVAL_4@7",
13598 .pme_desc = "Invalidations sent to four BWs. (M chip 7)",
13599 .pme_code = 951,
13600 .pme_flags = 0x0,
13601 .pme_numasks = 0,
13602 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13603 .pme_ctr = 11,
13604 .pme_event = 3,
13605 .pme_chipno = 7,
13606 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13607 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13608 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13609 },
13610 {
13611 .pme_name = "INVAL_4@8",
13612 .pme_desc = "Invalidations sent to four BWs. (M chip 8)",
13613 .pme_code = 952,
13614 .pme_flags = 0x0,
13615 .pme_numasks = 0,
13616 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13617 .pme_ctr = 11,
13618 .pme_event = 3,
13619 .pme_chipno = 8,
13620 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13621 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13622 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13623 },
13624 {
13625 .pme_name = "INVAL_4@9",
13626 .pme_desc = "Invalidations sent to four BWs. (M chip 9)",
13627 .pme_code = 953,
13628 .pme_flags = 0x0,
13629 .pme_numasks = 0,
13630 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13631 .pme_ctr = 11,
13632 .pme_event = 3,
13633 .pme_chipno = 9,
13634 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13635 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13636 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13637 },
13638 {
13639 .pme_name = "INVAL_4@10",
13640 .pme_desc = "Invalidations sent to four BWs. (M chip 10)",
13641 .pme_code = 954,
13642 .pme_flags = 0x0,
13643 .pme_numasks = 0,
13644 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13645 .pme_ctr = 11,
13646 .pme_event = 3,
13647 .pme_chipno = 10,
13648 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13649 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13650 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13651 },
13652 {
13653 .pme_name = "INVAL_4@11",
13654 .pme_desc = "Invalidations sent to four BWs. (M chip 11)",
13655 .pme_code = 955,
13656 .pme_flags = 0x0,
13657 .pme_numasks = 0,
13658 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13659 .pme_ctr = 11,
13660 .pme_event = 3,
13661 .pme_chipno = 11,
13662 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13663 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13664 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13665 },
13666 {
13667 .pme_name = "INVAL_4@12",
13668 .pme_desc = "Invalidations sent to four BWs. (M chip 12)",
13669 .pme_code = 956,
13670 .pme_flags = 0x0,
13671 .pme_numasks = 0,
13672 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13673 .pme_ctr = 11,
13674 .pme_event = 3,
13675 .pme_chipno = 12,
13676 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13677 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13678 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13679 },
13680 {
13681 .pme_name = "INVAL_4@13",
13682 .pme_desc = "Invalidations sent to four BWs. (M chip 13)",
13683 .pme_code = 957,
13684 .pme_flags = 0x0,
13685 .pme_numasks = 0,
13686 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13687 .pme_ctr = 11,
13688 .pme_event = 3,
13689 .pme_chipno = 13,
13690 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13691 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13692 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13693 },
13694 {
13695 .pme_name = "INVAL_4@14",
13696 .pme_desc = "Invalidations sent to four BWs. (M chip 14)",
13697 .pme_code = 958,
13698 .pme_flags = 0x0,
13699 .pme_numasks = 0,
13700 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13701 .pme_ctr = 11,
13702 .pme_event = 3,
13703 .pme_chipno = 14,
13704 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13705 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13706 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13707 },
13708 {
13709 .pme_name = "INVAL_4@15",
13710 .pme_desc = "Invalidations sent to four BWs. (M chip 15)",
13711 .pme_code = 959,
13712 .pme_flags = 0x0,
13713 .pme_numasks = 0,
13714 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13715 .pme_ctr = 11,
13716 .pme_event = 3,
13717 .pme_chipno = 15,
13718 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13719 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13720 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13721 },
13722 /* M Counter 12 Event 0 */
13723 {
13724 .pme_name = "UPDATE_NACK_RECV@0",
13725 .pme_desc = "UpdateNacks received. (M chip 0)",
13726 .pme_code = 960,
13727 .pme_flags = 0x0,
13728 .pme_numasks = 0,
13729 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13730 .pme_ctr = 12,
13731 .pme_event = 0,
13732 .pme_chipno = 0,
13733 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13734 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13735 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13736 },
13737 {
13738 .pme_name = "UPDATE_NACK_RECV@1",
13739 .pme_desc = "UpdateNacks received. (M chip 1)",
13740 .pme_code = 961,
13741 .pme_flags = 0x0,
13742 .pme_numasks = 0,
13743 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13744 .pme_ctr = 12,
13745 .pme_event = 0,
13746 .pme_chipno = 1,
13747 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13748 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13749 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13750 },
13751 {
13752 .pme_name = "UPDATE_NACK_RECV@2",
13753 .pme_desc = "UpdateNacks received. (M chip 2)",
13754 .pme_code = 962,
13755 .pme_flags = 0x0,
13756 .pme_numasks = 0,
13757 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13758 .pme_ctr = 12,
13759 .pme_event = 0,
13760 .pme_chipno = 2,
13761 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13762 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13763 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13764 },
13765 {
13766 .pme_name = "UPDATE_NACK_RECV@3",
13767 .pme_desc = "UpdateNacks received. (M chip 3)",
13768 .pme_code = 963,
13769 .pme_flags = 0x0,
13770 .pme_numasks = 0,
13771 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13772 .pme_ctr = 12,
13773 .pme_event = 0,
13774 .pme_chipno = 3,
13775 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13776 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13777 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13778 },
13779 {
13780 .pme_name = "UPDATE_NACK_RECV@4",
13781 .pme_desc = "UpdateNacks received. (M chip 4)",
13782 .pme_code = 964,
13783 .pme_flags = 0x0,
13784 .pme_numasks = 0,
13785 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13786 .pme_ctr = 12,
13787 .pme_event = 0,
13788 .pme_chipno = 4,
13789 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13790 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13791 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13792 },
13793 {
13794 .pme_name = "UPDATE_NACK_RECV@5",
13795 .pme_desc = "UpdateNacks received. (M chip 5)",
13796 .pme_code = 965,
13797 .pme_flags = 0x0,
13798 .pme_numasks = 0,
13799 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13800 .pme_ctr = 12,
13801 .pme_event = 0,
13802 .pme_chipno = 5,
13803 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13804 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13805 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13806 },
13807 {
13808 .pme_name = "UPDATE_NACK_RECV@6",
13809 .pme_desc = "UpdateNacks received. (M chip 6)",
13810 .pme_code = 966,
13811 .pme_flags = 0x0,
13812 .pme_numasks = 0,
13813 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13814 .pme_ctr = 12,
13815 .pme_event = 0,
13816 .pme_chipno = 6,
13817 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13818 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13819 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13820 },
13821 {
13822 .pme_name = "UPDATE_NACK_RECV@7",
13823 .pme_desc = "UpdateNacks received. (M chip 7)",
13824 .pme_code = 967,
13825 .pme_flags = 0x0,
13826 .pme_numasks = 0,
13827 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13828 .pme_ctr = 12,
13829 .pme_event = 0,
13830 .pme_chipno = 7,
13831 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13832 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13833 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13834 },
13835 {
13836 .pme_name = "UPDATE_NACK_RECV@8",
13837 .pme_desc = "UpdateNacks received. (M chip 8)",
13838 .pme_code = 968,
13839 .pme_flags = 0x0,
13840 .pme_numasks = 0,
13841 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13842 .pme_ctr = 12,
13843 .pme_event = 0,
13844 .pme_chipno = 8,
13845 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13846 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13847 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13848 },
13849 {
13850 .pme_name = "UPDATE_NACK_RECV@9",
13851 .pme_desc = "UpdateNacks received. (M chip 9)",
13852 .pme_code = 969,
13853 .pme_flags = 0x0,
13854 .pme_numasks = 0,
13855 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13856 .pme_ctr = 12,
13857 .pme_event = 0,
13858 .pme_chipno = 9,
13859 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13860 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13861 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13862 },
13863 {
13864 .pme_name = "UPDATE_NACK_RECV@10",
13865 .pme_desc = "UpdateNacks received. (M chip 10)",
13866 .pme_code = 970,
13867 .pme_flags = 0x0,
13868 .pme_numasks = 0,
13869 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13870 .pme_ctr = 12,
13871 .pme_event = 0,
13872 .pme_chipno = 10,
13873 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13874 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13875 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13876 },
13877 {
13878 .pme_name = "UPDATE_NACK_RECV@11",
13879 .pme_desc = "UpdateNacks received. (M chip 11)",
13880 .pme_code = 971,
13881 .pme_flags = 0x0,
13882 .pme_numasks = 0,
13883 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13884 .pme_ctr = 12,
13885 .pme_event = 0,
13886 .pme_chipno = 11,
13887 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13888 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13889 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13890 },
13891 {
13892 .pme_name = "UPDATE_NACK_RECV@12",
13893 .pme_desc = "UpdateNacks received. (M chip 12)",
13894 .pme_code = 972,
13895 .pme_flags = 0x0,
13896 .pme_numasks = 0,
13897 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13898 .pme_ctr = 12,
13899 .pme_event = 0,
13900 .pme_chipno = 12,
13901 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13902 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13903 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13904 },
13905 {
13906 .pme_name = "UPDATE_NACK_RECV@13",
13907 .pme_desc = "UpdateNacks received. (M chip 13)",
13908 .pme_code = 973,
13909 .pme_flags = 0x0,
13910 .pme_numasks = 0,
13911 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13912 .pme_ctr = 12,
13913 .pme_event = 0,
13914 .pme_chipno = 13,
13915 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13916 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13917 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13918 },
13919 {
13920 .pme_name = "UPDATE_NACK_RECV@14",
13921 .pme_desc = "UpdateNacks received. (M chip 14)",
13922 .pme_code = 974,
13923 .pme_flags = 0x0,
13924 .pme_numasks = 0,
13925 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13926 .pme_ctr = 12,
13927 .pme_event = 0,
13928 .pme_chipno = 14,
13929 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13930 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13931 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13932 },
13933 {
13934 .pme_name = "UPDATE_NACK_RECV@15",
13935 .pme_desc = "UpdateNacks received. (M chip 15)",
13936 .pme_code = 975,
13937 .pme_flags = 0x0,
13938 .pme_numasks = 0,
13939 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13940 .pme_ctr = 12,
13941 .pme_event = 0,
13942 .pme_chipno = 15,
13943 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13944 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13945 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13946 },
13947 /* M Counter 12 Event 1 */
13948 {
13949 .pme_name = "W_OUT_BLOCK_CRED_1@0",
13950 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 0)",
13951 .pme_code = 976,
13952 .pme_flags = 0x0,
13953 .pme_numasks = 0,
13954 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13955 .pme_ctr = 12,
13956 .pme_event = 1,
13957 .pme_chipno = 0,
13958 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13959 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13960 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13961 },
13962 {
13963 .pme_name = "W_OUT_BLOCK_CRED_1@1",
13964 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 1)",
13965 .pme_code = 977,
13966 .pme_flags = 0x0,
13967 .pme_numasks = 0,
13968 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13969 .pme_ctr = 12,
13970 .pme_event = 1,
13971 .pme_chipno = 1,
13972 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13973 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13974 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13975 },
13976 {
13977 .pme_name = "W_OUT_BLOCK_CRED_1@2",
13978 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 2)",
13979 .pme_code = 978,
13980 .pme_flags = 0x0,
13981 .pme_numasks = 0,
13982 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13983 .pme_ctr = 12,
13984 .pme_event = 1,
13985 .pme_chipno = 2,
13986 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
13987 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
13988 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
13989 },
13990 {
13991 .pme_name = "W_OUT_BLOCK_CRED_1@3",
13992 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 3)",
13993 .pme_code = 979,
13994 .pme_flags = 0x0,
13995 .pme_numasks = 0,
13996 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
13997 .pme_ctr = 12,
13998 .pme_event = 1,
13999 .pme_chipno = 3,
14000 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14001 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14002 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14003 },
14004 {
14005 .pme_name = "W_OUT_BLOCK_CRED_1@4",
14006 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 4)",
14007 .pme_code = 980,
14008 .pme_flags = 0x0,
14009 .pme_numasks = 0,
14010 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14011 .pme_ctr = 12,
14012 .pme_event = 1,
14013 .pme_chipno = 4,
14014 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14015 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14016 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14017 },
14018 {
14019 .pme_name = "W_OUT_BLOCK_CRED_1@5",
14020 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 5)",
14021 .pme_code = 981,
14022 .pme_flags = 0x0,
14023 .pme_numasks = 0,
14024 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14025 .pme_ctr = 12,
14026 .pme_event = 1,
14027 .pme_chipno = 5,
14028 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14029 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14030 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14031 },
14032 {
14033 .pme_name = "W_OUT_BLOCK_CRED_1@6",
14034 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 6)",
14035 .pme_code = 982,
14036 .pme_flags = 0x0,
14037 .pme_numasks = 0,
14038 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14039 .pme_ctr = 12,
14040 .pme_event = 1,
14041 .pme_chipno = 6,
14042 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14043 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14044 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14045 },
14046 {
14047 .pme_name = "W_OUT_BLOCK_CRED_1@7",
14048 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 7)",
14049 .pme_code = 983,
14050 .pme_flags = 0x0,
14051 .pme_numasks = 0,
14052 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14053 .pme_ctr = 12,
14054 .pme_event = 1,
14055 .pme_chipno = 7,
14056 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14057 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14058 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14059 },
14060 {
14061 .pme_name = "W_OUT_BLOCK_CRED_1@8",
14062 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 8)",
14063 .pme_code = 984,
14064 .pme_flags = 0x0,
14065 .pme_numasks = 0,
14066 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14067 .pme_ctr = 12,
14068 .pme_event = 1,
14069 .pme_chipno = 8,
14070 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14071 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14072 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14073 },
14074 {
14075 .pme_name = "W_OUT_BLOCK_CRED_1@9",
14076 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 9)",
14077 .pme_code = 985,
14078 .pme_flags = 0x0,
14079 .pme_numasks = 0,
14080 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14081 .pme_ctr = 12,
14082 .pme_event = 1,
14083 .pme_chipno = 9,
14084 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14085 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14086 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14087 },
14088 {
14089 .pme_name = "W_OUT_BLOCK_CRED_1@10",
14090 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 10)",
14091 .pme_code = 986,
14092 .pme_flags = 0x0,
14093 .pme_numasks = 0,
14094 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14095 .pme_ctr = 12,
14096 .pme_event = 1,
14097 .pme_chipno = 10,
14098 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14099 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14100 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14101 },
14102 {
14103 .pme_name = "W_OUT_BLOCK_CRED_1@11",
14104 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 11)",
14105 .pme_code = 987,
14106 .pme_flags = 0x0,
14107 .pme_numasks = 0,
14108 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14109 .pme_ctr = 12,
14110 .pme_event = 1,
14111 .pme_chipno = 11,
14112 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14113 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14114 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14115 },
14116 {
14117 .pme_name = "W_OUT_BLOCK_CRED_1@12",
14118 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 12)",
14119 .pme_code = 988,
14120 .pme_flags = 0x0,
14121 .pme_numasks = 0,
14122 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14123 .pme_ctr = 12,
14124 .pme_event = 1,
14125 .pme_chipno = 12,
14126 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14127 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14128 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14129 },
14130 {
14131 .pme_name = "W_OUT_BLOCK_CRED_1@13",
14132 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 13)",
14133 .pme_code = 989,
14134 .pme_flags = 0x0,
14135 .pme_numasks = 0,
14136 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14137 .pme_ctr = 12,
14138 .pme_event = 1,
14139 .pme_chipno = 13,
14140 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14141 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14142 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14143 },
14144 {
14145 .pme_name = "W_OUT_BLOCK_CRED_1@14",
14146 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 14)",
14147 .pme_code = 990,
14148 .pme_flags = 0x0,
14149 .pme_numasks = 0,
14150 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14151 .pme_ctr = 12,
14152 .pme_event = 1,
14153 .pme_chipno = 14,
14154 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14155 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14156 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14157 },
14158 {
14159 .pme_name = "W_OUT_BLOCK_CRED_1@15",
14160 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 15)",
14161 .pme_code = 991,
14162 .pme_flags = 0x0,
14163 .pme_numasks = 0,
14164 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14165 .pme_ctr = 12,
14166 .pme_event = 1,
14167 .pme_chipno = 15,
14168 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14169 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14170 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14171 },
14172 /* M Counter 12 Event 2 */
14173 {
14174 .pme_name = "W_IN_BLOCKED_0@0",
14175 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 0)",
14176 .pme_code = 992,
14177 .pme_flags = 0x0,
14178 .pme_numasks = 0,
14179 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14180 .pme_ctr = 12,
14181 .pme_event = 2,
14182 .pme_chipno = 0,
14183 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14184 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14185 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14186 },
14187 {
14188 .pme_name = "W_IN_BLOCKED_0@1",
14189 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 1)",
14190 .pme_code = 993,
14191 .pme_flags = 0x0,
14192 .pme_numasks = 0,
14193 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14194 .pme_ctr = 12,
14195 .pme_event = 2,
14196 .pme_chipno = 1,
14197 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14198 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14199 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14200 },
14201 {
14202 .pme_name = "W_IN_BLOCKED_0@2",
14203 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 2)",
14204 .pme_code = 994,
14205 .pme_flags = 0x0,
14206 .pme_numasks = 0,
14207 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14208 .pme_ctr = 12,
14209 .pme_event = 2,
14210 .pme_chipno = 2,
14211 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14212 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14213 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14214 },
14215 {
14216 .pme_name = "W_IN_BLOCKED_0@3",
14217 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 3)",
14218 .pme_code = 995,
14219 .pme_flags = 0x0,
14220 .pme_numasks = 0,
14221 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14222 .pme_ctr = 12,
14223 .pme_event = 2,
14224 .pme_chipno = 3,
14225 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14226 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14227 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14228 },
14229 {
14230 .pme_name = "W_IN_BLOCKED_0@4",
14231 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 4)",
14232 .pme_code = 996,
14233 .pme_flags = 0x0,
14234 .pme_numasks = 0,
14235 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14236 .pme_ctr = 12,
14237 .pme_event = 2,
14238 .pme_chipno = 4,
14239 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14240 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14241 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14242 },
14243 {
14244 .pme_name = "W_IN_BLOCKED_0@5",
14245 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 5)",
14246 .pme_code = 997,
14247 .pme_flags = 0x0,
14248 .pme_numasks = 0,
14249 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14250 .pme_ctr = 12,
14251 .pme_event = 2,
14252 .pme_chipno = 5,
14253 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14254 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14255 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14256 },
14257 {
14258 .pme_name = "W_IN_BLOCKED_0@6",
14259 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 6)",
14260 .pme_code = 998,
14261 .pme_flags = 0x0,
14262 .pme_numasks = 0,
14263 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14264 .pme_ctr = 12,
14265 .pme_event = 2,
14266 .pme_chipno = 6,
14267 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14268 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14269 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14270 },
14271 {
14272 .pme_name = "W_IN_BLOCKED_0@7",
14273 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 7)",
14274 .pme_code = 999,
14275 .pme_flags = 0x0,
14276 .pme_numasks = 0,
14277 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14278 .pme_ctr = 12,
14279 .pme_event = 2,
14280 .pme_chipno = 7,
14281 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14282 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14283 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14284 },
14285 {
14286 .pme_name = "W_IN_BLOCKED_0@8",
14287 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 8)",
14288 .pme_code = 1000,
14289 .pme_flags = 0x0,
14290 .pme_numasks = 0,
14291 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14292 .pme_ctr = 12,
14293 .pme_event = 2,
14294 .pme_chipno = 8,
14295 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14296 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14297 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14298 },
14299 {
14300 .pme_name = "W_IN_BLOCKED_0@9",
14301 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 9)",
14302 .pme_code = 1001,
14303 .pme_flags = 0x0,
14304 .pme_numasks = 0,
14305 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14306 .pme_ctr = 12,
14307 .pme_event = 2,
14308 .pme_chipno = 9,
14309 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14310 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14311 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14312 },
14313 {
14314 .pme_name = "W_IN_BLOCKED_0@10",
14315 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 10)",
14316 .pme_code = 1002,
14317 .pme_flags = 0x0,
14318 .pme_numasks = 0,
14319 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14320 .pme_ctr = 12,
14321 .pme_event = 2,
14322 .pme_chipno = 10,
14323 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14324 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14325 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14326 },
14327 {
14328 .pme_name = "W_IN_BLOCKED_0@11",
14329 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 11)",
14330 .pme_code = 1003,
14331 .pme_flags = 0x0,
14332 .pme_numasks = 0,
14333 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14334 .pme_ctr = 12,
14335 .pme_event = 2,
14336 .pme_chipno = 11,
14337 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14338 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14339 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14340 },
14341 {
14342 .pme_name = "W_IN_BLOCKED_0@12",
14343 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 12)",
14344 .pme_code = 1004,
14345 .pme_flags = 0x0,
14346 .pme_numasks = 0,
14347 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14348 .pme_ctr = 12,
14349 .pme_event = 2,
14350 .pme_chipno = 12,
14351 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14352 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14353 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14354 },
14355 {
14356 .pme_name = "W_IN_BLOCKED_0@13",
14357 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 13)",
14358 .pme_code = 1005,
14359 .pme_flags = 0x0,
14360 .pme_numasks = 0,
14361 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14362 .pme_ctr = 12,
14363 .pme_event = 2,
14364 .pme_chipno = 13,
14365 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14366 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14367 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14368 },
14369 {
14370 .pme_name = "W_IN_BLOCKED_0@14",
14371 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 14)",
14372 .pme_code = 1006,
14373 .pme_flags = 0x0,
14374 .pme_numasks = 0,
14375 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14376 .pme_ctr = 12,
14377 .pme_event = 2,
14378 .pme_chipno = 14,
14379 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14380 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14381 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14382 },
14383 {
14384 .pme_name = "W_IN_BLOCKED_0@15",
14385 .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 15)",
14386 .pme_code = 1007,
14387 .pme_flags = 0x0,
14388 .pme_numasks = 0,
14389 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14390 .pme_ctr = 12,
14391 .pme_event = 2,
14392 .pme_chipno = 15,
14393 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14394 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14395 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14396 },
14397 /* M Counter 12 Event 3 */
14398 {
14399 .pme_name = "FWD_GET_SENT@0",
14400 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 0)",
14401 .pme_code = 1008,
14402 .pme_flags = 0x0,
14403 .pme_numasks = 0,
14404 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14405 .pme_ctr = 12,
14406 .pme_event = 3,
14407 .pme_chipno = 0,
14408 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14409 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14410 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14411 },
14412 {
14413 .pme_name = "FWD_GET_SENT@1",
14414 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 1)",
14415 .pme_code = 1009,
14416 .pme_flags = 0x0,
14417 .pme_numasks = 0,
14418 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14419 .pme_ctr = 12,
14420 .pme_event = 3,
14421 .pme_chipno = 1,
14422 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14423 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14424 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14425 },
14426 {
14427 .pme_name = "FWD_GET_SENT@2",
14428 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 2)",
14429 .pme_code = 1010,
14430 .pme_flags = 0x0,
14431 .pme_numasks = 0,
14432 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14433 .pme_ctr = 12,
14434 .pme_event = 3,
14435 .pme_chipno = 2,
14436 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14437 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14438 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14439 },
14440 {
14441 .pme_name = "FWD_GET_SENT@3",
14442 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 3)",
14443 .pme_code = 1011,
14444 .pme_flags = 0x0,
14445 .pme_numasks = 0,
14446 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14447 .pme_ctr = 12,
14448 .pme_event = 3,
14449 .pme_chipno = 3,
14450 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14451 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14452 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14453 },
14454 {
14455 .pme_name = "FWD_GET_SENT@4",
14456 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 4)",
14457 .pme_code = 1012,
14458 .pme_flags = 0x0,
14459 .pme_numasks = 0,
14460 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14461 .pme_ctr = 12,
14462 .pme_event = 3,
14463 .pme_chipno = 4,
14464 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14465 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14466 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14467 },
14468 {
14469 .pme_name = "FWD_GET_SENT@5",
14470 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 5)",
14471 .pme_code = 1013,
14472 .pme_flags = 0x0,
14473 .pme_numasks = 0,
14474 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14475 .pme_ctr = 12,
14476 .pme_event = 3,
14477 .pme_chipno = 5,
14478 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14479 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14480 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14481 },
14482 {
14483 .pme_name = "FWD_GET_SENT@6",
14484 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 6)",
14485 .pme_code = 1014,
14486 .pme_flags = 0x0,
14487 .pme_numasks = 0,
14488 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14489 .pme_ctr = 12,
14490 .pme_event = 3,
14491 .pme_chipno = 6,
14492 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14493 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14494 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14495 },
14496 {
14497 .pme_name = "FWD_GET_SENT@7",
14498 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 7)",
14499 .pme_code = 1015,
14500 .pme_flags = 0x0,
14501 .pme_numasks = 0,
14502 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14503 .pme_ctr = 12,
14504 .pme_event = 3,
14505 .pme_chipno = 7,
14506 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14507 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14508 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14509 },
14510 {
14511 .pme_name = "FWD_GET_SENT@8",
14512 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 8)",
14513 .pme_code = 1016,
14514 .pme_flags = 0x0,
14515 .pme_numasks = 0,
14516 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14517 .pme_ctr = 12,
14518 .pme_event = 3,
14519 .pme_chipno = 8,
14520 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14521 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14522 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14523 },
14524 {
14525 .pme_name = "FWD_GET_SENT@9",
14526 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 9)",
14527 .pme_code = 1017,
14528 .pme_flags = 0x0,
14529 .pme_numasks = 0,
14530 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14531 .pme_ctr = 12,
14532 .pme_event = 3,
14533 .pme_chipno = 9,
14534 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14535 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14536 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14537 },
14538 {
14539 .pme_name = "FWD_GET_SENT@10",
14540 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 10)",
14541 .pme_code = 1018,
14542 .pme_flags = 0x0,
14543 .pme_numasks = 0,
14544 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14545 .pme_ctr = 12,
14546 .pme_event = 3,
14547 .pme_chipno = 10,
14548 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14549 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14550 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14551 },
14552 {
14553 .pme_name = "FWD_GET_SENT@11",
14554 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 11)",
14555 .pme_code = 1019,
14556 .pme_flags = 0x0,
14557 .pme_numasks = 0,
14558 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14559 .pme_ctr = 12,
14560 .pme_event = 3,
14561 .pme_chipno = 11,
14562 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14563 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14564 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14565 },
14566 {
14567 .pme_name = "FWD_GET_SENT@12",
14568 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 12)",
14569 .pme_code = 1020,
14570 .pme_flags = 0x0,
14571 .pme_numasks = 0,
14572 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14573 .pme_ctr = 12,
14574 .pme_event = 3,
14575 .pme_chipno = 12,
14576 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14577 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14578 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14579 },
14580 {
14581 .pme_name = "FWD_GET_SENT@13",
14582 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 13)",
14583 .pme_code = 1021,
14584 .pme_flags = 0x0,
14585 .pme_numasks = 0,
14586 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14587 .pme_ctr = 12,
14588 .pme_event = 3,
14589 .pme_chipno = 13,
14590 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14591 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14592 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14593 },
14594 {
14595 .pme_name = "FWD_GET_SENT@14",
14596 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 14)",
14597 .pme_code = 1022,
14598 .pme_flags = 0x0,
14599 .pme_numasks = 0,
14600 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14601 .pme_ctr = 12,
14602 .pme_event = 3,
14603 .pme_chipno = 14,
14604 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14605 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14606 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14607 },
14608 {
14609 .pme_name = "FWD_GET_SENT@15",
14610 .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 15)",
14611 .pme_code = 1023,
14612 .pme_flags = 0x0,
14613 .pme_numasks = 0,
14614 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14615 .pme_ctr = 12,
14616 .pme_event = 3,
14617 .pme_chipno = 15,
14618 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14619 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14620 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14621 },
14622 /* M Counter 13 Event 0 */
14623 {
14624 .pme_name = "PEND_DROP@0",
14625 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 0)",
14626 .pme_code = 1024,
14627 .pme_flags = 0x0,
14628 .pme_numasks = 0,
14629 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14630 .pme_ctr = 13,
14631 .pme_event = 0,
14632 .pme_chipno = 0,
14633 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14634 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14635 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14636 },
14637 {
14638 .pme_name = "PEND_DROP@1",
14639 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 1)",
14640 .pme_code = 1025,
14641 .pme_flags = 0x0,
14642 .pme_numasks = 0,
14643 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14644 .pme_ctr = 13,
14645 .pme_event = 0,
14646 .pme_chipno = 1,
14647 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14648 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14649 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14650 },
14651 {
14652 .pme_name = "PEND_DROP@2",
14653 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 2)",
14654 .pme_code = 1026,
14655 .pme_flags = 0x0,
14656 .pme_numasks = 0,
14657 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14658 .pme_ctr = 13,
14659 .pme_event = 0,
14660 .pme_chipno = 2,
14661 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14662 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14663 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14664 },
14665 {
14666 .pme_name = "PEND_DROP@3",
14667 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 3)",
14668 .pme_code = 1027,
14669 .pme_flags = 0x0,
14670 .pme_numasks = 0,
14671 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14672 .pme_ctr = 13,
14673 .pme_event = 0,
14674 .pme_chipno = 3,
14675 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14676 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14677 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14678 },
14679 {
14680 .pme_name = "PEND_DROP@4",
14681 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 4)",
14682 .pme_code = 1028,
14683 .pme_flags = 0x0,
14684 .pme_numasks = 0,
14685 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14686 .pme_ctr = 13,
14687 .pme_event = 0,
14688 .pme_chipno = 4,
14689 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14690 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14691 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14692 },
14693 {
14694 .pme_name = "PEND_DROP@5",
14695 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 5)",
14696 .pme_code = 1029,
14697 .pme_flags = 0x0,
14698 .pme_numasks = 0,
14699 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14700 .pme_ctr = 13,
14701 .pme_event = 0,
14702 .pme_chipno = 5,
14703 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14704 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14705 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14706 },
14707 {
14708 .pme_name = "PEND_DROP@6",
14709 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 6)",
14710 .pme_code = 1030,
14711 .pme_flags = 0x0,
14712 .pme_numasks = 0,
14713 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14714 .pme_ctr = 13,
14715 .pme_event = 0,
14716 .pme_chipno = 6,
14717 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14718 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14719 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14720 },
14721 {
14722 .pme_name = "PEND_DROP@7",
14723 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 7)",
14724 .pme_code = 1031,
14725 .pme_flags = 0x0,
14726 .pme_numasks = 0,
14727 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14728 .pme_ctr = 13,
14729 .pme_event = 0,
14730 .pme_chipno = 7,
14731 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14732 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14733 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14734 },
14735 {
14736 .pme_name = "PEND_DROP@8",
14737 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 8)",
14738 .pme_code = 1032,
14739 .pme_flags = 0x0,
14740 .pme_numasks = 0,
14741 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14742 .pme_ctr = 13,
14743 .pme_event = 0,
14744 .pme_chipno = 8,
14745 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14746 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14747 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14748 },
14749 {
14750 .pme_name = "PEND_DROP@9",
14751 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 9)",
14752 .pme_code = 1033,
14753 .pme_flags = 0x0,
14754 .pme_numasks = 0,
14755 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14756 .pme_ctr = 13,
14757 .pme_event = 0,
14758 .pme_chipno = 9,
14759 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14760 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14761 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14762 },
14763 {
14764 .pme_name = "PEND_DROP@10",
14765 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 10)",
14766 .pme_code = 1034,
14767 .pme_flags = 0x0,
14768 .pme_numasks = 0,
14769 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14770 .pme_ctr = 13,
14771 .pme_event = 0,
14772 .pme_chipno = 10,
14773 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14774 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14775 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14776 },
14777 {
14778 .pme_name = "PEND_DROP@11",
14779 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 11)",
14780 .pme_code = 1035,
14781 .pme_flags = 0x0,
14782 .pme_numasks = 0,
14783 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14784 .pme_ctr = 13,
14785 .pme_event = 0,
14786 .pme_chipno = 11,
14787 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14788 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14789 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14790 },
14791 {
14792 .pme_name = "PEND_DROP@12",
14793 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 12)",
14794 .pme_code = 1036,
14795 .pme_flags = 0x0,
14796 .pme_numasks = 0,
14797 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14798 .pme_ctr = 13,
14799 .pme_event = 0,
14800 .pme_chipno = 12,
14801 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14802 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14803 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14804 },
14805 {
14806 .pme_name = "PEND_DROP@13",
14807 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 13)",
14808 .pme_code = 1037,
14809 .pme_flags = 0x0,
14810 .pme_numasks = 0,
14811 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14812 .pme_ctr = 13,
14813 .pme_event = 0,
14814 .pme_chipno = 13,
14815 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14816 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14817 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14818 },
14819 {
14820 .pme_name = "PEND_DROP@14",
14821 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 14)",
14822 .pme_code = 1038,
14823 .pme_flags = 0x0,
14824 .pme_numasks = 0,
14825 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14826 .pme_ctr = 13,
14827 .pme_event = 0,
14828 .pme_chipno = 14,
14829 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14830 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14831 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14832 },
14833 {
14834 .pme_name = "PEND_DROP@15",
14835 .pme_desc = "Times entering PendDrop state (from Shared). (M chip 15)",
14836 .pme_code = 1039,
14837 .pme_flags = 0x0,
14838 .pme_numasks = 0,
14839 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14840 .pme_ctr = 13,
14841 .pme_event = 0,
14842 .pme_chipno = 15,
14843 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14844 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14845 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14846 },
14847 /* M Counter 13 Event 1 */
14848 {
14849 .pme_name = "LINE_EVICTIONS@0",
14850 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 0)",
14851 .pme_code = 1040,
14852 .pme_flags = 0x0,
14853 .pme_numasks = 0,
14854 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14855 .pme_ctr = 13,
14856 .pme_event = 1,
14857 .pme_chipno = 0,
14858 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14859 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14860 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14861 },
14862 {
14863 .pme_name = "LINE_EVICTIONS@1",
14864 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 1)",
14865 .pme_code = 1041,
14866 .pme_flags = 0x0,
14867 .pme_numasks = 0,
14868 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14869 .pme_ctr = 13,
14870 .pme_event = 1,
14871 .pme_chipno = 1,
14872 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14873 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14874 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14875 },
14876 {
14877 .pme_name = "LINE_EVICTIONS@2",
14878 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 2)",
14879 .pme_code = 1042,
14880 .pme_flags = 0x0,
14881 .pme_numasks = 0,
14882 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14883 .pme_ctr = 13,
14884 .pme_event = 1,
14885 .pme_chipno = 2,
14886 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14887 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14888 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14889 },
14890 {
14891 .pme_name = "LINE_EVICTIONS@3",
14892 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 3)",
14893 .pme_code = 1043,
14894 .pme_flags = 0x0,
14895 .pme_numasks = 0,
14896 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14897 .pme_ctr = 13,
14898 .pme_event = 1,
14899 .pme_chipno = 3,
14900 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14901 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14902 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14903 },
14904 {
14905 .pme_name = "LINE_EVICTIONS@4",
14906 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 4)",
14907 .pme_code = 1044,
14908 .pme_flags = 0x0,
14909 .pme_numasks = 0,
14910 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14911 .pme_ctr = 13,
14912 .pme_event = 1,
14913 .pme_chipno = 4,
14914 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14915 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14916 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14917 },
14918 {
14919 .pme_name = "LINE_EVICTIONS@5",
14920 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 5)",
14921 .pme_code = 1045,
14922 .pme_flags = 0x0,
14923 .pme_numasks = 0,
14924 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14925 .pme_ctr = 13,
14926 .pme_event = 1,
14927 .pme_chipno = 5,
14928 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14929 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14930 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14931 },
14932 {
14933 .pme_name = "LINE_EVICTIONS@6",
14934 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 6)",
14935 .pme_code = 1046,
14936 .pme_flags = 0x0,
14937 .pme_numasks = 0,
14938 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14939 .pme_ctr = 13,
14940 .pme_event = 1,
14941 .pme_chipno = 6,
14942 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14943 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14944 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14945 },
14946 {
14947 .pme_name = "LINE_EVICTIONS@7",
14948 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 7)",
14949 .pme_code = 1047,
14950 .pme_flags = 0x0,
14951 .pme_numasks = 0,
14952 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14953 .pme_ctr = 13,
14954 .pme_event = 1,
14955 .pme_chipno = 7,
14956 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14957 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14958 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14959 },
14960 {
14961 .pme_name = "LINE_EVICTIONS@8",
14962 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 8)",
14963 .pme_code = 1048,
14964 .pme_flags = 0x0,
14965 .pme_numasks = 0,
14966 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14967 .pme_ctr = 13,
14968 .pme_event = 1,
14969 .pme_chipno = 8,
14970 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14971 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14972 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14973 },
14974 {
14975 .pme_name = "LINE_EVICTIONS@9",
14976 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 9)",
14977 .pme_code = 1049,
14978 .pme_flags = 0x0,
14979 .pme_numasks = 0,
14980 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14981 .pme_ctr = 13,
14982 .pme_event = 1,
14983 .pme_chipno = 9,
14984 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14985 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
14986 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
14987 },
14988 {
14989 .pme_name = "LINE_EVICTIONS@10",
14990 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 10)",
14991 .pme_code = 1050,
14992 .pme_flags = 0x0,
14993 .pme_numasks = 0,
14994 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
14995 .pme_ctr = 13,
14996 .pme_event = 1,
14997 .pme_chipno = 10,
14998 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
14999 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15000 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15001 },
15002 {
15003 .pme_name = "LINE_EVICTIONS@11",
15004 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 11)",
15005 .pme_code = 1051,
15006 .pme_flags = 0x0,
15007 .pme_numasks = 0,
15008 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15009 .pme_ctr = 13,
15010 .pme_event = 1,
15011 .pme_chipno = 11,
15012 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15013 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15014 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15015 },
15016 {
15017 .pme_name = "LINE_EVICTIONS@12",
15018 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 12)",
15019 .pme_code = 1052,
15020 .pme_flags = 0x0,
15021 .pme_numasks = 0,
15022 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15023 .pme_ctr = 13,
15024 .pme_event = 1,
15025 .pme_chipno = 12,
15026 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15027 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15028 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15029 },
15030 {
15031 .pme_name = "LINE_EVICTIONS@13",
15032 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 13)",
15033 .pme_code = 1053,
15034 .pme_flags = 0x0,
15035 .pme_numasks = 0,
15036 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15037 .pme_ctr = 13,
15038 .pme_event = 1,
15039 .pme_chipno = 13,
15040 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15041 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15042 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15043 },
15044 {
15045 .pme_name = "LINE_EVICTIONS@14",
15046 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 14)",
15047 .pme_code = 1054,
15048 .pme_flags = 0x0,
15049 .pme_numasks = 0,
15050 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15051 .pme_ctr = 13,
15052 .pme_event = 1,
15053 .pme_chipno = 14,
15054 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15055 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15056 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15057 },
15058 {
15059 .pme_name = "LINE_EVICTIONS@15",
15060 .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 15)",
15061 .pme_code = 1055,
15062 .pme_flags = 0x0,
15063 .pme_numasks = 0,
15064 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15065 .pme_ctr = 13,
15066 .pme_event = 1,
15067 .pme_chipno = 15,
15068 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15069 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15070 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15071 },
15072 /* M Counter 13 Event 2 */
15073 {
15074 .pme_name = "W_IN_BLOCKED_1@0",
15075 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 0)",
15076 .pme_code = 1056,
15077 .pme_flags = 0x0,
15078 .pme_numasks = 0,
15079 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15080 .pme_ctr = 13,
15081 .pme_event = 2,
15082 .pme_chipno = 0,
15083 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15084 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15085 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15086 },
15087 {
15088 .pme_name = "W_IN_BLOCKED_1@1",
15089 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 1)",
15090 .pme_code = 1057,
15091 .pme_flags = 0x0,
15092 .pme_numasks = 0,
15093 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15094 .pme_ctr = 13,
15095 .pme_event = 2,
15096 .pme_chipno = 1,
15097 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15098 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15099 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15100 },
15101 {
15102 .pme_name = "W_IN_BLOCKED_1@2",
15103 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 2)",
15104 .pme_code = 1058,
15105 .pme_flags = 0x0,
15106 .pme_numasks = 0,
15107 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15108 .pme_ctr = 13,
15109 .pme_event = 2,
15110 .pme_chipno = 2,
15111 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15112 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15113 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15114 },
15115 {
15116 .pme_name = "W_IN_BLOCKED_1@3",
15117 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 3)",
15118 .pme_code = 1059,
15119 .pme_flags = 0x0,
15120 .pme_numasks = 0,
15121 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15122 .pme_ctr = 13,
15123 .pme_event = 2,
15124 .pme_chipno = 3,
15125 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15126 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15127 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15128 },
15129 {
15130 .pme_name = "W_IN_BLOCKED_1@4",
15131 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 4)",
15132 .pme_code = 1060,
15133 .pme_flags = 0x0,
15134 .pme_numasks = 0,
15135 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15136 .pme_ctr = 13,
15137 .pme_event = 2,
15138 .pme_chipno = 4,
15139 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15140 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15141 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15142 },
15143 {
15144 .pme_name = "W_IN_BLOCKED_1@5",
15145 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 5)",
15146 .pme_code = 1061,
15147 .pme_flags = 0x0,
15148 .pme_numasks = 0,
15149 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15150 .pme_ctr = 13,
15151 .pme_event = 2,
15152 .pme_chipno = 5,
15153 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15154 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15155 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15156 },
15157 {
15158 .pme_name = "W_IN_BLOCKED_1@6",
15159 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 6)",
15160 .pme_code = 1062,
15161 .pme_flags = 0x0,
15162 .pme_numasks = 0,
15163 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15164 .pme_ctr = 13,
15165 .pme_event = 2,
15166 .pme_chipno = 6,
15167 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15168 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15169 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15170 },
15171 {
15172 .pme_name = "W_IN_BLOCKED_1@7",
15173 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 7)",
15174 .pme_code = 1063,
15175 .pme_flags = 0x0,
15176 .pme_numasks = 0,
15177 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15178 .pme_ctr = 13,
15179 .pme_event = 2,
15180 .pme_chipno = 7,
15181 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15182 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15183 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15184 },
15185 {
15186 .pme_name = "W_IN_BLOCKED_1@8",
15187 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 8)",
15188 .pme_code = 1064,
15189 .pme_flags = 0x0,
15190 .pme_numasks = 0,
15191 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15192 .pme_ctr = 13,
15193 .pme_event = 2,
15194 .pme_chipno = 8,
15195 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15196 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15197 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15198 },
15199 {
15200 .pme_name = "W_IN_BLOCKED_1@9",
15201 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 9)",
15202 .pme_code = 1065,
15203 .pme_flags = 0x0,
15204 .pme_numasks = 0,
15205 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15206 .pme_ctr = 13,
15207 .pme_event = 2,
15208 .pme_chipno = 9,
15209 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15210 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15211 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15212 },
15213 {
15214 .pme_name = "W_IN_BLOCKED_1@10",
15215 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 10)",
15216 .pme_code = 1066,
15217 .pme_flags = 0x0,
15218 .pme_numasks = 0,
15219 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15220 .pme_ctr = 13,
15221 .pme_event = 2,
15222 .pme_chipno = 10,
15223 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15224 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15225 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15226 },
15227 {
15228 .pme_name = "W_IN_BLOCKED_1@11",
15229 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 11)",
15230 .pme_code = 1067,
15231 .pme_flags = 0x0,
15232 .pme_numasks = 0,
15233 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15234 .pme_ctr = 13,
15235 .pme_event = 2,
15236 .pme_chipno = 11,
15237 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15238 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15239 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15240 },
15241 {
15242 .pme_name = "W_IN_BLOCKED_1@12",
15243 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 12)",
15244 .pme_code = 1068,
15245 .pme_flags = 0x0,
15246 .pme_numasks = 0,
15247 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15248 .pme_ctr = 13,
15249 .pme_event = 2,
15250 .pme_chipno = 12,
15251 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15252 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15253 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15254 },
15255 {
15256 .pme_name = "W_IN_BLOCKED_1@13",
15257 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 13)",
15258 .pme_code = 1069,
15259 .pme_flags = 0x0,
15260 .pme_numasks = 0,
15261 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15262 .pme_ctr = 13,
15263 .pme_event = 2,
15264 .pme_chipno = 13,
15265 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15266 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15267 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15268 },
15269 {
15270 .pme_name = "W_IN_BLOCKED_1@14",
15271 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 14)",
15272 .pme_code = 1070,
15273 .pme_flags = 0x0,
15274 .pme_numasks = 0,
15275 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15276 .pme_ctr = 13,
15277 .pme_event = 2,
15278 .pme_chipno = 14,
15279 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15280 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15281 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15282 },
15283 {
15284 .pme_name = "W_IN_BLOCKED_1@15",
15285 .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 15)",
15286 .pme_code = 1071,
15287 .pme_flags = 0x0,
15288 .pme_numasks = 0,
15289 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15290 .pme_ctr = 13,
15291 .pme_event = 2,
15292 .pme_chipno = 15,
15293 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15294 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15295 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15296 },
15297 /* M Counter 13 Event 3 */
15298 {
15299 .pme_name = "FLUSH_REQ_PACKETS@0",
15300 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 0)",
15301 .pme_code = 1072,
15302 .pme_flags = 0x0,
15303 .pme_numasks = 0,
15304 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15305 .pme_ctr = 13,
15306 .pme_event = 3,
15307 .pme_chipno = 0,
15308 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15309 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15310 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15311 },
15312 {
15313 .pme_name = "FLUSH_REQ_PACKETS@1",
15314 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 1)",
15315 .pme_code = 1073,
15316 .pme_flags = 0x0,
15317 .pme_numasks = 0,
15318 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15319 .pme_ctr = 13,
15320 .pme_event = 3,
15321 .pme_chipno = 1,
15322 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15323 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15324 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15325 },
15326 {
15327 .pme_name = "FLUSH_REQ_PACKETS@2",
15328 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 2)",
15329 .pme_code = 1074,
15330 .pme_flags = 0x0,
15331 .pme_numasks = 0,
15332 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15333 .pme_ctr = 13,
15334 .pme_event = 3,
15335 .pme_chipno = 2,
15336 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15337 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15338 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15339 },
15340 {
15341 .pme_name = "FLUSH_REQ_PACKETS@3",
15342 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 3)",
15343 .pme_code = 1075,
15344 .pme_flags = 0x0,
15345 .pme_numasks = 0,
15346 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15347 .pme_ctr = 13,
15348 .pme_event = 3,
15349 .pme_chipno = 3,
15350 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15351 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15352 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15353 },
15354 {
15355 .pme_name = "FLUSH_REQ_PACKETS@4",
15356 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 4)",
15357 .pme_code = 1076,
15358 .pme_flags = 0x0,
15359 .pme_numasks = 0,
15360 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15361 .pme_ctr = 13,
15362 .pme_event = 3,
15363 .pme_chipno = 4,
15364 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15365 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15366 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15367 },
15368 {
15369 .pme_name = "FLUSH_REQ_PACKETS@5",
15370 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 5)",
15371 .pme_code = 1077,
15372 .pme_flags = 0x0,
15373 .pme_numasks = 0,
15374 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15375 .pme_ctr = 13,
15376 .pme_event = 3,
15377 .pme_chipno = 5,
15378 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15379 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15380 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15381 },
15382 {
15383 .pme_name = "FLUSH_REQ_PACKETS@6",
15384 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 6)",
15385 .pme_code = 1078,
15386 .pme_flags = 0x0,
15387 .pme_numasks = 0,
15388 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15389 .pme_ctr = 13,
15390 .pme_event = 3,
15391 .pme_chipno = 6,
15392 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15393 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15394 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15395 },
15396 {
15397 .pme_name = "FLUSH_REQ_PACKETS@7",
15398 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 7)",
15399 .pme_code = 1079,
15400 .pme_flags = 0x0,
15401 .pme_numasks = 0,
15402 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15403 .pme_ctr = 13,
15404 .pme_event = 3,
15405 .pme_chipno = 7,
15406 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15407 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15408 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15409 },
15410 {
15411 .pme_name = "FLUSH_REQ_PACKETS@8",
15412 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 8)",
15413 .pme_code = 1080,
15414 .pme_flags = 0x0,
15415 .pme_numasks = 0,
15416 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15417 .pme_ctr = 13,
15418 .pme_event = 3,
15419 .pme_chipno = 8,
15420 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15421 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15422 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15423 },
15424 {
15425 .pme_name = "FLUSH_REQ_PACKETS@9",
15426 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 9)",
15427 .pme_code = 1081,
15428 .pme_flags = 0x0,
15429 .pme_numasks = 0,
15430 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15431 .pme_ctr = 13,
15432 .pme_event = 3,
15433 .pme_chipno = 9,
15434 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15435 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15436 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15437 },
15438 {
15439 .pme_name = "FLUSH_REQ_PACKETS@10",
15440 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 10)",
15441 .pme_code = 1082,
15442 .pme_flags = 0x0,
15443 .pme_numasks = 0,
15444 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15445 .pme_ctr = 13,
15446 .pme_event = 3,
15447 .pme_chipno = 10,
15448 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15449 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15450 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15451 },
15452 {
15453 .pme_name = "FLUSH_REQ_PACKETS@11",
15454 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 11)",
15455 .pme_code = 1083,
15456 .pme_flags = 0x0,
15457 .pme_numasks = 0,
15458 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15459 .pme_ctr = 13,
15460 .pme_event = 3,
15461 .pme_chipno = 11,
15462 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15463 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15464 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15465 },
15466 {
15467 .pme_name = "FLUSH_REQ_PACKETS@12",
15468 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 12)",
15469 .pme_code = 1084,
15470 .pme_flags = 0x0,
15471 .pme_numasks = 0,
15472 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15473 .pme_ctr = 13,
15474 .pme_event = 3,
15475 .pme_chipno = 12,
15476 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15477 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15478 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15479 },
15480 {
15481 .pme_name = "FLUSH_REQ_PACKETS@13",
15482 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 13)",
15483 .pme_code = 1085,
15484 .pme_flags = 0x0,
15485 .pme_numasks = 0,
15486 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15487 .pme_ctr = 13,
15488 .pme_event = 3,
15489 .pme_chipno = 13,
15490 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15491 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15492 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15493 },
15494 {
15495 .pme_name = "FLUSH_REQ_PACKETS@14",
15496 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 14)",
15497 .pme_code = 1086,
15498 .pme_flags = 0x0,
15499 .pme_numasks = 0,
15500 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15501 .pme_ctr = 13,
15502 .pme_event = 3,
15503 .pme_chipno = 14,
15504 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15505 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15506 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15507 },
15508 {
15509 .pme_name = "FLUSH_REQ_PACKETS@15",
15510 .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 15)",
15511 .pme_code = 1087,
15512 .pme_flags = 0x0,
15513 .pme_numasks = 0,
15514 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15515 .pme_ctr = 13,
15516 .pme_event = 3,
15517 .pme_chipno = 15,
15518 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15519 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15520 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15521 },
15522 /* M Counter 14 Event 0 */
15523 {
15524 .pme_name = "INVAL_EVENTS@0",
15525 .pme_desc = "Invalidation events (any number of sharers). (M chip 0)",
15526 .pme_code = 1088,
15527 .pme_flags = 0x0,
15528 .pme_numasks = 0,
15529 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15530 .pme_ctr = 14,
15531 .pme_event = 0,
15532 .pme_chipno = 0,
15533 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15534 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15535 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15536 },
15537 {
15538 .pme_name = "INVAL_EVENTS@1",
15539 .pme_desc = "Invalidation events (any number of sharers). (M chip 1)",
15540 .pme_code = 1089,
15541 .pme_flags = 0x0,
15542 .pme_numasks = 0,
15543 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15544 .pme_ctr = 14,
15545 .pme_event = 0,
15546 .pme_chipno = 1,
15547 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15548 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15549 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15550 },
15551 {
15552 .pme_name = "INVAL_EVENTS@2",
15553 .pme_desc = "Invalidation events (any number of sharers). (M chip 2)",
15554 .pme_code = 1090,
15555 .pme_flags = 0x0,
15556 .pme_numasks = 0,
15557 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15558 .pme_ctr = 14,
15559 .pme_event = 0,
15560 .pme_chipno = 2,
15561 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15562 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15563 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15564 },
15565 {
15566 .pme_name = "INVAL_EVENTS@3",
15567 .pme_desc = "Invalidation events (any number of sharers). (M chip 3)",
15568 .pme_code = 1091,
15569 .pme_flags = 0x0,
15570 .pme_numasks = 0,
15571 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15572 .pme_ctr = 14,
15573 .pme_event = 0,
15574 .pme_chipno = 3,
15575 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15576 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15577 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15578 },
15579 {
15580 .pme_name = "INVAL_EVENTS@4",
15581 .pme_desc = "Invalidation events (any number of sharers). (M chip 4)",
15582 .pme_code = 1092,
15583 .pme_flags = 0x0,
15584 .pme_numasks = 0,
15585 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15586 .pme_ctr = 14,
15587 .pme_event = 0,
15588 .pme_chipno = 4,
15589 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15590 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15591 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15592 },
15593 {
15594 .pme_name = "INVAL_EVENTS@5",
15595 .pme_desc = "Invalidation events (any number of sharers). (M chip 5)",
15596 .pme_code = 1093,
15597 .pme_flags = 0x0,
15598 .pme_numasks = 0,
15599 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15600 .pme_ctr = 14,
15601 .pme_event = 0,
15602 .pme_chipno = 5,
15603 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15604 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15605 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15606 },
15607 {
15608 .pme_name = "INVAL_EVENTS@6",
15609 .pme_desc = "Invalidation events (any number of sharers). (M chip 6)",
15610 .pme_code = 1094,
15611 .pme_flags = 0x0,
15612 .pme_numasks = 0,
15613 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15614 .pme_ctr = 14,
15615 .pme_event = 0,
15616 .pme_chipno = 6,
15617 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15618 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15619 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15620 },
15621 {
15622 .pme_name = "INVAL_EVENTS@7",
15623 .pme_desc = "Invalidation events (any number of sharers). (M chip 7)",
15624 .pme_code = 1095,
15625 .pme_flags = 0x0,
15626 .pme_numasks = 0,
15627 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15628 .pme_ctr = 14,
15629 .pme_event = 0,
15630 .pme_chipno = 7,
15631 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15632 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15633 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15634 },
15635 {
15636 .pme_name = "INVAL_EVENTS@8",
15637 .pme_desc = "Invalidation events (any number of sharers). (M chip 8)",
15638 .pme_code = 1096,
15639 .pme_flags = 0x0,
15640 .pme_numasks = 0,
15641 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15642 .pme_ctr = 14,
15643 .pme_event = 0,
15644 .pme_chipno = 8,
15645 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15646 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15647 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15648 },
15649 {
15650 .pme_name = "INVAL_EVENTS@9",
15651 .pme_desc = "Invalidation events (any number of sharers). (M chip 9)",
15652 .pme_code = 1097,
15653 .pme_flags = 0x0,
15654 .pme_numasks = 0,
15655 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15656 .pme_ctr = 14,
15657 .pme_event = 0,
15658 .pme_chipno = 9,
15659 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15660 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15661 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15662 },
15663 {
15664 .pme_name = "INVAL_EVENTS@10",
15665 .pme_desc = "Invalidation events (any number of sharers). (M chip 10)",
15666 .pme_code = 1098,
15667 .pme_flags = 0x0,
15668 .pme_numasks = 0,
15669 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15670 .pme_ctr = 14,
15671 .pme_event = 0,
15672 .pme_chipno = 10,
15673 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15674 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15675 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15676 },
15677 {
15678 .pme_name = "INVAL_EVENTS@11",
15679 .pme_desc = "Invalidation events (any number of sharers). (M chip 11)",
15680 .pme_code = 1099,
15681 .pme_flags = 0x0,
15682 .pme_numasks = 0,
15683 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15684 .pme_ctr = 14,
15685 .pme_event = 0,
15686 .pme_chipno = 11,
15687 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15688 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15689 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15690 },
15691 {
15692 .pme_name = "INVAL_EVENTS@12",
15693 .pme_desc = "Invalidation events (any number of sharers). (M chip 12)",
15694 .pme_code = 1100,
15695 .pme_flags = 0x0,
15696 .pme_numasks = 0,
15697 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15698 .pme_ctr = 14,
15699 .pme_event = 0,
15700 .pme_chipno = 12,
15701 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15702 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15703 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15704 },
15705 {
15706 .pme_name = "INVAL_EVENTS@13",
15707 .pme_desc = "Invalidation events (any number of sharers). (M chip 13)",
15708 .pme_code = 1101,
15709 .pme_flags = 0x0,
15710 .pme_numasks = 0,
15711 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15712 .pme_ctr = 14,
15713 .pme_event = 0,
15714 .pme_chipno = 13,
15715 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15716 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15717 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15718 },
15719 {
15720 .pme_name = "INVAL_EVENTS@14",
15721 .pme_desc = "Invalidation events (any number of sharers). (M chip 14)",
15722 .pme_code = 1102,
15723 .pme_flags = 0x0,
15724 .pme_numasks = 0,
15725 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15726 .pme_ctr = 14,
15727 .pme_event = 0,
15728 .pme_chipno = 14,
15729 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15730 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15731 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15732 },
15733 {
15734 .pme_name = "INVAL_EVENTS@15",
15735 .pme_desc = "Invalidation events (any number of sharers). (M chip 15)",
15736 .pme_code = 1103,
15737 .pme_flags = 0x0,
15738 .pme_numasks = 0,
15739 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15740 .pme_ctr = 14,
15741 .pme_event = 0,
15742 .pme_chipno = 15,
15743 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15744 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15745 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15746 },
15747 /* M Counter 14 Event 1 */
15748 {
15749 .pme_name = "L3_LINE_HIT_GLOBAL@0",
15750 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 0)",
15751 .pme_code = 1104,
15752 .pme_flags = 0x0,
15753 .pme_numasks = 0,
15754 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15755 .pme_ctr = 14,
15756 .pme_event = 1,
15757 .pme_chipno = 0,
15758 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15759 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15760 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15761 },
15762 {
15763 .pme_name = "L3_LINE_HIT_GLOBAL@1",
15764 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 1)",
15765 .pme_code = 1105,
15766 .pme_flags = 0x0,
15767 .pme_numasks = 0,
15768 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15769 .pme_ctr = 14,
15770 .pme_event = 1,
15771 .pme_chipno = 1,
15772 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15773 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15774 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15775 },
15776 {
15777 .pme_name = "L3_LINE_HIT_GLOBAL@2",
15778 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 2)",
15779 .pme_code = 1106,
15780 .pme_flags = 0x0,
15781 .pme_numasks = 0,
15782 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15783 .pme_ctr = 14,
15784 .pme_event = 1,
15785 .pme_chipno = 2,
15786 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15787 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15788 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15789 },
15790 {
15791 .pme_name = "L3_LINE_HIT_GLOBAL@3",
15792 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 3)",
15793 .pme_code = 1107,
15794 .pme_flags = 0x0,
15795 .pme_numasks = 0,
15796 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15797 .pme_ctr = 14,
15798 .pme_event = 1,
15799 .pme_chipno = 3,
15800 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15801 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15802 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15803 },
15804 {
15805 .pme_name = "L3_LINE_HIT_GLOBAL@4",
15806 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 4)",
15807 .pme_code = 1108,
15808 .pme_flags = 0x0,
15809 .pme_numasks = 0,
15810 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15811 .pme_ctr = 14,
15812 .pme_event = 1,
15813 .pme_chipno = 4,
15814 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15815 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15816 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15817 },
15818 {
15819 .pme_name = "L3_LINE_HIT_GLOBAL@5",
15820 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 5)",
15821 .pme_code = 1109,
15822 .pme_flags = 0x0,
15823 .pme_numasks = 0,
15824 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15825 .pme_ctr = 14,
15826 .pme_event = 1,
15827 .pme_chipno = 5,
15828 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15829 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15830 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15831 },
15832 {
15833 .pme_name = "L3_LINE_HIT_GLOBAL@6",
15834 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 6)",
15835 .pme_code = 1110,
15836 .pme_flags = 0x0,
15837 .pme_numasks = 0,
15838 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15839 .pme_ctr = 14,
15840 .pme_event = 1,
15841 .pme_chipno = 6,
15842 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15843 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15844 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15845 },
15846 {
15847 .pme_name = "L3_LINE_HIT_GLOBAL@7",
15848 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 7)",
15849 .pme_code = 1111,
15850 .pme_flags = 0x0,
15851 .pme_numasks = 0,
15852 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15853 .pme_ctr = 14,
15854 .pme_event = 1,
15855 .pme_chipno = 7,
15856 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15857 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15858 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15859 },
15860 {
15861 .pme_name = "L3_LINE_HIT_GLOBAL@8",
15862 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 8)",
15863 .pme_code = 1112,
15864 .pme_flags = 0x0,
15865 .pme_numasks = 0,
15866 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15867 .pme_ctr = 14,
15868 .pme_event = 1,
15869 .pme_chipno = 8,
15870 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15871 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15872 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15873 },
15874 {
15875 .pme_name = "L3_LINE_HIT_GLOBAL@9",
15876 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 9)",
15877 .pme_code = 1113,
15878 .pme_flags = 0x0,
15879 .pme_numasks = 0,
15880 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15881 .pme_ctr = 14,
15882 .pme_event = 1,
15883 .pme_chipno = 9,
15884 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15885 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15886 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15887 },
15888 {
15889 .pme_name = "L3_LINE_HIT_GLOBAL@10",
15890 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 10)",
15891 .pme_code = 1114,
15892 .pme_flags = 0x0,
15893 .pme_numasks = 0,
15894 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15895 .pme_ctr = 14,
15896 .pme_event = 1,
15897 .pme_chipno = 10,
15898 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15899 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15900 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15901 },
15902 {
15903 .pme_name = "L3_LINE_HIT_GLOBAL@11",
15904 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 11)",
15905 .pme_code = 1115,
15906 .pme_flags = 0x0,
15907 .pme_numasks = 0,
15908 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15909 .pme_ctr = 14,
15910 .pme_event = 1,
15911 .pme_chipno = 11,
15912 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15913 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15914 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15915 },
15916 {
15917 .pme_name = "L3_LINE_HIT_GLOBAL@12",
15918 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 12)",
15919 .pme_code = 1116,
15920 .pme_flags = 0x0,
15921 .pme_numasks = 0,
15922 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15923 .pme_ctr = 14,
15924 .pme_event = 1,
15925 .pme_chipno = 12,
15926 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15927 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15928 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15929 },
15930 {
15931 .pme_name = "L3_LINE_HIT_GLOBAL@13",
15932 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 13)",
15933 .pme_code = 1117,
15934 .pme_flags = 0x0,
15935 .pme_numasks = 0,
15936 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15937 .pme_ctr = 14,
15938 .pme_event = 1,
15939 .pme_chipno = 13,
15940 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15941 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15942 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15943 },
15944 {
15945 .pme_name = "L3_LINE_HIT_GLOBAL@14",
15946 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 14)",
15947 .pme_code = 1118,
15948 .pme_flags = 0x0,
15949 .pme_numasks = 0,
15950 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15951 .pme_ctr = 14,
15952 .pme_event = 1,
15953 .pme_chipno = 14,
15954 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15955 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15956 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15957 },
15958 {
15959 .pme_name = "L3_LINE_HIT_GLOBAL@15",
15960 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 15)",
15961 .pme_code = 1119,
15962 .pme_flags = 0x0,
15963 .pme_numasks = 0,
15964 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15965 .pme_ctr = 14,
15966 .pme_event = 1,
15967 .pme_chipno = 15,
15968 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15969 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15970 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15971 },
15972 /* M Counter 14 Event 2 */
15973 {
15974 .pme_name = "W_IN_BLOCKED_2@0",
15975 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 0)",
15976 .pme_code = 1120,
15977 .pme_flags = 0x0,
15978 .pme_numasks = 0,
15979 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15980 .pme_ctr = 14,
15981 .pme_event = 2,
15982 .pme_chipno = 0,
15983 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15984 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15985 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
15986 },
15987 {
15988 .pme_name = "W_IN_BLOCKED_2@1",
15989 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 1)",
15990 .pme_code = 1121,
15991 .pme_flags = 0x0,
15992 .pme_numasks = 0,
15993 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
15994 .pme_ctr = 14,
15995 .pme_event = 2,
15996 .pme_chipno = 1,
15997 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
15998 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
15999 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16000 },
16001 {
16002 .pme_name = "W_IN_BLOCKED_2@2",
16003 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 2)",
16004 .pme_code = 1122,
16005 .pme_flags = 0x0,
16006 .pme_numasks = 0,
16007 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16008 .pme_ctr = 14,
16009 .pme_event = 2,
16010 .pme_chipno = 2,
16011 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16012 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16013 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16014 },
16015 {
16016 .pme_name = "W_IN_BLOCKED_2@3",
16017 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 3)",
16018 .pme_code = 1123,
16019 .pme_flags = 0x0,
16020 .pme_numasks = 0,
16021 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16022 .pme_ctr = 14,
16023 .pme_event = 2,
16024 .pme_chipno = 3,
16025 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16026 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16027 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16028 },
16029 {
16030 .pme_name = "W_IN_BLOCKED_2@4",
16031 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 4)",
16032 .pme_code = 1124,
16033 .pme_flags = 0x0,
16034 .pme_numasks = 0,
16035 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16036 .pme_ctr = 14,
16037 .pme_event = 2,
16038 .pme_chipno = 4,
16039 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16040 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16041 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16042 },
16043 {
16044 .pme_name = "W_IN_BLOCKED_2@5",
16045 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 5)",
16046 .pme_code = 1125,
16047 .pme_flags = 0x0,
16048 .pme_numasks = 0,
16049 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16050 .pme_ctr = 14,
16051 .pme_event = 2,
16052 .pme_chipno = 5,
16053 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16054 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16055 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16056 },
16057 {
16058 .pme_name = "W_IN_BLOCKED_2@6",
16059 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 6)",
16060 .pme_code = 1126,
16061 .pme_flags = 0x0,
16062 .pme_numasks = 0,
16063 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16064 .pme_ctr = 14,
16065 .pme_event = 2,
16066 .pme_chipno = 6,
16067 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16068 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16069 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16070 },
16071 {
16072 .pme_name = "W_IN_BLOCKED_2@7",
16073 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 7)",
16074 .pme_code = 1127,
16075 .pme_flags = 0x0,
16076 .pme_numasks = 0,
16077 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16078 .pme_ctr = 14,
16079 .pme_event = 2,
16080 .pme_chipno = 7,
16081 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16082 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16083 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16084 },
16085 {
16086 .pme_name = "W_IN_BLOCKED_2@8",
16087 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 8)",
16088 .pme_code = 1128,
16089 .pme_flags = 0x0,
16090 .pme_numasks = 0,
16091 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16092 .pme_ctr = 14,
16093 .pme_event = 2,
16094 .pme_chipno = 8,
16095 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16096 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16097 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16098 },
16099 {
16100 .pme_name = "W_IN_BLOCKED_2@9",
16101 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 9)",
16102 .pme_code = 1129,
16103 .pme_flags = 0x0,
16104 .pme_numasks = 0,
16105 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16106 .pme_ctr = 14,
16107 .pme_event = 2,
16108 .pme_chipno = 9,
16109 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16110 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16111 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16112 },
16113 {
16114 .pme_name = "W_IN_BLOCKED_2@10",
16115 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 10)",
16116 .pme_code = 1130,
16117 .pme_flags = 0x0,
16118 .pme_numasks = 0,
16119 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16120 .pme_ctr = 14,
16121 .pme_event = 2,
16122 .pme_chipno = 10,
16123 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16124 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16125 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16126 },
16127 {
16128 .pme_name = "W_IN_BLOCKED_2@11",
16129 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 11)",
16130 .pme_code = 1131,
16131 .pme_flags = 0x0,
16132 .pme_numasks = 0,
16133 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16134 .pme_ctr = 14,
16135 .pme_event = 2,
16136 .pme_chipno = 11,
16137 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16138 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16139 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16140 },
16141 {
16142 .pme_name = "W_IN_BLOCKED_2@12",
16143 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 12)",
16144 .pme_code = 1132,
16145 .pme_flags = 0x0,
16146 .pme_numasks = 0,
16147 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16148 .pme_ctr = 14,
16149 .pme_event = 2,
16150 .pme_chipno = 12,
16151 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16152 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16153 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16154 },
16155 {
16156 .pme_name = "W_IN_BLOCKED_2@13",
16157 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 13)",
16158 .pme_code = 1133,
16159 .pme_flags = 0x0,
16160 .pme_numasks = 0,
16161 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16162 .pme_ctr = 14,
16163 .pme_event = 2,
16164 .pme_chipno = 13,
16165 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16166 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16167 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16168 },
16169 {
16170 .pme_name = "W_IN_BLOCKED_2@14",
16171 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 14)",
16172 .pme_code = 1134,
16173 .pme_flags = 0x0,
16174 .pme_numasks = 0,
16175 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16176 .pme_ctr = 14,
16177 .pme_event = 2,
16178 .pme_chipno = 14,
16179 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16180 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16181 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16182 },
16183 {
16184 .pme_name = "W_IN_BLOCKED_2@15",
16185 .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 15)",
16186 .pme_code = 1135,
16187 .pme_flags = 0x0,
16188 .pme_numasks = 0,
16189 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16190 .pme_ctr = 14,
16191 .pme_event = 2,
16192 .pme_chipno = 15,
16193 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16194 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16195 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16196 },
16197 /* M Counter 14 Event 3 */
16198 {
16199 .pme_name = "W_OUT_BLOCK_CRED_2@0",
16200 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 0)",
16201 .pme_code = 1136,
16202 .pme_flags = 0x0,
16203 .pme_numasks = 0,
16204 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16205 .pme_ctr = 14,
16206 .pme_event = 3,
16207 .pme_chipno = 0,
16208 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16209 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16210 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16211 },
16212 {
16213 .pme_name = "W_OUT_BLOCK_CRED_2@1",
16214 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 1)",
16215 .pme_code = 1137,
16216 .pme_flags = 0x0,
16217 .pme_numasks = 0,
16218 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16219 .pme_ctr = 14,
16220 .pme_event = 3,
16221 .pme_chipno = 1,
16222 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16223 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16224 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16225 },
16226 {
16227 .pme_name = "W_OUT_BLOCK_CRED_2@2",
16228 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 2)",
16229 .pme_code = 1138,
16230 .pme_flags = 0x0,
16231 .pme_numasks = 0,
16232 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16233 .pme_ctr = 14,
16234 .pme_event = 3,
16235 .pme_chipno = 2,
16236 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16237 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16238 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16239 },
16240 {
16241 .pme_name = "W_OUT_BLOCK_CRED_2@3",
16242 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 3)",
16243 .pme_code = 1139,
16244 .pme_flags = 0x0,
16245 .pme_numasks = 0,
16246 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16247 .pme_ctr = 14,
16248 .pme_event = 3,
16249 .pme_chipno = 3,
16250 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16251 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16252 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16253 },
16254 {
16255 .pme_name = "W_OUT_BLOCK_CRED_2@4",
16256 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 4)",
16257 .pme_code = 1140,
16258 .pme_flags = 0x0,
16259 .pme_numasks = 0,
16260 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16261 .pme_ctr = 14,
16262 .pme_event = 3,
16263 .pme_chipno = 4,
16264 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16265 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16266 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16267 },
16268 {
16269 .pme_name = "W_OUT_BLOCK_CRED_2@5",
16270 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 5)",
16271 .pme_code = 1141,
16272 .pme_flags = 0x0,
16273 .pme_numasks = 0,
16274 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16275 .pme_ctr = 14,
16276 .pme_event = 3,
16277 .pme_chipno = 5,
16278 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16279 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16280 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16281 },
16282 {
16283 .pme_name = "W_OUT_BLOCK_CRED_2@6",
16284 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 6)",
16285 .pme_code = 1142,
16286 .pme_flags = 0x0,
16287 .pme_numasks = 0,
16288 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16289 .pme_ctr = 14,
16290 .pme_event = 3,
16291 .pme_chipno = 6,
16292 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16293 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16294 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16295 },
16296 {
16297 .pme_name = "W_OUT_BLOCK_CRED_2@7",
16298 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 7)",
16299 .pme_code = 1143,
16300 .pme_flags = 0x0,
16301 .pme_numasks = 0,
16302 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16303 .pme_ctr = 14,
16304 .pme_event = 3,
16305 .pme_chipno = 7,
16306 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16307 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16308 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16309 },
16310 {
16311 .pme_name = "W_OUT_BLOCK_CRED_2@8",
16312 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 8)",
16313 .pme_code = 1144,
16314 .pme_flags = 0x0,
16315 .pme_numasks = 0,
16316 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16317 .pme_ctr = 14,
16318 .pme_event = 3,
16319 .pme_chipno = 8,
16320 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16321 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16322 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16323 },
16324 {
16325 .pme_name = "W_OUT_BLOCK_CRED_2@9",
16326 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 9)",
16327 .pme_code = 1145,
16328 .pme_flags = 0x0,
16329 .pme_numasks = 0,
16330 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16331 .pme_ctr = 14,
16332 .pme_event = 3,
16333 .pme_chipno = 9,
16334 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16335 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16336 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16337 },
16338 {
16339 .pme_name = "W_OUT_BLOCK_CRED_2@10",
16340 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 10)",
16341 .pme_code = 1146,
16342 .pme_flags = 0x0,
16343 .pme_numasks = 0,
16344 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16345 .pme_ctr = 14,
16346 .pme_event = 3,
16347 .pme_chipno = 10,
16348 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16349 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16350 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16351 },
16352 {
16353 .pme_name = "W_OUT_BLOCK_CRED_2@11",
16354 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 11)",
16355 .pme_code = 1147,
16356 .pme_flags = 0x0,
16357 .pme_numasks = 0,
16358 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16359 .pme_ctr = 14,
16360 .pme_event = 3,
16361 .pme_chipno = 11,
16362 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16363 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16364 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16365 },
16366 {
16367 .pme_name = "W_OUT_BLOCK_CRED_2@12",
16368 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 12)",
16369 .pme_code = 1148,
16370 .pme_flags = 0x0,
16371 .pme_numasks = 0,
16372 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16373 .pme_ctr = 14,
16374 .pme_event = 3,
16375 .pme_chipno = 12,
16376 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16377 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16378 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16379 },
16380 {
16381 .pme_name = "W_OUT_BLOCK_CRED_2@13",
16382 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 13)",
16383 .pme_code = 1149,
16384 .pme_flags = 0x0,
16385 .pme_numasks = 0,
16386 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16387 .pme_ctr = 14,
16388 .pme_event = 3,
16389 .pme_chipno = 13,
16390 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16391 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16392 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16393 },
16394 {
16395 .pme_name = "W_OUT_BLOCK_CRED_2@14",
16396 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 14)",
16397 .pme_code = 1150,
16398 .pme_flags = 0x0,
16399 .pme_numasks = 0,
16400 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16401 .pme_ctr = 14,
16402 .pme_event = 3,
16403 .pme_chipno = 14,
16404 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16405 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16406 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16407 },
16408 {
16409 .pme_name = "W_OUT_BLOCK_CRED_2@15",
16410 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 15)",
16411 .pme_code = 1151,
16412 .pme_flags = 0x0,
16413 .pme_numasks = 0,
16414 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16415 .pme_ctr = 14,
16416 .pme_event = 3,
16417 .pme_chipno = 15,
16418 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16419 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16420 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16421 },
16422 /* M Counter 15 Event 0 */
16423 {
16424 .pme_name = "REQUEST_ALLOC_NO_FILL@0",
16425 .pme_desc = "Allocating no fill requests. (M chip 0)",
16426 .pme_code = 1152,
16427 .pme_flags = 0x0,
16428 .pme_numasks = 0,
16429 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16430 .pme_ctr = 15,
16431 .pme_event = 0,
16432 .pme_chipno = 0,
16433 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16434 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16435 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16436 },
16437 {
16438 .pme_name = "REQUEST_ALLOC_NO_FILL@1",
16439 .pme_desc = "Allocating no fill requests. (M chip 1)",
16440 .pme_code = 1153,
16441 .pme_flags = 0x0,
16442 .pme_numasks = 0,
16443 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16444 .pme_ctr = 15,
16445 .pme_event = 0,
16446 .pme_chipno = 1,
16447 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16448 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16449 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16450 },
16451 {
16452 .pme_name = "REQUEST_ALLOC_NO_FILL@2",
16453 .pme_desc = "Allocating no fill requests. (M chip 2)",
16454 .pme_code = 1154,
16455 .pme_flags = 0x0,
16456 .pme_numasks = 0,
16457 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16458 .pme_ctr = 15,
16459 .pme_event = 0,
16460 .pme_chipno = 2,
16461 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16462 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16463 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16464 },
16465 {
16466 .pme_name = "REQUEST_ALLOC_NO_FILL@3",
16467 .pme_desc = "Allocating no fill requests. (M chip 3)",
16468 .pme_code = 1155,
16469 .pme_flags = 0x0,
16470 .pme_numasks = 0,
16471 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16472 .pme_ctr = 15,
16473 .pme_event = 0,
16474 .pme_chipno = 3,
16475 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16476 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16477 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16478 },
16479 {
16480 .pme_name = "REQUEST_ALLOC_NO_FILL@4",
16481 .pme_desc = "Allocating no fill requests. (M chip 4)",
16482 .pme_code = 1156,
16483 .pme_flags = 0x0,
16484 .pme_numasks = 0,
16485 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16486 .pme_ctr = 15,
16487 .pme_event = 0,
16488 .pme_chipno = 4,
16489 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16490 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16491 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16492 },
16493 {
16494 .pme_name = "REQUEST_ALLOC_NO_FILL@5",
16495 .pme_desc = "Allocating no fill requests. (M chip 5)",
16496 .pme_code = 1157,
16497 .pme_flags = 0x0,
16498 .pme_numasks = 0,
16499 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16500 .pme_ctr = 15,
16501 .pme_event = 0,
16502 .pme_chipno = 5,
16503 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16504 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16505 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16506 },
16507 {
16508 .pme_name = "REQUEST_ALLOC_NO_FILL@6",
16509 .pme_desc = "Allocating no fill requests. (M chip 6)",
16510 .pme_code = 1158,
16511 .pme_flags = 0x0,
16512 .pme_numasks = 0,
16513 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16514 .pme_ctr = 15,
16515 .pme_event = 0,
16516 .pme_chipno = 6,
16517 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16518 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16519 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16520 },
16521 {
16522 .pme_name = "REQUEST_ALLOC_NO_FILL@7",
16523 .pme_desc = "Allocating no fill requests. (M chip 7)",
16524 .pme_code = 1159,
16525 .pme_flags = 0x0,
16526 .pme_numasks = 0,
16527 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16528 .pme_ctr = 15,
16529 .pme_event = 0,
16530 .pme_chipno = 7,
16531 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16532 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16533 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16534 },
16535 {
16536 .pme_name = "REQUEST_ALLOC_NO_FILL@8",
16537 .pme_desc = "Allocating no fill requests. (M chip 8)",
16538 .pme_code = 1160,
16539 .pme_flags = 0x0,
16540 .pme_numasks = 0,
16541 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16542 .pme_ctr = 15,
16543 .pme_event = 0,
16544 .pme_chipno = 8,
16545 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16546 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16547 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16548 },
16549 {
16550 .pme_name = "REQUEST_ALLOC_NO_FILL@9",
16551 .pme_desc = "Allocating no fill requests. (M chip 9)",
16552 .pme_code = 1161,
16553 .pme_flags = 0x0,
16554 .pme_numasks = 0,
16555 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16556 .pme_ctr = 15,
16557 .pme_event = 0,
16558 .pme_chipno = 9,
16559 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16560 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16561 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16562 },
16563 {
16564 .pme_name = "REQUEST_ALLOC_NO_FILL@10",
16565 .pme_desc = "Allocating no fill requests. (M chip 10)",
16566 .pme_code = 1162,
16567 .pme_flags = 0x0,
16568 .pme_numasks = 0,
16569 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16570 .pme_ctr = 15,
16571 .pme_event = 0,
16572 .pme_chipno = 10,
16573 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16574 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16575 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16576 },
16577 {
16578 .pme_name = "REQUEST_ALLOC_NO_FILL@11",
16579 .pme_desc = "Allocating no fill requests. (M chip 11)",
16580 .pme_code = 1163,
16581 .pme_flags = 0x0,
16582 .pme_numasks = 0,
16583 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16584 .pme_ctr = 15,
16585 .pme_event = 0,
16586 .pme_chipno = 11,
16587 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16588 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16589 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16590 },
16591 {
16592 .pme_name = "REQUEST_ALLOC_NO_FILL@12",
16593 .pme_desc = "Allocating no fill requests. (M chip 12)",
16594 .pme_code = 1164,
16595 .pme_flags = 0x0,
16596 .pme_numasks = 0,
16597 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16598 .pme_ctr = 15,
16599 .pme_event = 0,
16600 .pme_chipno = 12,
16601 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16602 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16603 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16604 },
16605 {
16606 .pme_name = "REQUEST_ALLOC_NO_FILL@13",
16607 .pme_desc = "Allocating no fill requests. (M chip 13)",
16608 .pme_code = 1165,
16609 .pme_flags = 0x0,
16610 .pme_numasks = 0,
16611 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16612 .pme_ctr = 15,
16613 .pme_event = 0,
16614 .pme_chipno = 13,
16615 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16616 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16617 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16618 },
16619 {
16620 .pme_name = "REQUEST_ALLOC_NO_FILL@14",
16621 .pme_desc = "Allocating no fill requests. (M chip 14)",
16622 .pme_code = 1166,
16623 .pme_flags = 0x0,
16624 .pme_numasks = 0,
16625 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16626 .pme_ctr = 15,
16627 .pme_event = 0,
16628 .pme_chipno = 14,
16629 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16630 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16631 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16632 },
16633 {
16634 .pme_name = "REQUEST_ALLOC_NO_FILL@15",
16635 .pme_desc = "Allocating no fill requests. (M chip 15)",
16636 .pme_code = 1167,
16637 .pme_flags = 0x0,
16638 .pme_numasks = 0,
16639 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16640 .pme_ctr = 15,
16641 .pme_event = 0,
16642 .pme_chipno = 15,
16643 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16644 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16645 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16646 },
16647 /* M Counter 15 Event 1 */
16648 {
16649 .pme_name = "L3_LINE_HIT_SHARED@0",
16650 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 0)",
16651 .pme_code = 1168,
16652 .pme_flags = 0x0,
16653 .pme_numasks = 0,
16654 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16655 .pme_ctr = 15,
16656 .pme_event = 1,
16657 .pme_chipno = 0,
16658 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16659 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16660 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16661 },
16662 {
16663 .pme_name = "L3_LINE_HIT_SHARED@1",
16664 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 1)",
16665 .pme_code = 1169,
16666 .pme_flags = 0x0,
16667 .pme_numasks = 0,
16668 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16669 .pme_ctr = 15,
16670 .pme_event = 1,
16671 .pme_chipno = 1,
16672 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16673 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16674 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16675 },
16676 {
16677 .pme_name = "L3_LINE_HIT_SHARED@2",
16678 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 2)",
16679 .pme_code = 1170,
16680 .pme_flags = 0x0,
16681 .pme_numasks = 0,
16682 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16683 .pme_ctr = 15,
16684 .pme_event = 1,
16685 .pme_chipno = 2,
16686 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16687 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16688 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16689 },
16690 {
16691 .pme_name = "L3_LINE_HIT_SHARED@3",
16692 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 3)",
16693 .pme_code = 1171,
16694 .pme_flags = 0x0,
16695 .pme_numasks = 0,
16696 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16697 .pme_ctr = 15,
16698 .pme_event = 1,
16699 .pme_chipno = 3,
16700 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16701 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16702 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16703 },
16704 {
16705 .pme_name = "L3_LINE_HIT_SHARED@4",
16706 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 4)",
16707 .pme_code = 1172,
16708 .pme_flags = 0x0,
16709 .pme_numasks = 0,
16710 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16711 .pme_ctr = 15,
16712 .pme_event = 1,
16713 .pme_chipno = 4,
16714 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16715 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16716 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16717 },
16718 {
16719 .pme_name = "L3_LINE_HIT_SHARED@5",
16720 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 5)",
16721 .pme_code = 1173,
16722 .pme_flags = 0x0,
16723 .pme_numasks = 0,
16724 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16725 .pme_ctr = 15,
16726 .pme_event = 1,
16727 .pme_chipno = 5,
16728 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16729 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16730 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16731 },
16732 {
16733 .pme_name = "L3_LINE_HIT_SHARED@6",
16734 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 6)",
16735 .pme_code = 1174,
16736 .pme_flags = 0x0,
16737 .pme_numasks = 0,
16738 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16739 .pme_ctr = 15,
16740 .pme_event = 1,
16741 .pme_chipno = 6,
16742 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16743 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16744 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16745 },
16746 {
16747 .pme_name = "L3_LINE_HIT_SHARED@7",
16748 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 7)",
16749 .pme_code = 1175,
16750 .pme_flags = 0x0,
16751 .pme_numasks = 0,
16752 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16753 .pme_ctr = 15,
16754 .pme_event = 1,
16755 .pme_chipno = 7,
16756 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16757 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16758 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16759 },
16760 {
16761 .pme_name = "L3_LINE_HIT_SHARED@8",
16762 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 8)",
16763 .pme_code = 1176,
16764 .pme_flags = 0x0,
16765 .pme_numasks = 0,
16766 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16767 .pme_ctr = 15,
16768 .pme_event = 1,
16769 .pme_chipno = 8,
16770 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16771 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16772 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16773 },
16774 {
16775 .pme_name = "L3_LINE_HIT_SHARED@9",
16776 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 9)",
16777 .pme_code = 1177,
16778 .pme_flags = 0x0,
16779 .pme_numasks = 0,
16780 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16781 .pme_ctr = 15,
16782 .pme_event = 1,
16783 .pme_chipno = 9,
16784 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16785 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16786 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16787 },
16788 {
16789 .pme_name = "L3_LINE_HIT_SHARED@10",
16790 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 10)",
16791 .pme_code = 1178,
16792 .pme_flags = 0x0,
16793 .pme_numasks = 0,
16794 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16795 .pme_ctr = 15,
16796 .pme_event = 1,
16797 .pme_chipno = 10,
16798 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16799 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16800 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16801 },
16802 {
16803 .pme_name = "L3_LINE_HIT_SHARED@11",
16804 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 11)",
16805 .pme_code = 1179,
16806 .pme_flags = 0x0,
16807 .pme_numasks = 0,
16808 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16809 .pme_ctr = 15,
16810 .pme_event = 1,
16811 .pme_chipno = 11,
16812 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16813 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16814 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16815 },
16816 {
16817 .pme_name = "L3_LINE_HIT_SHARED@12",
16818 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 12)",
16819 .pme_code = 1180,
16820 .pme_flags = 0x0,
16821 .pme_numasks = 0,
16822 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16823 .pme_ctr = 15,
16824 .pme_event = 1,
16825 .pme_chipno = 12,
16826 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16827 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16828 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16829 },
16830 {
16831 .pme_name = "L3_LINE_HIT_SHARED@13",
16832 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 13)",
16833 .pme_code = 1181,
16834 .pme_flags = 0x0,
16835 .pme_numasks = 0,
16836 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16837 .pme_ctr = 15,
16838 .pme_event = 1,
16839 .pme_chipno = 13,
16840 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16841 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16842 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16843 },
16844 {
16845 .pme_name = "L3_LINE_HIT_SHARED@14",
16846 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 14)",
16847 .pme_code = 1182,
16848 .pme_flags = 0x0,
16849 .pme_numasks = 0,
16850 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16851 .pme_ctr = 15,
16852 .pme_event = 1,
16853 .pme_chipno = 14,
16854 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16855 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16856 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16857 },
16858 {
16859 .pme_name = "L3_LINE_HIT_SHARED@15",
16860 .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 15)",
16861 .pme_code = 1183,
16862 .pme_flags = 0x0,
16863 .pme_numasks = 0,
16864 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16865 .pme_ctr = 15,
16866 .pme_event = 1,
16867 .pme_chipno = 15,
16868 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16869 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16870 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16871 },
16872 /* M Counter 15 Event 2 */
16873 {
16874 .pme_name = "W_IN_BLOCKED_3@0",
16875 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 0)",
16876 .pme_code = 1184,
16877 .pme_flags = 0x0,
16878 .pme_numasks = 0,
16879 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16880 .pme_ctr = 15,
16881 .pme_event = 2,
16882 .pme_chipno = 0,
16883 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16884 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16885 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16886 },
16887 {
16888 .pme_name = "W_IN_BLOCKED_3@1",
16889 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 1)",
16890 .pme_code = 1185,
16891 .pme_flags = 0x0,
16892 .pme_numasks = 0,
16893 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16894 .pme_ctr = 15,
16895 .pme_event = 2,
16896 .pme_chipno = 1,
16897 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16898 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16899 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16900 },
16901 {
16902 .pme_name = "W_IN_BLOCKED_3@2",
16903 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 2)",
16904 .pme_code = 1186,
16905 .pme_flags = 0x0,
16906 .pme_numasks = 0,
16907 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16908 .pme_ctr = 15,
16909 .pme_event = 2,
16910 .pme_chipno = 2,
16911 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16912 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16913 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16914 },
16915 {
16916 .pme_name = "W_IN_BLOCKED_3@3",
16917 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 3)",
16918 .pme_code = 1187,
16919 .pme_flags = 0x0,
16920 .pme_numasks = 0,
16921 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16922 .pme_ctr = 15,
16923 .pme_event = 2,
16924 .pme_chipno = 3,
16925 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16926 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16927 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16928 },
16929 {
16930 .pme_name = "W_IN_BLOCKED_3@4",
16931 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 4)",
16932 .pme_code = 1188,
16933 .pme_flags = 0x0,
16934 .pme_numasks = 0,
16935 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16936 .pme_ctr = 15,
16937 .pme_event = 2,
16938 .pme_chipno = 4,
16939 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16940 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16941 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16942 },
16943 {
16944 .pme_name = "W_IN_BLOCKED_3@5",
16945 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 5)",
16946 .pme_code = 1189,
16947 .pme_flags = 0x0,
16948 .pme_numasks = 0,
16949 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16950 .pme_ctr = 15,
16951 .pme_event = 2,
16952 .pme_chipno = 5,
16953 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16954 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16955 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16956 },
16957 {
16958 .pme_name = "W_IN_BLOCKED_3@6",
16959 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 6)",
16960 .pme_code = 1190,
16961 .pme_flags = 0x0,
16962 .pme_numasks = 0,
16963 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16964 .pme_ctr = 15,
16965 .pme_event = 2,
16966 .pme_chipno = 6,
16967 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16968 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16969 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16970 },
16971 {
16972 .pme_name = "W_IN_BLOCKED_3@7",
16973 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 7)",
16974 .pme_code = 1191,
16975 .pme_flags = 0x0,
16976 .pme_numasks = 0,
16977 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16978 .pme_ctr = 15,
16979 .pme_event = 2,
16980 .pme_chipno = 7,
16981 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16982 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16983 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16984 },
16985 {
16986 .pme_name = "W_IN_BLOCKED_3@8",
16987 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 8)",
16988 .pme_code = 1192,
16989 .pme_flags = 0x0,
16990 .pme_numasks = 0,
16991 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
16992 .pme_ctr = 15,
16993 .pme_event = 2,
16994 .pme_chipno = 8,
16995 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
16996 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
16997 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
16998 },
16999 {
17000 .pme_name = "W_IN_BLOCKED_3@9",
17001 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 9)",
17002 .pme_code = 1193,
17003 .pme_flags = 0x0,
17004 .pme_numasks = 0,
17005 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17006 .pme_ctr = 15,
17007 .pme_event = 2,
17008 .pme_chipno = 9,
17009 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17010 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17011 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17012 },
17013 {
17014 .pme_name = "W_IN_BLOCKED_3@10",
17015 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 10)",
17016 .pme_code = 1194,
17017 .pme_flags = 0x0,
17018 .pme_numasks = 0,
17019 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17020 .pme_ctr = 15,
17021 .pme_event = 2,
17022 .pme_chipno = 10,
17023 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17024 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17025 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17026 },
17027 {
17028 .pme_name = "W_IN_BLOCKED_3@11",
17029 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 11)",
17030 .pme_code = 1195,
17031 .pme_flags = 0x0,
17032 .pme_numasks = 0,
17033 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17034 .pme_ctr = 15,
17035 .pme_event = 2,
17036 .pme_chipno = 11,
17037 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17038 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17039 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17040 },
17041 {
17042 .pme_name = "W_IN_BLOCKED_3@12",
17043 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 12)",
17044 .pme_code = 1196,
17045 .pme_flags = 0x0,
17046 .pme_numasks = 0,
17047 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17048 .pme_ctr = 15,
17049 .pme_event = 2,
17050 .pme_chipno = 12,
17051 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17052 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17053 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17054 },
17055 {
17056 .pme_name = "W_IN_BLOCKED_3@13",
17057 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 13)",
17058 .pme_code = 1197,
17059 .pme_flags = 0x0,
17060 .pme_numasks = 0,
17061 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17062 .pme_ctr = 15,
17063 .pme_event = 2,
17064 .pme_chipno = 13,
17065 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17066 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17067 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17068 },
17069 {
17070 .pme_name = "W_IN_BLOCKED_3@14",
17071 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 14)",
17072 .pme_code = 1198,
17073 .pme_flags = 0x0,
17074 .pme_numasks = 0,
17075 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17076 .pme_ctr = 15,
17077 .pme_event = 2,
17078 .pme_chipno = 14,
17079 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17080 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17081 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17082 },
17083 {
17084 .pme_name = "W_IN_BLOCKED_3@15",
17085 .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 15)",
17086 .pme_code = 1199,
17087 .pme_flags = 0x0,
17088 .pme_numasks = 0,
17089 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17090 .pme_ctr = 15,
17091 .pme_event = 2,
17092 .pme_chipno = 15,
17093 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17094 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17095 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17096 },
17097 /* M Counter 15 Event 3 */
17098 {
17099 .pme_name = "W_OUT_BLOCK_CRED_3@0",
17100 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 0)",
17101 .pme_code = 1200,
17102 .pme_flags = 0x0,
17103 .pme_numasks = 0,
17104 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17105 .pme_ctr = 15,
17106 .pme_event = 3,
17107 .pme_chipno = 0,
17108 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17109 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17110 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17111 },
17112 {
17113 .pme_name = "W_OUT_BLOCK_CRED_3@1",
17114 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 1)",
17115 .pme_code = 1201,
17116 .pme_flags = 0x0,
17117 .pme_numasks = 0,
17118 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17119 .pme_ctr = 15,
17120 .pme_event = 3,
17121 .pme_chipno = 1,
17122 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17123 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17124 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17125 },
17126 {
17127 .pme_name = "W_OUT_BLOCK_CRED_3@2",
17128 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 2)",
17129 .pme_code = 1202,
17130 .pme_flags = 0x0,
17131 .pme_numasks = 0,
17132 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17133 .pme_ctr = 15,
17134 .pme_event = 3,
17135 .pme_chipno = 2,
17136 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17137 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17138 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17139 },
17140 {
17141 .pme_name = "W_OUT_BLOCK_CRED_3@3",
17142 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 3)",
17143 .pme_code = 1203,
17144 .pme_flags = 0x0,
17145 .pme_numasks = 0,
17146 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17147 .pme_ctr = 15,
17148 .pme_event = 3,
17149 .pme_chipno = 3,
17150 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17151 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17152 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17153 },
17154 {
17155 .pme_name = "W_OUT_BLOCK_CRED_3@4",
17156 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 4)",
17157 .pme_code = 1204,
17158 .pme_flags = 0x0,
17159 .pme_numasks = 0,
17160 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17161 .pme_ctr = 15,
17162 .pme_event = 3,
17163 .pme_chipno = 4,
17164 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17165 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17166 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17167 },
17168 {
17169 .pme_name = "W_OUT_BLOCK_CRED_3@5",
17170 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 5)",
17171 .pme_code = 1205,
17172 .pme_flags = 0x0,
17173 .pme_numasks = 0,
17174 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17175 .pme_ctr = 15,
17176 .pme_event = 3,
17177 .pme_chipno = 5,
17178 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17179 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17180 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17181 },
17182 {
17183 .pme_name = "W_OUT_BLOCK_CRED_3@6",
17184 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 6)",
17185 .pme_code = 1206,
17186 .pme_flags = 0x0,
17187 .pme_numasks = 0,
17188 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17189 .pme_ctr = 15,
17190 .pme_event = 3,
17191 .pme_chipno = 6,
17192 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17193 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17194 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17195 },
17196 {
17197 .pme_name = "W_OUT_BLOCK_CRED_3@7",
17198 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 7)",
17199 .pme_code = 1207,
17200 .pme_flags = 0x0,
17201 .pme_numasks = 0,
17202 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17203 .pme_ctr = 15,
17204 .pme_event = 3,
17205 .pme_chipno = 7,
17206 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17207 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17208 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17209 },
17210 {
17211 .pme_name = "W_OUT_BLOCK_CRED_3@8",
17212 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 8)",
17213 .pme_code = 1208,
17214 .pme_flags = 0x0,
17215 .pme_numasks = 0,
17216 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17217 .pme_ctr = 15,
17218 .pme_event = 3,
17219 .pme_chipno = 8,
17220 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17221 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17222 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17223 },
17224 {
17225 .pme_name = "W_OUT_BLOCK_CRED_3@9",
17226 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 9)",
17227 .pme_code = 1209,
17228 .pme_flags = 0x0,
17229 .pme_numasks = 0,
17230 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17231 .pme_ctr = 15,
17232 .pme_event = 3,
17233 .pme_chipno = 9,
17234 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17235 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17236 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17237 },
17238 {
17239 .pme_name = "W_OUT_BLOCK_CRED_3@10",
17240 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 10)",
17241 .pme_code = 1210,
17242 .pme_flags = 0x0,
17243 .pme_numasks = 0,
17244 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17245 .pme_ctr = 15,
17246 .pme_event = 3,
17247 .pme_chipno = 10,
17248 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17249 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17250 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17251 },
17252 {
17253 .pme_name = "W_OUT_BLOCK_CRED_3@11",
17254 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 11)",
17255 .pme_code = 1211,
17256 .pme_flags = 0x0,
17257 .pme_numasks = 0,
17258 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17259 .pme_ctr = 15,
17260 .pme_event = 3,
17261 .pme_chipno = 11,
17262 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17263 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17264 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17265 },
17266 {
17267 .pme_name = "W_OUT_BLOCK_CRED_3@12",
17268 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 12)",
17269 .pme_code = 1212,
17270 .pme_flags = 0x0,
17271 .pme_numasks = 0,
17272 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17273 .pme_ctr = 15,
17274 .pme_event = 3,
17275 .pme_chipno = 12,
17276 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17277 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17278 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17279 },
17280 {
17281 .pme_name = "W_OUT_BLOCK_CRED_3@13",
17282 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 13)",
17283 .pme_code = 1213,
17284 .pme_flags = 0x0,
17285 .pme_numasks = 0,
17286 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17287 .pme_ctr = 15,
17288 .pme_event = 3,
17289 .pme_chipno = 13,
17290 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17291 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17292 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17293 },
17294 {
17295 .pme_name = "W_OUT_BLOCK_CRED_3@14",
17296 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 14)",
17297 .pme_code = 1214,
17298 .pme_flags = 0x0,
17299 .pme_numasks = 0,
17300 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17301 .pme_ctr = 15,
17302 .pme_event = 3,
17303 .pme_chipno = 14,
17304 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17305 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17306 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17307 },
17308 {
17309 .pme_name = "W_OUT_BLOCK_CRED_3@15",
17310 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 15)",
17311 .pme_code = 1215,
17312 .pme_flags = 0x0,
17313 .pme_numasks = 0,
17314 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17315 .pme_ctr = 15,
17316 .pme_event = 3,
17317 .pme_chipno = 15,
17318 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17319 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17320 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17321 },
17322 /* M Counter 16 Event 0 */
17323 {
17324 .pme_name = "REQUEST_1DWORD_L3_HIT@0",
17325 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 0)",
17326 .pme_code = 1216,
17327 .pme_flags = 0x0,
17328 .pme_numasks = 0,
17329 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17330 .pme_ctr = 16,
17331 .pme_event = 0,
17332 .pme_chipno = 0,
17333 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17334 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17335 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17336 },
17337 {
17338 .pme_name = "REQUEST_1DWORD_L3_HIT@1",
17339 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 1)",
17340 .pme_code = 1217,
17341 .pme_flags = 0x0,
17342 .pme_numasks = 0,
17343 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17344 .pme_ctr = 16,
17345 .pme_event = 0,
17346 .pme_chipno = 1,
17347 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17348 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17349 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17350 },
17351 {
17352 .pme_name = "REQUEST_1DWORD_L3_HIT@2",
17353 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 2)",
17354 .pme_code = 1218,
17355 .pme_flags = 0x0,
17356 .pme_numasks = 0,
17357 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17358 .pme_ctr = 16,
17359 .pme_event = 0,
17360 .pme_chipno = 2,
17361 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17362 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17363 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17364 },
17365 {
17366 .pme_name = "REQUEST_1DWORD_L3_HIT@3",
17367 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 3)",
17368 .pme_code = 1219,
17369 .pme_flags = 0x0,
17370 .pme_numasks = 0,
17371 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17372 .pme_ctr = 16,
17373 .pme_event = 0,
17374 .pme_chipno = 3,
17375 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17376 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17377 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17378 },
17379 {
17380 .pme_name = "REQUEST_1DWORD_L3_HIT@4",
17381 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 4)",
17382 .pme_code = 1220,
17383 .pme_flags = 0x0,
17384 .pme_numasks = 0,
17385 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17386 .pme_ctr = 16,
17387 .pme_event = 0,
17388 .pme_chipno = 4,
17389 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17390 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17391 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17392 },
17393 {
17394 .pme_name = "REQUEST_1DWORD_L3_HIT@5",
17395 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 5)",
17396 .pme_code = 1221,
17397 .pme_flags = 0x0,
17398 .pme_numasks = 0,
17399 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17400 .pme_ctr = 16,
17401 .pme_event = 0,
17402 .pme_chipno = 5,
17403 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17404 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17405 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17406 },
17407 {
17408 .pme_name = "REQUEST_1DWORD_L3_HIT@6",
17409 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 6)",
17410 .pme_code = 1222,
17411 .pme_flags = 0x0,
17412 .pme_numasks = 0,
17413 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17414 .pme_ctr = 16,
17415 .pme_event = 0,
17416 .pme_chipno = 6,
17417 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17418 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17419 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17420 },
17421 {
17422 .pme_name = "REQUEST_1DWORD_L3_HIT@7",
17423 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 7)",
17424 .pme_code = 1223,
17425 .pme_flags = 0x0,
17426 .pme_numasks = 0,
17427 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17428 .pme_ctr = 16,
17429 .pme_event = 0,
17430 .pme_chipno = 7,
17431 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17432 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17433 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17434 },
17435 {
17436 .pme_name = "REQUEST_1DWORD_L3_HIT@8",
17437 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 8)",
17438 .pme_code = 1224,
17439 .pme_flags = 0x0,
17440 .pme_numasks = 0,
17441 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17442 .pme_ctr = 16,
17443 .pme_event = 0,
17444 .pme_chipno = 8,
17445 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17446 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17447 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17448 },
17449 {
17450 .pme_name = "REQUEST_1DWORD_L3_HIT@9",
17451 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 9)",
17452 .pme_code = 1225,
17453 .pme_flags = 0x0,
17454 .pme_numasks = 0,
17455 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17456 .pme_ctr = 16,
17457 .pme_event = 0,
17458 .pme_chipno = 9,
17459 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17460 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17461 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17462 },
17463 {
17464 .pme_name = "REQUEST_1DWORD_L3_HIT@10",
17465 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 10)",
17466 .pme_code = 1226,
17467 .pme_flags = 0x0,
17468 .pme_numasks = 0,
17469 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17470 .pme_ctr = 16,
17471 .pme_event = 0,
17472 .pme_chipno = 10,
17473 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17474 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17475 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17476 },
17477 {
17478 .pme_name = "REQUEST_1DWORD_L3_HIT@11",
17479 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 11)",
17480 .pme_code = 1227,
17481 .pme_flags = 0x0,
17482 .pme_numasks = 0,
17483 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17484 .pme_ctr = 16,
17485 .pme_event = 0,
17486 .pme_chipno = 11,
17487 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17488 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17489 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17490 },
17491 {
17492 .pme_name = "REQUEST_1DWORD_L3_HIT@12",
17493 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 12)",
17494 .pme_code = 1228,
17495 .pme_flags = 0x0,
17496 .pme_numasks = 0,
17497 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17498 .pme_ctr = 16,
17499 .pme_event = 0,
17500 .pme_chipno = 12,
17501 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17502 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17503 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17504 },
17505 {
17506 .pme_name = "REQUEST_1DWORD_L3_HIT@13",
17507 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 13)",
17508 .pme_code = 1229,
17509 .pme_flags = 0x0,
17510 .pme_numasks = 0,
17511 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17512 .pme_ctr = 16,
17513 .pme_event = 0,
17514 .pme_chipno = 13,
17515 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17516 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17517 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17518 },
17519 {
17520 .pme_name = "REQUEST_1DWORD_L3_HIT@14",
17521 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 14)",
17522 .pme_code = 1230,
17523 .pme_flags = 0x0,
17524 .pme_numasks = 0,
17525 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17526 .pme_ctr = 16,
17527 .pme_event = 0,
17528 .pme_chipno = 14,
17529 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17530 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17531 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17532 },
17533 {
17534 .pme_name = "REQUEST_1DWORD_L3_HIT@15",
17535 .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 15)",
17536 .pme_code = 1231,
17537 .pme_flags = 0x0,
17538 .pme_numasks = 0,
17539 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17540 .pme_ctr = 16,
17541 .pme_event = 0,
17542 .pme_chipno = 15,
17543 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17544 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17545 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17546 },
17547 /* M Counter 16 Event 1 */
17548 {
17549 .pme_name = "AMOS@0",
17550 .pme_desc = "AMOs to local memory (memory manager). (M chip 0)",
17551 .pme_code = 1232,
17552 .pme_flags = 0x0,
17553 .pme_numasks = 0,
17554 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17555 .pme_ctr = 16,
17556 .pme_event = 1,
17557 .pme_chipno = 0,
17558 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17559 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17560 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17561 },
17562 {
17563 .pme_name = "AMOS@1",
17564 .pme_desc = "AMOs to local memory (memory manager). (M chip 1)",
17565 .pme_code = 1233,
17566 .pme_flags = 0x0,
17567 .pme_numasks = 0,
17568 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17569 .pme_ctr = 16,
17570 .pme_event = 1,
17571 .pme_chipno = 1,
17572 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17573 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17574 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17575 },
17576 {
17577 .pme_name = "AMOS@2",
17578 .pme_desc = "AMOs to local memory (memory manager). (M chip 2)",
17579 .pme_code = 1234,
17580 .pme_flags = 0x0,
17581 .pme_numasks = 0,
17582 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17583 .pme_ctr = 16,
17584 .pme_event = 1,
17585 .pme_chipno = 2,
17586 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17587 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17588 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17589 },
17590 {
17591 .pme_name = "AMOS@3",
17592 .pme_desc = "AMOs to local memory (memory manager). (M chip 3)",
17593 .pme_code = 1235,
17594 .pme_flags = 0x0,
17595 .pme_numasks = 0,
17596 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17597 .pme_ctr = 16,
17598 .pme_event = 1,
17599 .pme_chipno = 3,
17600 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17601 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17602 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17603 },
17604 {
17605 .pme_name = "AMOS@4",
17606 .pme_desc = "AMOs to local memory (memory manager). (M chip 4)",
17607 .pme_code = 1236,
17608 .pme_flags = 0x0,
17609 .pme_numasks = 0,
17610 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17611 .pme_ctr = 16,
17612 .pme_event = 1,
17613 .pme_chipno = 4,
17614 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17615 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17616 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17617 },
17618 {
17619 .pme_name = "AMOS@5",
17620 .pme_desc = "AMOs to local memory (memory manager). (M chip 5)",
17621 .pme_code = 1237,
17622 .pme_flags = 0x0,
17623 .pme_numasks = 0,
17624 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17625 .pme_ctr = 16,
17626 .pme_event = 1,
17627 .pme_chipno = 5,
17628 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17629 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17630 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17631 },
17632 {
17633 .pme_name = "AMOS@6",
17634 .pme_desc = "AMOs to local memory (memory manager). (M chip 6)",
17635 .pme_code = 1238,
17636 .pme_flags = 0x0,
17637 .pme_numasks = 0,
17638 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17639 .pme_ctr = 16,
17640 .pme_event = 1,
17641 .pme_chipno = 6,
17642 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17643 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17644 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17645 },
17646 {
17647 .pme_name = "AMOS@7",
17648 .pme_desc = "AMOs to local memory (memory manager). (M chip 7)",
17649 .pme_code = 1239,
17650 .pme_flags = 0x0,
17651 .pme_numasks = 0,
17652 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17653 .pme_ctr = 16,
17654 .pme_event = 1,
17655 .pme_chipno = 7,
17656 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17657 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17658 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17659 },
17660 {
17661 .pme_name = "AMOS@8",
17662 .pme_desc = "AMOs to local memory (memory manager). (M chip 8)",
17663 .pme_code = 1240,
17664 .pme_flags = 0x0,
17665 .pme_numasks = 0,
17666 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17667 .pme_ctr = 16,
17668 .pme_event = 1,
17669 .pme_chipno = 8,
17670 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17671 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17672 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17673 },
17674 {
17675 .pme_name = "AMOS@9",
17676 .pme_desc = "AMOs to local memory (memory manager). (M chip 9)",
17677 .pme_code = 1241,
17678 .pme_flags = 0x0,
17679 .pme_numasks = 0,
17680 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17681 .pme_ctr = 16,
17682 .pme_event = 1,
17683 .pme_chipno = 9,
17684 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17685 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17686 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17687 },
17688 {
17689 .pme_name = "AMOS@10",
17690 .pme_desc = "AMOs to local memory (memory manager). (M chip 10)",
17691 .pme_code = 1242,
17692 .pme_flags = 0x0,
17693 .pme_numasks = 0,
17694 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17695 .pme_ctr = 16,
17696 .pme_event = 1,
17697 .pme_chipno = 10,
17698 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17699 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17700 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17701 },
17702 {
17703 .pme_name = "AMOS@11",
17704 .pme_desc = "AMOs to local memory (memory manager). (M chip 11)",
17705 .pme_code = 1243,
17706 .pme_flags = 0x0,
17707 .pme_numasks = 0,
17708 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17709 .pme_ctr = 16,
17710 .pme_event = 1,
17711 .pme_chipno = 11,
17712 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17713 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17714 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17715 },
17716 {
17717 .pme_name = "AMOS@12",
17718 .pme_desc = "AMOs to local memory (memory manager). (M chip 12)",
17719 .pme_code = 1244,
17720 .pme_flags = 0x0,
17721 .pme_numasks = 0,
17722 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17723 .pme_ctr = 16,
17724 .pme_event = 1,
17725 .pme_chipno = 12,
17726 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17727 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17728 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17729 },
17730 {
17731 .pme_name = "AMOS@13",
17732 .pme_desc = "AMOs to local memory (memory manager). (M chip 13)",
17733 .pme_code = 1245,
17734 .pme_flags = 0x0,
17735 .pme_numasks = 0,
17736 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17737 .pme_ctr = 16,
17738 .pme_event = 1,
17739 .pme_chipno = 13,
17740 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17741 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17742 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17743 },
17744 {
17745 .pme_name = "AMOS@14",
17746 .pme_desc = "AMOs to local memory (memory manager). (M chip 14)",
17747 .pme_code = 1246,
17748 .pme_flags = 0x0,
17749 .pme_numasks = 0,
17750 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17751 .pme_ctr = 16,
17752 .pme_event = 1,
17753 .pme_chipno = 14,
17754 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17755 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17756 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17757 },
17758 {
17759 .pme_name = "AMOS@15",
17760 .pme_desc = "AMOs to local memory (memory manager). (M chip 15)",
17761 .pme_code = 1247,
17762 .pme_flags = 0x0,
17763 .pme_numasks = 0,
17764 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17765 .pme_ctr = 16,
17766 .pme_event = 1,
17767 .pme_chipno = 15,
17768 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17769 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17770 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17771 },
17772 /* M Counter 16 Event 2 */
17773 {
17774 .pme_name = "MM0_ANY_BANK_BUSY@0",
17775 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 0)",
17776 .pme_code = 1248,
17777 .pme_flags = 0x0,
17778 .pme_numasks = 0,
17779 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17780 .pme_ctr = 16,
17781 .pme_event = 2,
17782 .pme_chipno = 0,
17783 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17784 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17785 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17786 },
17787 {
17788 .pme_name = "MM0_ANY_BANK_BUSY@1",
17789 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 1)",
17790 .pme_code = 1249,
17791 .pme_flags = 0x0,
17792 .pme_numasks = 0,
17793 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17794 .pme_ctr = 16,
17795 .pme_event = 2,
17796 .pme_chipno = 1,
17797 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17798 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17799 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17800 },
17801 {
17802 .pme_name = "MM0_ANY_BANK_BUSY@2",
17803 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 2)",
17804 .pme_code = 1250,
17805 .pme_flags = 0x0,
17806 .pme_numasks = 0,
17807 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17808 .pme_ctr = 16,
17809 .pme_event = 2,
17810 .pme_chipno = 2,
17811 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17812 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17813 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17814 },
17815 {
17816 .pme_name = "MM0_ANY_BANK_BUSY@3",
17817 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 3)",
17818 .pme_code = 1251,
17819 .pme_flags = 0x0,
17820 .pme_numasks = 0,
17821 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17822 .pme_ctr = 16,
17823 .pme_event = 2,
17824 .pme_chipno = 3,
17825 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17826 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17827 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17828 },
17829 {
17830 .pme_name = "MM0_ANY_BANK_BUSY@4",
17831 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 4)",
17832 .pme_code = 1252,
17833 .pme_flags = 0x0,
17834 .pme_numasks = 0,
17835 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17836 .pme_ctr = 16,
17837 .pme_event = 2,
17838 .pme_chipno = 4,
17839 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17840 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17841 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17842 },
17843 {
17844 .pme_name = "MM0_ANY_BANK_BUSY@5",
17845 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 5)",
17846 .pme_code = 1253,
17847 .pme_flags = 0x0,
17848 .pme_numasks = 0,
17849 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17850 .pme_ctr = 16,
17851 .pme_event = 2,
17852 .pme_chipno = 5,
17853 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17854 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17855 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17856 },
17857 {
17858 .pme_name = "MM0_ANY_BANK_BUSY@6",
17859 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 6)",
17860 .pme_code = 1254,
17861 .pme_flags = 0x0,
17862 .pme_numasks = 0,
17863 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17864 .pme_ctr = 16,
17865 .pme_event = 2,
17866 .pme_chipno = 6,
17867 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17868 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17869 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17870 },
17871 {
17872 .pme_name = "MM0_ANY_BANK_BUSY@7",
17873 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 7)",
17874 .pme_code = 1255,
17875 .pme_flags = 0x0,
17876 .pme_numasks = 0,
17877 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17878 .pme_ctr = 16,
17879 .pme_event = 2,
17880 .pme_chipno = 7,
17881 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17882 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17883 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17884 },
17885 {
17886 .pme_name = "MM0_ANY_BANK_BUSY@8",
17887 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 8)",
17888 .pme_code = 1256,
17889 .pme_flags = 0x0,
17890 .pme_numasks = 0,
17891 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17892 .pme_ctr = 16,
17893 .pme_event = 2,
17894 .pme_chipno = 8,
17895 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17896 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17897 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17898 },
17899 {
17900 .pme_name = "MM0_ANY_BANK_BUSY@9",
17901 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 9)",
17902 .pme_code = 1257,
17903 .pme_flags = 0x0,
17904 .pme_numasks = 0,
17905 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17906 .pme_ctr = 16,
17907 .pme_event = 2,
17908 .pme_chipno = 9,
17909 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17910 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17911 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17912 },
17913 {
17914 .pme_name = "MM0_ANY_BANK_BUSY@10",
17915 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 10)",
17916 .pme_code = 1258,
17917 .pme_flags = 0x0,
17918 .pme_numasks = 0,
17919 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17920 .pme_ctr = 16,
17921 .pme_event = 2,
17922 .pme_chipno = 10,
17923 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17924 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17925 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17926 },
17927 {
17928 .pme_name = "MM0_ANY_BANK_BUSY@11",
17929 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 11)",
17930 .pme_code = 1259,
17931 .pme_flags = 0x0,
17932 .pme_numasks = 0,
17933 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17934 .pme_ctr = 16,
17935 .pme_event = 2,
17936 .pme_chipno = 11,
17937 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17938 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17939 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17940 },
17941 {
17942 .pme_name = "MM0_ANY_BANK_BUSY@12",
17943 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 12)",
17944 .pme_code = 1260,
17945 .pme_flags = 0x0,
17946 .pme_numasks = 0,
17947 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17948 .pme_ctr = 16,
17949 .pme_event = 2,
17950 .pme_chipno = 12,
17951 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17952 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17953 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17954 },
17955 {
17956 .pme_name = "MM0_ANY_BANK_BUSY@13",
17957 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 13)",
17958 .pme_code = 1261,
17959 .pme_flags = 0x0,
17960 .pme_numasks = 0,
17961 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17962 .pme_ctr = 16,
17963 .pme_event = 2,
17964 .pme_chipno = 13,
17965 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17966 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17967 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17968 },
17969 {
17970 .pme_name = "MM0_ANY_BANK_BUSY@14",
17971 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 14)",
17972 .pme_code = 1262,
17973 .pme_flags = 0x0,
17974 .pme_numasks = 0,
17975 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17976 .pme_ctr = 16,
17977 .pme_event = 2,
17978 .pme_chipno = 14,
17979 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17980 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17981 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17982 },
17983 {
17984 .pme_name = "MM0_ANY_BANK_BUSY@15",
17985 .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 15)",
17986 .pme_code = 1263,
17987 .pme_flags = 0x0,
17988 .pme_numasks = 0,
17989 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
17990 .pme_ctr = 16,
17991 .pme_event = 2,
17992 .pme_chipno = 15,
17993 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
17994 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
17995 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
17996 },
17997 /* M Counter 16 Event 3 */
17998 {
17999 .pme_name = "W_OUT_BLOCK_CHN_0@0",
18000 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 0)",
18001 .pme_code = 1264,
18002 .pme_flags = 0x0,
18003 .pme_numasks = 0,
18004 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18005 .pme_ctr = 16,
18006 .pme_event = 3,
18007 .pme_chipno = 0,
18008 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18009 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18010 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18011 },
18012 {
18013 .pme_name = "W_OUT_BLOCK_CHN_0@1",
18014 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 1)",
18015 .pme_code = 1265,
18016 .pme_flags = 0x0,
18017 .pme_numasks = 0,
18018 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18019 .pme_ctr = 16,
18020 .pme_event = 3,
18021 .pme_chipno = 1,
18022 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18023 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18024 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18025 },
18026 {
18027 .pme_name = "W_OUT_BLOCK_CHN_0@2",
18028 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 2)",
18029 .pme_code = 1266,
18030 .pme_flags = 0x0,
18031 .pme_numasks = 0,
18032 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18033 .pme_ctr = 16,
18034 .pme_event = 3,
18035 .pme_chipno = 2,
18036 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18037 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18038 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18039 },
18040 {
18041 .pme_name = "W_OUT_BLOCK_CHN_0@3",
18042 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 3)",
18043 .pme_code = 1267,
18044 .pme_flags = 0x0,
18045 .pme_numasks = 0,
18046 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18047 .pme_ctr = 16,
18048 .pme_event = 3,
18049 .pme_chipno = 3,
18050 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18051 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18052 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18053 },
18054 {
18055 .pme_name = "W_OUT_BLOCK_CHN_0@4",
18056 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 4)",
18057 .pme_code = 1268,
18058 .pme_flags = 0x0,
18059 .pme_numasks = 0,
18060 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18061 .pme_ctr = 16,
18062 .pme_event = 3,
18063 .pme_chipno = 4,
18064 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18065 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18066 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18067 },
18068 {
18069 .pme_name = "W_OUT_BLOCK_CHN_0@5",
18070 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 5)",
18071 .pme_code = 1269,
18072 .pme_flags = 0x0,
18073 .pme_numasks = 0,
18074 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18075 .pme_ctr = 16,
18076 .pme_event = 3,
18077 .pme_chipno = 5,
18078 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18079 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18080 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18081 },
18082 {
18083 .pme_name = "W_OUT_BLOCK_CHN_0@6",
18084 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 6)",
18085 .pme_code = 1270,
18086 .pme_flags = 0x0,
18087 .pme_numasks = 0,
18088 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18089 .pme_ctr = 16,
18090 .pme_event = 3,
18091 .pme_chipno = 6,
18092 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18093 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18094 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18095 },
18096 {
18097 .pme_name = "W_OUT_BLOCK_CHN_0@7",
18098 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 7)",
18099 .pme_code = 1271,
18100 .pme_flags = 0x0,
18101 .pme_numasks = 0,
18102 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18103 .pme_ctr = 16,
18104 .pme_event = 3,
18105 .pme_chipno = 7,
18106 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18107 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18108 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18109 },
18110 {
18111 .pme_name = "W_OUT_BLOCK_CHN_0@8",
18112 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 8)",
18113 .pme_code = 1272,
18114 .pme_flags = 0x0,
18115 .pme_numasks = 0,
18116 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18117 .pme_ctr = 16,
18118 .pme_event = 3,
18119 .pme_chipno = 8,
18120 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18121 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18122 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18123 },
18124 {
18125 .pme_name = "W_OUT_BLOCK_CHN_0@9",
18126 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 9)",
18127 .pme_code = 1273,
18128 .pme_flags = 0x0,
18129 .pme_numasks = 0,
18130 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18131 .pme_ctr = 16,
18132 .pme_event = 3,
18133 .pme_chipno = 9,
18134 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18135 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18136 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18137 },
18138 {
18139 .pme_name = "W_OUT_BLOCK_CHN_0@10",
18140 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 10)",
18141 .pme_code = 1274,
18142 .pme_flags = 0x0,
18143 .pme_numasks = 0,
18144 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18145 .pme_ctr = 16,
18146 .pme_event = 3,
18147 .pme_chipno = 10,
18148 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18149 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18150 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18151 },
18152 {
18153 .pme_name = "W_OUT_BLOCK_CHN_0@11",
18154 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 11)",
18155 .pme_code = 1275,
18156 .pme_flags = 0x0,
18157 .pme_numasks = 0,
18158 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18159 .pme_ctr = 16,
18160 .pme_event = 3,
18161 .pme_chipno = 11,
18162 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18163 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18164 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18165 },
18166 {
18167 .pme_name = "W_OUT_BLOCK_CHN_0@12",
18168 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 12)",
18169 .pme_code = 1276,
18170 .pme_flags = 0x0,
18171 .pme_numasks = 0,
18172 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18173 .pme_ctr = 16,
18174 .pme_event = 3,
18175 .pme_chipno = 12,
18176 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18177 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18178 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18179 },
18180 {
18181 .pme_name = "W_OUT_BLOCK_CHN_0@13",
18182 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 13)",
18183 .pme_code = 1277,
18184 .pme_flags = 0x0,
18185 .pme_numasks = 0,
18186 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18187 .pme_ctr = 16,
18188 .pme_event = 3,
18189 .pme_chipno = 13,
18190 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18191 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18192 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18193 },
18194 {
18195 .pme_name = "W_OUT_BLOCK_CHN_0@14",
18196 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 14)",
18197 .pme_code = 1278,
18198 .pme_flags = 0x0,
18199 .pme_numasks = 0,
18200 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18201 .pme_ctr = 16,
18202 .pme_event = 3,
18203 .pme_chipno = 14,
18204 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18205 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18206 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18207 },
18208 {
18209 .pme_name = "W_OUT_BLOCK_CHN_0@15",
18210 .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 15)",
18211 .pme_code = 1279,
18212 .pme_flags = 0x0,
18213 .pme_numasks = 0,
18214 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18215 .pme_ctr = 16,
18216 .pme_event = 3,
18217 .pme_chipno = 15,
18218 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18219 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18220 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18221 },
18222 /* M Counter 17 Event 0 */
18223 {
18224 .pme_name = "REQUEST_4DWORDS_L3_HIT@0",
18225 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 0)",
18226 .pme_code = 1280,
18227 .pme_flags = 0x0,
18228 .pme_numasks = 0,
18229 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18230 .pme_ctr = 17,
18231 .pme_event = 0,
18232 .pme_chipno = 0,
18233 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18234 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18235 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18236 },
18237 {
18238 .pme_name = "REQUEST_4DWORDS_L3_HIT@1",
18239 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 1)",
18240 .pme_code = 1281,
18241 .pme_flags = 0x0,
18242 .pme_numasks = 0,
18243 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18244 .pme_ctr = 17,
18245 .pme_event = 0,
18246 .pme_chipno = 1,
18247 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18248 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18249 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18250 },
18251 {
18252 .pme_name = "REQUEST_4DWORDS_L3_HIT@2",
18253 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 2)",
18254 .pme_code = 1282,
18255 .pme_flags = 0x0,
18256 .pme_numasks = 0,
18257 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18258 .pme_ctr = 17,
18259 .pme_event = 0,
18260 .pme_chipno = 2,
18261 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18262 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18263 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18264 },
18265 {
18266 .pme_name = "REQUEST_4DWORDS_L3_HIT@3",
18267 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 3)",
18268 .pme_code = 1283,
18269 .pme_flags = 0x0,
18270 .pme_numasks = 0,
18271 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18272 .pme_ctr = 17,
18273 .pme_event = 0,
18274 .pme_chipno = 3,
18275 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18276 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18277 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18278 },
18279 {
18280 .pme_name = "REQUEST_4DWORDS_L3_HIT@4",
18281 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 4)",
18282 .pme_code = 1284,
18283 .pme_flags = 0x0,
18284 .pme_numasks = 0,
18285 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18286 .pme_ctr = 17,
18287 .pme_event = 0,
18288 .pme_chipno = 4,
18289 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18290 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18291 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18292 },
18293 {
18294 .pme_name = "REQUEST_4DWORDS_L3_HIT@5",
18295 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 5)",
18296 .pme_code = 1285,
18297 .pme_flags = 0x0,
18298 .pme_numasks = 0,
18299 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18300 .pme_ctr = 17,
18301 .pme_event = 0,
18302 .pme_chipno = 5,
18303 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18304 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18305 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18306 },
18307 {
18308 .pme_name = "REQUEST_4DWORDS_L3_HIT@6",
18309 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 6)",
18310 .pme_code = 1286,
18311 .pme_flags = 0x0,
18312 .pme_numasks = 0,
18313 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18314 .pme_ctr = 17,
18315 .pme_event = 0,
18316 .pme_chipno = 6,
18317 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18318 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18319 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18320 },
18321 {
18322 .pme_name = "REQUEST_4DWORDS_L3_HIT@7",
18323 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 7)",
18324 .pme_code = 1287,
18325 .pme_flags = 0x0,
18326 .pme_numasks = 0,
18327 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18328 .pme_ctr = 17,
18329 .pme_event = 0,
18330 .pme_chipno = 7,
18331 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18332 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18333 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18334 },
18335 {
18336 .pme_name = "REQUEST_4DWORDS_L3_HIT@8",
18337 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 8)",
18338 .pme_code = 1288,
18339 .pme_flags = 0x0,
18340 .pme_numasks = 0,
18341 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18342 .pme_ctr = 17,
18343 .pme_event = 0,
18344 .pme_chipno = 8,
18345 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18346 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18347 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18348 },
18349 {
18350 .pme_name = "REQUEST_4DWORDS_L3_HIT@9",
18351 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 9)",
18352 .pme_code = 1289,
18353 .pme_flags = 0x0,
18354 .pme_numasks = 0,
18355 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18356 .pme_ctr = 17,
18357 .pme_event = 0,
18358 .pme_chipno = 9,
18359 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18360 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18361 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18362 },
18363 {
18364 .pme_name = "REQUEST_4DWORDS_L3_HIT@10",
18365 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 10)",
18366 .pme_code = 1290,
18367 .pme_flags = 0x0,
18368 .pme_numasks = 0,
18369 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18370 .pme_ctr = 17,
18371 .pme_event = 0,
18372 .pme_chipno = 10,
18373 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18374 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18375 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18376 },
18377 {
18378 .pme_name = "REQUEST_4DWORDS_L3_HIT@11",
18379 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 11)",
18380 .pme_code = 1291,
18381 .pme_flags = 0x0,
18382 .pme_numasks = 0,
18383 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18384 .pme_ctr = 17,
18385 .pme_event = 0,
18386 .pme_chipno = 11,
18387 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18388 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18389 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18390 },
18391 {
18392 .pme_name = "REQUEST_4DWORDS_L3_HIT@12",
18393 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 12)",
18394 .pme_code = 1292,
18395 .pme_flags = 0x0,
18396 .pme_numasks = 0,
18397 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18398 .pme_ctr = 17,
18399 .pme_event = 0,
18400 .pme_chipno = 12,
18401 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18402 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18403 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18404 },
18405 {
18406 .pme_name = "REQUEST_4DWORDS_L3_HIT@13",
18407 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 13)",
18408 .pme_code = 1293,
18409 .pme_flags = 0x0,
18410 .pme_numasks = 0,
18411 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18412 .pme_ctr = 17,
18413 .pme_event = 0,
18414 .pme_chipno = 13,
18415 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18416 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18417 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18418 },
18419 {
18420 .pme_name = "REQUEST_4DWORDS_L3_HIT@14",
18421 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 14)",
18422 .pme_code = 1294,
18423 .pme_flags = 0x0,
18424 .pme_numasks = 0,
18425 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18426 .pme_ctr = 17,
18427 .pme_event = 0,
18428 .pme_chipno = 14,
18429 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18430 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18431 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18432 },
18433 {
18434 .pme_name = "REQUEST_4DWORDS_L3_HIT@15",
18435 .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 15)",
18436 .pme_code = 1295,
18437 .pme_flags = 0x0,
18438 .pme_numasks = 0,
18439 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18440 .pme_ctr = 17,
18441 .pme_event = 0,
18442 .pme_chipno = 15,
18443 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18444 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18445 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18446 },
18447 /* M Counter 17 Event 1 */
18448 {
18449 .pme_name = "AMO_MISSES@0",
18450 .pme_desc = "Misses in AMO cache (memory manager). (M chip 0)",
18451 .pme_code = 1296,
18452 .pme_flags = 0x0,
18453 .pme_numasks = 0,
18454 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18455 .pme_ctr = 17,
18456 .pme_event = 1,
18457 .pme_chipno = 0,
18458 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18459 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18460 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18461 },
18462 {
18463 .pme_name = "AMO_MISSES@1",
18464 .pme_desc = "Misses in AMO cache (memory manager). (M chip 1)",
18465 .pme_code = 1297,
18466 .pme_flags = 0x0,
18467 .pme_numasks = 0,
18468 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18469 .pme_ctr = 17,
18470 .pme_event = 1,
18471 .pme_chipno = 1,
18472 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18473 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18474 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18475 },
18476 {
18477 .pme_name = "AMO_MISSES@2",
18478 .pme_desc = "Misses in AMO cache (memory manager). (M chip 2)",
18479 .pme_code = 1298,
18480 .pme_flags = 0x0,
18481 .pme_numasks = 0,
18482 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18483 .pme_ctr = 17,
18484 .pme_event = 1,
18485 .pme_chipno = 2,
18486 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18487 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18488 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18489 },
18490 {
18491 .pme_name = "AMO_MISSES@3",
18492 .pme_desc = "Misses in AMO cache (memory manager). (M chip 3)",
18493 .pme_code = 1299,
18494 .pme_flags = 0x0,
18495 .pme_numasks = 0,
18496 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18497 .pme_ctr = 17,
18498 .pme_event = 1,
18499 .pme_chipno = 3,
18500 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18501 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18502 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18503 },
18504 {
18505 .pme_name = "AMO_MISSES@4",
18506 .pme_desc = "Misses in AMO cache (memory manager). (M chip 4)",
18507 .pme_code = 1300,
18508 .pme_flags = 0x0,
18509 .pme_numasks = 0,
18510 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18511 .pme_ctr = 17,
18512 .pme_event = 1,
18513 .pme_chipno = 4,
18514 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18515 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18516 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18517 },
18518 {
18519 .pme_name = "AMO_MISSES@5",
18520 .pme_desc = "Misses in AMO cache (memory manager). (M chip 5)",
18521 .pme_code = 1301,
18522 .pme_flags = 0x0,
18523 .pme_numasks = 0,
18524 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18525 .pme_ctr = 17,
18526 .pme_event = 1,
18527 .pme_chipno = 5,
18528 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18529 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18530 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18531 },
18532 {
18533 .pme_name = "AMO_MISSES@6",
18534 .pme_desc = "Misses in AMO cache (memory manager). (M chip 6)",
18535 .pme_code = 1302,
18536 .pme_flags = 0x0,
18537 .pme_numasks = 0,
18538 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18539 .pme_ctr = 17,
18540 .pme_event = 1,
18541 .pme_chipno = 6,
18542 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18543 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18544 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18545 },
18546 {
18547 .pme_name = "AMO_MISSES@7",
18548 .pme_desc = "Misses in AMO cache (memory manager). (M chip 7)",
18549 .pme_code = 1303,
18550 .pme_flags = 0x0,
18551 .pme_numasks = 0,
18552 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18553 .pme_ctr = 17,
18554 .pme_event = 1,
18555 .pme_chipno = 7,
18556 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18557 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18558 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18559 },
18560 {
18561 .pme_name = "AMO_MISSES@8",
18562 .pme_desc = "Misses in AMO cache (memory manager). (M chip 8)",
18563 .pme_code = 1304,
18564 .pme_flags = 0x0,
18565 .pme_numasks = 0,
18566 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18567 .pme_ctr = 17,
18568 .pme_event = 1,
18569 .pme_chipno = 8,
18570 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18571 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18572 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18573 },
18574 {
18575 .pme_name = "AMO_MISSES@9",
18576 .pme_desc = "Misses in AMO cache (memory manager). (M chip 9)",
18577 .pme_code = 1305,
18578 .pme_flags = 0x0,
18579 .pme_numasks = 0,
18580 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18581 .pme_ctr = 17,
18582 .pme_event = 1,
18583 .pme_chipno = 9,
18584 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18585 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18586 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18587 },
18588 {
18589 .pme_name = "AMO_MISSES@10",
18590 .pme_desc = "Misses in AMO cache (memory manager). (M chip 10)",
18591 .pme_code = 1306,
18592 .pme_flags = 0x0,
18593 .pme_numasks = 0,
18594 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18595 .pme_ctr = 17,
18596 .pme_event = 1,
18597 .pme_chipno = 10,
18598 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18599 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18600 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18601 },
18602 {
18603 .pme_name = "AMO_MISSES@11",
18604 .pme_desc = "Misses in AMO cache (memory manager). (M chip 11)",
18605 .pme_code = 1307,
18606 .pme_flags = 0x0,
18607 .pme_numasks = 0,
18608 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18609 .pme_ctr = 17,
18610 .pme_event = 1,
18611 .pme_chipno = 11,
18612 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18613 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18614 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18615 },
18616 {
18617 .pme_name = "AMO_MISSES@12",
18618 .pme_desc = "Misses in AMO cache (memory manager). (M chip 12)",
18619 .pme_code = 1308,
18620 .pme_flags = 0x0,
18621 .pme_numasks = 0,
18622 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18623 .pme_ctr = 17,
18624 .pme_event = 1,
18625 .pme_chipno = 12,
18626 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18627 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18628 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18629 },
18630 {
18631 .pme_name = "AMO_MISSES@13",
18632 .pme_desc = "Misses in AMO cache (memory manager). (M chip 13)",
18633 .pme_code = 1309,
18634 .pme_flags = 0x0,
18635 .pme_numasks = 0,
18636 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18637 .pme_ctr = 17,
18638 .pme_event = 1,
18639 .pme_chipno = 13,
18640 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18641 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18642 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18643 },
18644 {
18645 .pme_name = "AMO_MISSES@14",
18646 .pme_desc = "Misses in AMO cache (memory manager). (M chip 14)",
18647 .pme_code = 1310,
18648 .pme_flags = 0x0,
18649 .pme_numasks = 0,
18650 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18651 .pme_ctr = 17,
18652 .pme_event = 1,
18653 .pme_chipno = 14,
18654 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18655 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18656 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18657 },
18658 {
18659 .pme_name = "AMO_MISSES@15",
18660 .pme_desc = "Misses in AMO cache (memory manager). (M chip 15)",
18661 .pme_code = 1311,
18662 .pme_flags = 0x0,
18663 .pme_numasks = 0,
18664 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18665 .pme_ctr = 17,
18666 .pme_event = 1,
18667 .pme_chipno = 15,
18668 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18669 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18670 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18671 },
18672 /* M Counter 17 Event 2 */
18673 {
18674 .pme_name = "MM0_ACCUM_BANK_BUSY@0",
18675 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)",
18676 .pme_code = 1312,
18677 .pme_flags = 0x0,
18678 .pme_numasks = 0,
18679 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18680 .pme_ctr = 17,
18681 .pme_event = 2,
18682 .pme_chipno = 0,
18683 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18684 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18685 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18686 },
18687 {
18688 .pme_name = "MM0_ACCUM_BANK_BUSY@1",
18689 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)",
18690 .pme_code = 1313,
18691 .pme_flags = 0x0,
18692 .pme_numasks = 0,
18693 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18694 .pme_ctr = 17,
18695 .pme_event = 2,
18696 .pme_chipno = 1,
18697 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18698 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18699 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18700 },
18701 {
18702 .pme_name = "MM0_ACCUM_BANK_BUSY@2",
18703 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)",
18704 .pme_code = 1314,
18705 .pme_flags = 0x0,
18706 .pme_numasks = 0,
18707 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18708 .pme_ctr = 17,
18709 .pme_event = 2,
18710 .pme_chipno = 2,
18711 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18712 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18713 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18714 },
18715 {
18716 .pme_name = "MM0_ACCUM_BANK_BUSY@3",
18717 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)",
18718 .pme_code = 1315,
18719 .pme_flags = 0x0,
18720 .pme_numasks = 0,
18721 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18722 .pme_ctr = 17,
18723 .pme_event = 2,
18724 .pme_chipno = 3,
18725 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18726 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18727 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18728 },
18729 {
18730 .pme_name = "MM0_ACCUM_BANK_BUSY@4",
18731 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)",
18732 .pme_code = 1316,
18733 .pme_flags = 0x0,
18734 .pme_numasks = 0,
18735 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18736 .pme_ctr = 17,
18737 .pme_event = 2,
18738 .pme_chipno = 4,
18739 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18740 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18741 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18742 },
18743 {
18744 .pme_name = "MM0_ACCUM_BANK_BUSY@5",
18745 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)",
18746 .pme_code = 1317,
18747 .pme_flags = 0x0,
18748 .pme_numasks = 0,
18749 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18750 .pme_ctr = 17,
18751 .pme_event = 2,
18752 .pme_chipno = 5,
18753 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18754 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18755 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18756 },
18757 {
18758 .pme_name = "MM0_ACCUM_BANK_BUSY@6",
18759 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)",
18760 .pme_code = 1318,
18761 .pme_flags = 0x0,
18762 .pme_numasks = 0,
18763 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18764 .pme_ctr = 17,
18765 .pme_event = 2,
18766 .pme_chipno = 6,
18767 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18768 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18769 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18770 },
18771 {
18772 .pme_name = "MM0_ACCUM_BANK_BUSY@7",
18773 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)",
18774 .pme_code = 1319,
18775 .pme_flags = 0x0,
18776 .pme_numasks = 0,
18777 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18778 .pme_ctr = 17,
18779 .pme_event = 2,
18780 .pme_chipno = 7,
18781 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18782 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18783 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18784 },
18785 {
18786 .pme_name = "MM0_ACCUM_BANK_BUSY@8",
18787 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)",
18788 .pme_code = 1320,
18789 .pme_flags = 0x0,
18790 .pme_numasks = 0,
18791 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18792 .pme_ctr = 17,
18793 .pme_event = 2,
18794 .pme_chipno = 8,
18795 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18796 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18797 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18798 },
18799 {
18800 .pme_name = "MM0_ACCUM_BANK_BUSY@9",
18801 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)",
18802 .pme_code = 1321,
18803 .pme_flags = 0x0,
18804 .pme_numasks = 0,
18805 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18806 .pme_ctr = 17,
18807 .pme_event = 2,
18808 .pme_chipno = 9,
18809 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18810 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18811 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18812 },
18813 {
18814 .pme_name = "MM0_ACCUM_BANK_BUSY@10",
18815 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)",
18816 .pme_code = 1322,
18817 .pme_flags = 0x0,
18818 .pme_numasks = 0,
18819 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18820 .pme_ctr = 17,
18821 .pme_event = 2,
18822 .pme_chipno = 10,
18823 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18824 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18825 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18826 },
18827 {
18828 .pme_name = "MM0_ACCUM_BANK_BUSY@11",
18829 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)",
18830 .pme_code = 1323,
18831 .pme_flags = 0x0,
18832 .pme_numasks = 0,
18833 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18834 .pme_ctr = 17,
18835 .pme_event = 2,
18836 .pme_chipno = 11,
18837 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18838 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18839 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18840 },
18841 {
18842 .pme_name = "MM0_ACCUM_BANK_BUSY@12",
18843 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)",
18844 .pme_code = 1324,
18845 .pme_flags = 0x0,
18846 .pme_numasks = 0,
18847 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18848 .pme_ctr = 17,
18849 .pme_event = 2,
18850 .pme_chipno = 12,
18851 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18852 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18853 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18854 },
18855 {
18856 .pme_name = "MM0_ACCUM_BANK_BUSY@13",
18857 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)",
18858 .pme_code = 1325,
18859 .pme_flags = 0x0,
18860 .pme_numasks = 0,
18861 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18862 .pme_ctr = 17,
18863 .pme_event = 2,
18864 .pme_chipno = 13,
18865 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18866 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18867 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18868 },
18869 {
18870 .pme_name = "MM0_ACCUM_BANK_BUSY@14",
18871 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)",
18872 .pme_code = 1326,
18873 .pme_flags = 0x0,
18874 .pme_numasks = 0,
18875 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18876 .pme_ctr = 17,
18877 .pme_event = 2,
18878 .pme_chipno = 14,
18879 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18880 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18881 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18882 },
18883 {
18884 .pme_name = "MM0_ACCUM_BANK_BUSY@15",
18885 .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)",
18886 .pme_code = 1327,
18887 .pme_flags = 0x0,
18888 .pme_numasks = 0,
18889 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18890 .pme_ctr = 17,
18891 .pme_event = 2,
18892 .pme_chipno = 15,
18893 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18894 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18895 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18896 },
18897 /* M Counter 17 Event 3 */
18898 {
18899 .pme_name = "W_OUT_BLOCK_CHN_1@0",
18900 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 0)",
18901 .pme_code = 1328,
18902 .pme_flags = 0x0,
18903 .pme_numasks = 0,
18904 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18905 .pme_ctr = 17,
18906 .pme_event = 3,
18907 .pme_chipno = 0,
18908 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18909 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18910 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18911 },
18912 {
18913 .pme_name = "W_OUT_BLOCK_CHN_1@1",
18914 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 1)",
18915 .pme_code = 1329,
18916 .pme_flags = 0x0,
18917 .pme_numasks = 0,
18918 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18919 .pme_ctr = 17,
18920 .pme_event = 3,
18921 .pme_chipno = 1,
18922 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18923 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18924 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18925 },
18926 {
18927 .pme_name = "W_OUT_BLOCK_CHN_1@2",
18928 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 2)",
18929 .pme_code = 1330,
18930 .pme_flags = 0x0,
18931 .pme_numasks = 0,
18932 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18933 .pme_ctr = 17,
18934 .pme_event = 3,
18935 .pme_chipno = 2,
18936 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18937 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18938 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18939 },
18940 {
18941 .pme_name = "W_OUT_BLOCK_CHN_1@3",
18942 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 3)",
18943 .pme_code = 1331,
18944 .pme_flags = 0x0,
18945 .pme_numasks = 0,
18946 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18947 .pme_ctr = 17,
18948 .pme_event = 3,
18949 .pme_chipno = 3,
18950 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18951 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18952 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18953 },
18954 {
18955 .pme_name = "W_OUT_BLOCK_CHN_1@4",
18956 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 4)",
18957 .pme_code = 1332,
18958 .pme_flags = 0x0,
18959 .pme_numasks = 0,
18960 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18961 .pme_ctr = 17,
18962 .pme_event = 3,
18963 .pme_chipno = 4,
18964 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18965 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18966 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18967 },
18968 {
18969 .pme_name = "W_OUT_BLOCK_CHN_1@5",
18970 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 5)",
18971 .pme_code = 1333,
18972 .pme_flags = 0x0,
18973 .pme_numasks = 0,
18974 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18975 .pme_ctr = 17,
18976 .pme_event = 3,
18977 .pme_chipno = 5,
18978 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18979 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18980 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18981 },
18982 {
18983 .pme_name = "W_OUT_BLOCK_CHN_1@6",
18984 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 6)",
18985 .pme_code = 1334,
18986 .pme_flags = 0x0,
18987 .pme_numasks = 0,
18988 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
18989 .pme_ctr = 17,
18990 .pme_event = 3,
18991 .pme_chipno = 6,
18992 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
18993 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
18994 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
18995 },
18996 {
18997 .pme_name = "W_OUT_BLOCK_CHN_1@7",
18998 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 7)",
18999 .pme_code = 1335,
19000 .pme_flags = 0x0,
19001 .pme_numasks = 0,
19002 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19003 .pme_ctr = 17,
19004 .pme_event = 3,
19005 .pme_chipno = 7,
19006 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19007 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19008 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19009 },
19010 {
19011 .pme_name = "W_OUT_BLOCK_CHN_1@8",
19012 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 8)",
19013 .pme_code = 1336,
19014 .pme_flags = 0x0,
19015 .pme_numasks = 0,
19016 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19017 .pme_ctr = 17,
19018 .pme_event = 3,
19019 .pme_chipno = 8,
19020 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19021 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19022 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19023 },
19024 {
19025 .pme_name = "W_OUT_BLOCK_CHN_1@9",
19026 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 9)",
19027 .pme_code = 1337,
19028 .pme_flags = 0x0,
19029 .pme_numasks = 0,
19030 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19031 .pme_ctr = 17,
19032 .pme_event = 3,
19033 .pme_chipno = 9,
19034 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19035 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19036 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19037 },
19038 {
19039 .pme_name = "W_OUT_BLOCK_CHN_1@10",
19040 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 10)",
19041 .pme_code = 1338,
19042 .pme_flags = 0x0,
19043 .pme_numasks = 0,
19044 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19045 .pme_ctr = 17,
19046 .pme_event = 3,
19047 .pme_chipno = 10,
19048 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19049 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19050 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19051 },
19052 {
19053 .pme_name = "W_OUT_BLOCK_CHN_1@11",
19054 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 11)",
19055 .pme_code = 1339,
19056 .pme_flags = 0x0,
19057 .pme_numasks = 0,
19058 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19059 .pme_ctr = 17,
19060 .pme_event = 3,
19061 .pme_chipno = 11,
19062 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19063 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19064 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19065 },
19066 {
19067 .pme_name = "W_OUT_BLOCK_CHN_1@12",
19068 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 12)",
19069 .pme_code = 1340,
19070 .pme_flags = 0x0,
19071 .pme_numasks = 0,
19072 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19073 .pme_ctr = 17,
19074 .pme_event = 3,
19075 .pme_chipno = 12,
19076 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19077 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19078 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19079 },
19080 {
19081 .pme_name = "W_OUT_BLOCK_CHN_1@13",
19082 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 13)",
19083 .pme_code = 1341,
19084 .pme_flags = 0x0,
19085 .pme_numasks = 0,
19086 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19087 .pme_ctr = 17,
19088 .pme_event = 3,
19089 .pme_chipno = 13,
19090 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19091 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19092 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19093 },
19094 {
19095 .pme_name = "W_OUT_BLOCK_CHN_1@14",
19096 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 14)",
19097 .pme_code = 1342,
19098 .pme_flags = 0x0,
19099 .pme_numasks = 0,
19100 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19101 .pme_ctr = 17,
19102 .pme_event = 3,
19103 .pme_chipno = 14,
19104 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19105 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19106 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19107 },
19108 {
19109 .pme_name = "W_OUT_BLOCK_CHN_1@15",
19110 .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 15)",
19111 .pme_code = 1343,
19112 .pme_flags = 0x0,
19113 .pme_numasks = 0,
19114 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19115 .pme_ctr = 17,
19116 .pme_event = 3,
19117 .pme_chipno = 15,
19118 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19119 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19120 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19121 },
19122 /* M Counter 18 Event 0 */
19123 {
19124 .pme_name = "REQUEST_1DWORD@0",
19125 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 0)",
19126 .pme_code = 1344,
19127 .pme_flags = 0x0,
19128 .pme_numasks = 0,
19129 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19130 .pme_ctr = 18,
19131 .pme_event = 0,
19132 .pme_chipno = 0,
19133 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19134 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19135 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19136 },
19137 {
19138 .pme_name = "REQUEST_1DWORD@1",
19139 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 1)",
19140 .pme_code = 1345,
19141 .pme_flags = 0x0,
19142 .pme_numasks = 0,
19143 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19144 .pme_ctr = 18,
19145 .pme_event = 0,
19146 .pme_chipno = 1,
19147 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19148 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19149 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19150 },
19151 {
19152 .pme_name = "REQUEST_1DWORD@2",
19153 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 2)",
19154 .pme_code = 1346,
19155 .pme_flags = 0x0,
19156 .pme_numasks = 0,
19157 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19158 .pme_ctr = 18,
19159 .pme_event = 0,
19160 .pme_chipno = 2,
19161 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19162 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19163 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19164 },
19165 {
19166 .pme_name = "REQUEST_1DWORD@3",
19167 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 3)",
19168 .pme_code = 1347,
19169 .pme_flags = 0x0,
19170 .pme_numasks = 0,
19171 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19172 .pme_ctr = 18,
19173 .pme_event = 0,
19174 .pme_chipno = 3,
19175 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19176 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19177 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19178 },
19179 {
19180 .pme_name = "REQUEST_1DWORD@4",
19181 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 4)",
19182 .pme_code = 1348,
19183 .pme_flags = 0x0,
19184 .pme_numasks = 0,
19185 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19186 .pme_ctr = 18,
19187 .pme_event = 0,
19188 .pme_chipno = 4,
19189 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19190 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19191 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19192 },
19193 {
19194 .pme_name = "REQUEST_1DWORD@5",
19195 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 5)",
19196 .pme_code = 1349,
19197 .pme_flags = 0x0,
19198 .pme_numasks = 0,
19199 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19200 .pme_ctr = 18,
19201 .pme_event = 0,
19202 .pme_chipno = 5,
19203 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19204 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19205 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19206 },
19207 {
19208 .pme_name = "REQUEST_1DWORD@6",
19209 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 6)",
19210 .pme_code = 1350,
19211 .pme_flags = 0x0,
19212 .pme_numasks = 0,
19213 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19214 .pme_ctr = 18,
19215 .pme_event = 0,
19216 .pme_chipno = 6,
19217 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19218 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19219 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19220 },
19221 {
19222 .pme_name = "REQUEST_1DWORD@7",
19223 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 7)",
19224 .pme_code = 1351,
19225 .pme_flags = 0x0,
19226 .pme_numasks = 0,
19227 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19228 .pme_ctr = 18,
19229 .pme_event = 0,
19230 .pme_chipno = 7,
19231 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19232 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19233 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19234 },
19235 {
19236 .pme_name = "REQUEST_1DWORD@8",
19237 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 8)",
19238 .pme_code = 1352,
19239 .pme_flags = 0x0,
19240 .pme_numasks = 0,
19241 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19242 .pme_ctr = 18,
19243 .pme_event = 0,
19244 .pme_chipno = 8,
19245 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19246 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19247 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19248 },
19249 {
19250 .pme_name = "REQUEST_1DWORD@9",
19251 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 9)",
19252 .pme_code = 1353,
19253 .pme_flags = 0x0,
19254 .pme_numasks = 0,
19255 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19256 .pme_ctr = 18,
19257 .pme_event = 0,
19258 .pme_chipno = 9,
19259 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19260 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19261 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19262 },
19263 {
19264 .pme_name = "REQUEST_1DWORD@10",
19265 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 10)",
19266 .pme_code = 1354,
19267 .pme_flags = 0x0,
19268 .pme_numasks = 0,
19269 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19270 .pme_ctr = 18,
19271 .pme_event = 0,
19272 .pme_chipno = 10,
19273 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19274 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19275 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19276 },
19277 {
19278 .pme_name = "REQUEST_1DWORD@11",
19279 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 11)",
19280 .pme_code = 1355,
19281 .pme_flags = 0x0,
19282 .pme_numasks = 0,
19283 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19284 .pme_ctr = 18,
19285 .pme_event = 0,
19286 .pme_chipno = 11,
19287 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19288 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19289 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19290 },
19291 {
19292 .pme_name = "REQUEST_1DWORD@12",
19293 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 12)",
19294 .pme_code = 1356,
19295 .pme_flags = 0x0,
19296 .pme_numasks = 0,
19297 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19298 .pme_ctr = 18,
19299 .pme_event = 0,
19300 .pme_chipno = 12,
19301 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19302 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19303 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19304 },
19305 {
19306 .pme_name = "REQUEST_1DWORD@13",
19307 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 13)",
19308 .pme_code = 1357,
19309 .pme_flags = 0x0,
19310 .pme_numasks = 0,
19311 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19312 .pme_ctr = 18,
19313 .pme_event = 0,
19314 .pme_chipno = 13,
19315 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19316 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19317 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19318 },
19319 {
19320 .pme_name = "REQUEST_1DWORD@14",
19321 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 14)",
19322 .pme_code = 1358,
19323 .pme_flags = 0x0,
19324 .pme_numasks = 0,
19325 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19326 .pme_ctr = 18,
19327 .pme_event = 0,
19328 .pme_chipno = 14,
19329 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19330 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19331 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19332 },
19333 {
19334 .pme_name = "REQUEST_1DWORD@15",
19335 .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 15)",
19336 .pme_code = 1359,
19337 .pme_flags = 0x0,
19338 .pme_numasks = 0,
19339 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19340 .pme_ctr = 18,
19341 .pme_event = 0,
19342 .pme_chipno = 15,
19343 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19344 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19345 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19346 },
19347 /* M Counter 18 Event 1 */
19348 {
19349 .pme_name = "RETRIES_MM@0",
19350 .pme_desc = "Memory Manager retries. (M chip 0)",
19351 .pme_code = 1360,
19352 .pme_flags = 0x0,
19353 .pme_numasks = 0,
19354 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19355 .pme_ctr = 18,
19356 .pme_event = 1,
19357 .pme_chipno = 0,
19358 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19359 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19360 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19361 },
19362 {
19363 .pme_name = "RETRIES_MM@1",
19364 .pme_desc = "Memory Manager retries. (M chip 1)",
19365 .pme_code = 1361,
19366 .pme_flags = 0x0,
19367 .pme_numasks = 0,
19368 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19369 .pme_ctr = 18,
19370 .pme_event = 1,
19371 .pme_chipno = 1,
19372 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19373 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19374 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19375 },
19376 {
19377 .pme_name = "RETRIES_MM@2",
19378 .pme_desc = "Memory Manager retries. (M chip 2)",
19379 .pme_code = 1362,
19380 .pme_flags = 0x0,
19381 .pme_numasks = 0,
19382 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19383 .pme_ctr = 18,
19384 .pme_event = 1,
19385 .pme_chipno = 2,
19386 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19387 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19388 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19389 },
19390 {
19391 .pme_name = "RETRIES_MM@3",
19392 .pme_desc = "Memory Manager retries. (M chip 3)",
19393 .pme_code = 1363,
19394 .pme_flags = 0x0,
19395 .pme_numasks = 0,
19396 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19397 .pme_ctr = 18,
19398 .pme_event = 1,
19399 .pme_chipno = 3,
19400 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19401 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19402 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19403 },
19404 {
19405 .pme_name = "RETRIES_MM@4",
19406 .pme_desc = "Memory Manager retries. (M chip 4)",
19407 .pme_code = 1364,
19408 .pme_flags = 0x0,
19409 .pme_numasks = 0,
19410 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19411 .pme_ctr = 18,
19412 .pme_event = 1,
19413 .pme_chipno = 4,
19414 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19415 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19416 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19417 },
19418 {
19419 .pme_name = "RETRIES_MM@5",
19420 .pme_desc = "Memory Manager retries. (M chip 5)",
19421 .pme_code = 1365,
19422 .pme_flags = 0x0,
19423 .pme_numasks = 0,
19424 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19425 .pme_ctr = 18,
19426 .pme_event = 1,
19427 .pme_chipno = 5,
19428 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19429 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19430 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19431 },
19432 {
19433 .pme_name = "RETRIES_MM@6",
19434 .pme_desc = "Memory Manager retries. (M chip 6)",
19435 .pme_code = 1366,
19436 .pme_flags = 0x0,
19437 .pme_numasks = 0,
19438 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19439 .pme_ctr = 18,
19440 .pme_event = 1,
19441 .pme_chipno = 6,
19442 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19443 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19444 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19445 },
19446 {
19447 .pme_name = "RETRIES_MM@7",
19448 .pme_desc = "Memory Manager retries. (M chip 7)",
19449 .pme_code = 1367,
19450 .pme_flags = 0x0,
19451 .pme_numasks = 0,
19452 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19453 .pme_ctr = 18,
19454 .pme_event = 1,
19455 .pme_chipno = 7,
19456 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19457 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19458 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19459 },
19460 {
19461 .pme_name = "RETRIES_MM@8",
19462 .pme_desc = "Memory Manager retries. (M chip 8)",
19463 .pme_code = 1368,
19464 .pme_flags = 0x0,
19465 .pme_numasks = 0,
19466 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19467 .pme_ctr = 18,
19468 .pme_event = 1,
19469 .pme_chipno = 8,
19470 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19471 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19472 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19473 },
19474 {
19475 .pme_name = "RETRIES_MM@9",
19476 .pme_desc = "Memory Manager retries. (M chip 9)",
19477 .pme_code = 1369,
19478 .pme_flags = 0x0,
19479 .pme_numasks = 0,
19480 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19481 .pme_ctr = 18,
19482 .pme_event = 1,
19483 .pme_chipno = 9,
19484 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19485 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19486 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19487 },
19488 {
19489 .pme_name = "RETRIES_MM@10",
19490 .pme_desc = "Memory Manager retries. (M chip 10)",
19491 .pme_code = 1370,
19492 .pme_flags = 0x0,
19493 .pme_numasks = 0,
19494 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19495 .pme_ctr = 18,
19496 .pme_event = 1,
19497 .pme_chipno = 10,
19498 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19499 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19500 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19501 },
19502 {
19503 .pme_name = "RETRIES_MM@11",
19504 .pme_desc = "Memory Manager retries. (M chip 11)",
19505 .pme_code = 1371,
19506 .pme_flags = 0x0,
19507 .pme_numasks = 0,
19508 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19509 .pme_ctr = 18,
19510 .pme_event = 1,
19511 .pme_chipno = 11,
19512 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19513 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19514 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19515 },
19516 {
19517 .pme_name = "RETRIES_MM@12",
19518 .pme_desc = "Memory Manager retries. (M chip 12)",
19519 .pme_code = 1372,
19520 .pme_flags = 0x0,
19521 .pme_numasks = 0,
19522 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19523 .pme_ctr = 18,
19524 .pme_event = 1,
19525 .pme_chipno = 12,
19526 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19527 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19528 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19529 },
19530 {
19531 .pme_name = "RETRIES_MM@13",
19532 .pme_desc = "Memory Manager retries. (M chip 13)",
19533 .pme_code = 1373,
19534 .pme_flags = 0x0,
19535 .pme_numasks = 0,
19536 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19537 .pme_ctr = 18,
19538 .pme_event = 1,
19539 .pme_chipno = 13,
19540 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19541 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19542 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19543 },
19544 {
19545 .pme_name = "RETRIES_MM@14",
19546 .pme_desc = "Memory Manager retries. (M chip 14)",
19547 .pme_code = 1374,
19548 .pme_flags = 0x0,
19549 .pme_numasks = 0,
19550 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19551 .pme_ctr = 18,
19552 .pme_event = 1,
19553 .pme_chipno = 14,
19554 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19555 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19556 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19557 },
19558 {
19559 .pme_name = "RETRIES_MM@15",
19560 .pme_desc = "Memory Manager retries. (M chip 15)",
19561 .pme_code = 1375,
19562 .pme_flags = 0x0,
19563 .pme_numasks = 0,
19564 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19565 .pme_ctr = 18,
19566 .pme_event = 1,
19567 .pme_chipno = 15,
19568 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19569 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19570 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19571 },
19572 /* M Counter 18 Event 2 */
19573 {
19574 .pme_name = "MM1_ANY_BANK_BUSY@0",
19575 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 0)",
19576 .pme_code = 1376,
19577 .pme_flags = 0x0,
19578 .pme_numasks = 0,
19579 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19580 .pme_ctr = 18,
19581 .pme_event = 2,
19582 .pme_chipno = 0,
19583 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19584 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19585 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19586 },
19587 {
19588 .pme_name = "MM1_ANY_BANK_BUSY@1",
19589 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 1)",
19590 .pme_code = 1377,
19591 .pme_flags = 0x0,
19592 .pme_numasks = 0,
19593 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19594 .pme_ctr = 18,
19595 .pme_event = 2,
19596 .pme_chipno = 1,
19597 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19598 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19599 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19600 },
19601 {
19602 .pme_name = "MM1_ANY_BANK_BUSY@2",
19603 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 2)",
19604 .pme_code = 1378,
19605 .pme_flags = 0x0,
19606 .pme_numasks = 0,
19607 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19608 .pme_ctr = 18,
19609 .pme_event = 2,
19610 .pme_chipno = 2,
19611 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19612 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19613 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19614 },
19615 {
19616 .pme_name = "MM1_ANY_BANK_BUSY@3",
19617 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 3)",
19618 .pme_code = 1379,
19619 .pme_flags = 0x0,
19620 .pme_numasks = 0,
19621 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19622 .pme_ctr = 18,
19623 .pme_event = 2,
19624 .pme_chipno = 3,
19625 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19626 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19627 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19628 },
19629 {
19630 .pme_name = "MM1_ANY_BANK_BUSY@4",
19631 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 4)",
19632 .pme_code = 1380,
19633 .pme_flags = 0x0,
19634 .pme_numasks = 0,
19635 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19636 .pme_ctr = 18,
19637 .pme_event = 2,
19638 .pme_chipno = 4,
19639 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19640 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19641 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19642 },
19643 {
19644 .pme_name = "MM1_ANY_BANK_BUSY@5",
19645 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 5)",
19646 .pme_code = 1381,
19647 .pme_flags = 0x0,
19648 .pme_numasks = 0,
19649 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19650 .pme_ctr = 18,
19651 .pme_event = 2,
19652 .pme_chipno = 5,
19653 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19654 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19655 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19656 },
19657 {
19658 .pme_name = "MM1_ANY_BANK_BUSY@6",
19659 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 6)",
19660 .pme_code = 1382,
19661 .pme_flags = 0x0,
19662 .pme_numasks = 0,
19663 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19664 .pme_ctr = 18,
19665 .pme_event = 2,
19666 .pme_chipno = 6,
19667 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19668 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19669 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19670 },
19671 {
19672 .pme_name = "MM1_ANY_BANK_BUSY@7",
19673 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 7)",
19674 .pme_code = 1383,
19675 .pme_flags = 0x0,
19676 .pme_numasks = 0,
19677 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19678 .pme_ctr = 18,
19679 .pme_event = 2,
19680 .pme_chipno = 7,
19681 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19682 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19683 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19684 },
19685 {
19686 .pme_name = "MM1_ANY_BANK_BUSY@8",
19687 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 8)",
19688 .pme_code = 1384,
19689 .pme_flags = 0x0,
19690 .pme_numasks = 0,
19691 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19692 .pme_ctr = 18,
19693 .pme_event = 2,
19694 .pme_chipno = 8,
19695 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19696 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19697 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19698 },
19699 {
19700 .pme_name = "MM1_ANY_BANK_BUSY@9",
19701 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 9)",
19702 .pme_code = 1385,
19703 .pme_flags = 0x0,
19704 .pme_numasks = 0,
19705 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19706 .pme_ctr = 18,
19707 .pme_event = 2,
19708 .pme_chipno = 9,
19709 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19710 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19711 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19712 },
19713 {
19714 .pme_name = "MM1_ANY_BANK_BUSY@10",
19715 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 10)",
19716 .pme_code = 1386,
19717 .pme_flags = 0x0,
19718 .pme_numasks = 0,
19719 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19720 .pme_ctr = 18,
19721 .pme_event = 2,
19722 .pme_chipno = 10,
19723 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19724 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19725 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19726 },
19727 {
19728 .pme_name = "MM1_ANY_BANK_BUSY@11",
19729 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 11)",
19730 .pme_code = 1387,
19731 .pme_flags = 0x0,
19732 .pme_numasks = 0,
19733 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19734 .pme_ctr = 18,
19735 .pme_event = 2,
19736 .pme_chipno = 11,
19737 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19738 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19739 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19740 },
19741 {
19742 .pme_name = "MM1_ANY_BANK_BUSY@12",
19743 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 12)",
19744 .pme_code = 1388,
19745 .pme_flags = 0x0,
19746 .pme_numasks = 0,
19747 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19748 .pme_ctr = 18,
19749 .pme_event = 2,
19750 .pme_chipno = 12,
19751 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19752 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19753 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19754 },
19755 {
19756 .pme_name = "MM1_ANY_BANK_BUSY@13",
19757 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 13)",
19758 .pme_code = 1389,
19759 .pme_flags = 0x0,
19760 .pme_numasks = 0,
19761 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19762 .pme_ctr = 18,
19763 .pme_event = 2,
19764 .pme_chipno = 13,
19765 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19766 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19767 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19768 },
19769 {
19770 .pme_name = "MM1_ANY_BANK_BUSY@14",
19771 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 14)",
19772 .pme_code = 1390,
19773 .pme_flags = 0x0,
19774 .pme_numasks = 0,
19775 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19776 .pme_ctr = 18,
19777 .pme_event = 2,
19778 .pme_chipno = 14,
19779 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19780 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19781 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19782 },
19783 {
19784 .pme_name = "MM1_ANY_BANK_BUSY@15",
19785 .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 15)",
19786 .pme_code = 1391,
19787 .pme_flags = 0x0,
19788 .pme_numasks = 0,
19789 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19790 .pme_ctr = 18,
19791 .pme_event = 2,
19792 .pme_chipno = 15,
19793 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19794 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19795 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19796 },
19797 /* M Counter 18 Event 3 */
19798 {
19799 .pme_name = "W_OUT_BLOCK_CHN_2@0",
19800 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 0)",
19801 .pme_code = 1392,
19802 .pme_flags = 0x0,
19803 .pme_numasks = 0,
19804 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19805 .pme_ctr = 18,
19806 .pme_event = 3,
19807 .pme_chipno = 0,
19808 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19809 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19810 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19811 },
19812 {
19813 .pme_name = "W_OUT_BLOCK_CHN_2@1",
19814 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 1)",
19815 .pme_code = 1393,
19816 .pme_flags = 0x0,
19817 .pme_numasks = 0,
19818 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19819 .pme_ctr = 18,
19820 .pme_event = 3,
19821 .pme_chipno = 1,
19822 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19823 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19824 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19825 },
19826 {
19827 .pme_name = "W_OUT_BLOCK_CHN_2@2",
19828 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 2)",
19829 .pme_code = 1394,
19830 .pme_flags = 0x0,
19831 .pme_numasks = 0,
19832 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19833 .pme_ctr = 18,
19834 .pme_event = 3,
19835 .pme_chipno = 2,
19836 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19837 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19838 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19839 },
19840 {
19841 .pme_name = "W_OUT_BLOCK_CHN_2@3",
19842 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 3)",
19843 .pme_code = 1395,
19844 .pme_flags = 0x0,
19845 .pme_numasks = 0,
19846 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19847 .pme_ctr = 18,
19848 .pme_event = 3,
19849 .pme_chipno = 3,
19850 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19851 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19852 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19853 },
19854 {
19855 .pme_name = "W_OUT_BLOCK_CHN_2@4",
19856 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 4)",
19857 .pme_code = 1396,
19858 .pme_flags = 0x0,
19859 .pme_numasks = 0,
19860 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19861 .pme_ctr = 18,
19862 .pme_event = 3,
19863 .pme_chipno = 4,
19864 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19865 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19866 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19867 },
19868 {
19869 .pme_name = "W_OUT_BLOCK_CHN_2@5",
19870 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 5)",
19871 .pme_code = 1397,
19872 .pme_flags = 0x0,
19873 .pme_numasks = 0,
19874 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19875 .pme_ctr = 18,
19876 .pme_event = 3,
19877 .pme_chipno = 5,
19878 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19879 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19880 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19881 },
19882 {
19883 .pme_name = "W_OUT_BLOCK_CHN_2@6",
19884 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 6)",
19885 .pme_code = 1398,
19886 .pme_flags = 0x0,
19887 .pme_numasks = 0,
19888 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19889 .pme_ctr = 18,
19890 .pme_event = 3,
19891 .pme_chipno = 6,
19892 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19893 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19894 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19895 },
19896 {
19897 .pme_name = "W_OUT_BLOCK_CHN_2@7",
19898 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 7)",
19899 .pme_code = 1399,
19900 .pme_flags = 0x0,
19901 .pme_numasks = 0,
19902 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19903 .pme_ctr = 18,
19904 .pme_event = 3,
19905 .pme_chipno = 7,
19906 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19907 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19908 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19909 },
19910 {
19911 .pme_name = "W_OUT_BLOCK_CHN_2@8",
19912 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 8)",
19913 .pme_code = 1400,
19914 .pme_flags = 0x0,
19915 .pme_numasks = 0,
19916 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19917 .pme_ctr = 18,
19918 .pme_event = 3,
19919 .pme_chipno = 8,
19920 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19921 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19922 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19923 },
19924 {
19925 .pme_name = "W_OUT_BLOCK_CHN_2@9",
19926 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 9)",
19927 .pme_code = 1401,
19928 .pme_flags = 0x0,
19929 .pme_numasks = 0,
19930 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19931 .pme_ctr = 18,
19932 .pme_event = 3,
19933 .pme_chipno = 9,
19934 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19935 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19936 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19937 },
19938 {
19939 .pme_name = "W_OUT_BLOCK_CHN_2@10",
19940 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 10)",
19941 .pme_code = 1402,
19942 .pme_flags = 0x0,
19943 .pme_numasks = 0,
19944 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19945 .pme_ctr = 18,
19946 .pme_event = 3,
19947 .pme_chipno = 10,
19948 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19949 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19950 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19951 },
19952 {
19953 .pme_name = "W_OUT_BLOCK_CHN_2@11",
19954 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 11)",
19955 .pme_code = 1403,
19956 .pme_flags = 0x0,
19957 .pme_numasks = 0,
19958 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19959 .pme_ctr = 18,
19960 .pme_event = 3,
19961 .pme_chipno = 11,
19962 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19963 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19964 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19965 },
19966 {
19967 .pme_name = "W_OUT_BLOCK_CHN_2@12",
19968 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 12)",
19969 .pme_code = 1404,
19970 .pme_flags = 0x0,
19971 .pme_numasks = 0,
19972 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19973 .pme_ctr = 18,
19974 .pme_event = 3,
19975 .pme_chipno = 12,
19976 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19977 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19978 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19979 },
19980 {
19981 .pme_name = "W_OUT_BLOCK_CHN_2@13",
19982 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 13)",
19983 .pme_code = 1405,
19984 .pme_flags = 0x0,
19985 .pme_numasks = 0,
19986 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
19987 .pme_ctr = 18,
19988 .pme_event = 3,
19989 .pme_chipno = 13,
19990 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
19991 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
19992 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
19993 },
19994 {
19995 .pme_name = "W_OUT_BLOCK_CHN_2@14",
19996 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 14)",
19997 .pme_code = 1406,
19998 .pme_flags = 0x0,
19999 .pme_numasks = 0,
20000 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20001 .pme_ctr = 18,
20002 .pme_event = 3,
20003 .pme_chipno = 14,
20004 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20005 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20006 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20007 },
20008 {
20009 .pme_name = "W_OUT_BLOCK_CHN_2@15",
20010 .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 15)",
20011 .pme_code = 1407,
20012 .pme_flags = 0x0,
20013 .pme_numasks = 0,
20014 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20015 .pme_ctr = 18,
20016 .pme_event = 3,
20017 .pme_chipno = 15,
20018 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20019 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20020 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20021 },
20022 /* M Counter 19 Event 0 */
20023 {
20024 .pme_name = "REQUEST_4DWORDS@0",
20025 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 0)",
20026 .pme_code = 1408,
20027 .pme_flags = 0x0,
20028 .pme_numasks = 0,
20029 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20030 .pme_ctr = 19,
20031 .pme_event = 0,
20032 .pme_chipno = 0,
20033 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20034 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20035 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20036 },
20037 {
20038 .pme_name = "REQUEST_4DWORDS@1",
20039 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 1)",
20040 .pme_code = 1409,
20041 .pme_flags = 0x0,
20042 .pme_numasks = 0,
20043 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20044 .pme_ctr = 19,
20045 .pme_event = 0,
20046 .pme_chipno = 1,
20047 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20048 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20049 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20050 },
20051 {
20052 .pme_name = "REQUEST_4DWORDS@2",
20053 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 2)",
20054 .pme_code = 1410,
20055 .pme_flags = 0x0,
20056 .pme_numasks = 0,
20057 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20058 .pme_ctr = 19,
20059 .pme_event = 0,
20060 .pme_chipno = 2,
20061 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20062 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20063 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20064 },
20065 {
20066 .pme_name = "REQUEST_4DWORDS@3",
20067 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 3)",
20068 .pme_code = 1411,
20069 .pme_flags = 0x0,
20070 .pme_numasks = 0,
20071 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20072 .pme_ctr = 19,
20073 .pme_event = 0,
20074 .pme_chipno = 3,
20075 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20076 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20077 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20078 },
20079 {
20080 .pme_name = "REQUEST_4DWORDS@4",
20081 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 4)",
20082 .pme_code = 1412,
20083 .pme_flags = 0x0,
20084 .pme_numasks = 0,
20085 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20086 .pme_ctr = 19,
20087 .pme_event = 0,
20088 .pme_chipno = 4,
20089 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20090 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20091 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20092 },
20093 {
20094 .pme_name = "REQUEST_4DWORDS@5",
20095 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 5)",
20096 .pme_code = 1413,
20097 .pme_flags = 0x0,
20098 .pme_numasks = 0,
20099 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20100 .pme_ctr = 19,
20101 .pme_event = 0,
20102 .pme_chipno = 5,
20103 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20104 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20105 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20106 },
20107 {
20108 .pme_name = "REQUEST_4DWORDS@6",
20109 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 6)",
20110 .pme_code = 1414,
20111 .pme_flags = 0x0,
20112 .pme_numasks = 0,
20113 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20114 .pme_ctr = 19,
20115 .pme_event = 0,
20116 .pme_chipno = 6,
20117 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20118 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20119 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20120 },
20121 {
20122 .pme_name = "REQUEST_4DWORDS@7",
20123 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 7)",
20124 .pme_code = 1415,
20125 .pme_flags = 0x0,
20126 .pme_numasks = 0,
20127 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20128 .pme_ctr = 19,
20129 .pme_event = 0,
20130 .pme_chipno = 7,
20131 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20132 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20133 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20134 },
20135 {
20136 .pme_name = "REQUEST_4DWORDS@8",
20137 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 8)",
20138 .pme_code = 1416,
20139 .pme_flags = 0x0,
20140 .pme_numasks = 0,
20141 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20142 .pme_ctr = 19,
20143 .pme_event = 0,
20144 .pme_chipno = 8,
20145 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20146 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20147 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20148 },
20149 {
20150 .pme_name = "REQUEST_4DWORDS@9",
20151 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 9)",
20152 .pme_code = 1417,
20153 .pme_flags = 0x0,
20154 .pme_numasks = 0,
20155 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20156 .pme_ctr = 19,
20157 .pme_event = 0,
20158 .pme_chipno = 9,
20159 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20160 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20161 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20162 },
20163 {
20164 .pme_name = "REQUEST_4DWORDS@10",
20165 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 10)",
20166 .pme_code = 1418,
20167 .pme_flags = 0x0,
20168 .pme_numasks = 0,
20169 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20170 .pme_ctr = 19,
20171 .pme_event = 0,
20172 .pme_chipno = 10,
20173 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20174 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20175 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20176 },
20177 {
20178 .pme_name = "REQUEST_4DWORDS@11",
20179 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 11)",
20180 .pme_code = 1419,
20181 .pme_flags = 0x0,
20182 .pme_numasks = 0,
20183 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20184 .pme_ctr = 19,
20185 .pme_event = 0,
20186 .pme_chipno = 11,
20187 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20188 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20189 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20190 },
20191 {
20192 .pme_name = "REQUEST_4DWORDS@12",
20193 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 12)",
20194 .pme_code = 1420,
20195 .pme_flags = 0x0,
20196 .pme_numasks = 0,
20197 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20198 .pme_ctr = 19,
20199 .pme_event = 0,
20200 .pme_chipno = 12,
20201 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20202 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20203 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20204 },
20205 {
20206 .pme_name = "REQUEST_4DWORDS@13",
20207 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 13)",
20208 .pme_code = 1421,
20209 .pme_flags = 0x0,
20210 .pme_numasks = 0,
20211 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20212 .pme_ctr = 19,
20213 .pme_event = 0,
20214 .pme_chipno = 13,
20215 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20216 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20217 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20218 },
20219 {
20220 .pme_name = "REQUEST_4DWORDS@14",
20221 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 14)",
20222 .pme_code = 1422,
20223 .pme_flags = 0x0,
20224 .pme_numasks = 0,
20225 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20226 .pme_ctr = 19,
20227 .pme_event = 0,
20228 .pme_chipno = 14,
20229 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20230 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20231 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20232 },
20233 {
20234 .pme_name = "REQUEST_4DWORDS@15",
20235 .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 15)",
20236 .pme_code = 1423,
20237 .pme_flags = 0x0,
20238 .pme_numasks = 0,
20239 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20240 .pme_ctr = 19,
20241 .pme_event = 0,
20242 .pme_chipno = 15,
20243 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20244 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20245 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20246 },
20247 /* M Counter 19 Event 1 */
20248 {
20249 .pme_name = "<M:19:1>@0",
20250 .pme_desc = "<NA>",
20251 .pme_code = 1424,
20252 .pme_flags = 0x0,
20253 .pme_numasks = 0,
20254 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20255 .pme_ctr = 19,
20256 .pme_event = 1,
20257 .pme_chipno = 0,
20258 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20259 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20260 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20261 },
20262 {
20263 .pme_name = "<M:19:1>@1",
20264 .pme_desc = "<NA>",
20265 .pme_code = 1425,
20266 .pme_flags = 0x0,
20267 .pme_numasks = 0,
20268 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20269 .pme_ctr = 19,
20270 .pme_event = 1,
20271 .pme_chipno = 1,
20272 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20273 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20274 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20275 },
20276 {
20277 .pme_name = "<M:19:1>@2",
20278 .pme_desc = "<NA>",
20279 .pme_code = 1426,
20280 .pme_flags = 0x0,
20281 .pme_numasks = 0,
20282 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20283 .pme_ctr = 19,
20284 .pme_event = 1,
20285 .pme_chipno = 2,
20286 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20287 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20288 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20289 },
20290 {
20291 .pme_name = "<M:19:1>@3",
20292 .pme_desc = "<NA>",
20293 .pme_code = 1427,
20294 .pme_flags = 0x0,
20295 .pme_numasks = 0,
20296 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20297 .pme_ctr = 19,
20298 .pme_event = 1,
20299 .pme_chipno = 3,
20300 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20301 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20302 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20303 },
20304 {
20305 .pme_name = "<M:19:1>@4",
20306 .pme_desc = "<NA>",
20307 .pme_code = 1428,
20308 .pme_flags = 0x0,
20309 .pme_numasks = 0,
20310 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20311 .pme_ctr = 19,
20312 .pme_event = 1,
20313 .pme_chipno = 4,
20314 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20315 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20316 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20317 },
20318 {
20319 .pme_name = "<M:19:1>@5",
20320 .pme_desc = "<NA>",
20321 .pme_code = 1429,
20322 .pme_flags = 0x0,
20323 .pme_numasks = 0,
20324 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20325 .pme_ctr = 19,
20326 .pme_event = 1,
20327 .pme_chipno = 5,
20328 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20329 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20330 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20331 },
20332 {
20333 .pme_name = "<M:19:1>@6",
20334 .pme_desc = "<NA>",
20335 .pme_code = 1430,
20336 .pme_flags = 0x0,
20337 .pme_numasks = 0,
20338 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20339 .pme_ctr = 19,
20340 .pme_event = 1,
20341 .pme_chipno = 6,
20342 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20343 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20344 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20345 },
20346 {
20347 .pme_name = "<M:19:1>@7",
20348 .pme_desc = "<NA>",
20349 .pme_code = 1431,
20350 .pme_flags = 0x0,
20351 .pme_numasks = 0,
20352 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20353 .pme_ctr = 19,
20354 .pme_event = 1,
20355 .pme_chipno = 7,
20356 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20357 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20358 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20359 },
20360 {
20361 .pme_name = "<M:19:1>@8",
20362 .pme_desc = "<NA>",
20363 .pme_code = 1432,
20364 .pme_flags = 0x0,
20365 .pme_numasks = 0,
20366 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20367 .pme_ctr = 19,
20368 .pme_event = 1,
20369 .pme_chipno = 8,
20370 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20371 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20372 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20373 },
20374 {
20375 .pme_name = "<M:19:1>@9",
20376 .pme_desc = "<NA>",
20377 .pme_code = 1433,
20378 .pme_flags = 0x0,
20379 .pme_numasks = 0,
20380 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20381 .pme_ctr = 19,
20382 .pme_event = 1,
20383 .pme_chipno = 9,
20384 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20385 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20386 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20387 },
20388 {
20389 .pme_name = "<M:19:1>@10",
20390 .pme_desc = "<NA>",
20391 .pme_code = 1434,
20392 .pme_flags = 0x0,
20393 .pme_numasks = 0,
20394 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20395 .pme_ctr = 19,
20396 .pme_event = 1,
20397 .pme_chipno = 10,
20398 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20399 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20400 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20401 },
20402 {
20403 .pme_name = "<M:19:1>@11",
20404 .pme_desc = "<NA>",
20405 .pme_code = 1435,
20406 .pme_flags = 0x0,
20407 .pme_numasks = 0,
20408 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20409 .pme_ctr = 19,
20410 .pme_event = 1,
20411 .pme_chipno = 11,
20412 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20413 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20414 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20415 },
20416 {
20417 .pme_name = "<M:19:1>@12",
20418 .pme_desc = "<NA>",
20419 .pme_code = 1436,
20420 .pme_flags = 0x0,
20421 .pme_numasks = 0,
20422 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20423 .pme_ctr = 19,
20424 .pme_event = 1,
20425 .pme_chipno = 12,
20426 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20427 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20428 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20429 },
20430 {
20431 .pme_name = "<M:19:1>@13",
20432 .pme_desc = "<NA>",
20433 .pme_code = 1437,
20434 .pme_flags = 0x0,
20435 .pme_numasks = 0,
20436 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20437 .pme_ctr = 19,
20438 .pme_event = 1,
20439 .pme_chipno = 13,
20440 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20441 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20442 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20443 },
20444 {
20445 .pme_name = "<M:19:1>@14",
20446 .pme_desc = "<NA>",
20447 .pme_code = 1438,
20448 .pme_flags = 0x0,
20449 .pme_numasks = 0,
20450 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20451 .pme_ctr = 19,
20452 .pme_event = 1,
20453 .pme_chipno = 14,
20454 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20455 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20456 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20457 },
20458 {
20459 .pme_name = "<M:19:1>@15",
20460 .pme_desc = "<NA>",
20461 .pme_code = 1439,
20462 .pme_flags = 0x0,
20463 .pme_numasks = 0,
20464 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20465 .pme_ctr = 19,
20466 .pme_event = 1,
20467 .pme_chipno = 15,
20468 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20469 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20470 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20471 },
20472 /* M Counter 19 Event 2 */
20473 {
20474 .pme_name = "MM1_ACCUM_BANK_BUSY@0",
20475 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)",
20476 .pme_code = 1440,
20477 .pme_flags = 0x0,
20478 .pme_numasks = 0,
20479 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20480 .pme_ctr = 19,
20481 .pme_event = 2,
20482 .pme_chipno = 0,
20483 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20484 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20485 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20486 },
20487 {
20488 .pme_name = "MM1_ACCUM_BANK_BUSY@1",
20489 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)",
20490 .pme_code = 1441,
20491 .pme_flags = 0x0,
20492 .pme_numasks = 0,
20493 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20494 .pme_ctr = 19,
20495 .pme_event = 2,
20496 .pme_chipno = 1,
20497 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20498 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20499 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20500 },
20501 {
20502 .pme_name = "MM1_ACCUM_BANK_BUSY@2",
20503 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)",
20504 .pme_code = 1442,
20505 .pme_flags = 0x0,
20506 .pme_numasks = 0,
20507 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20508 .pme_ctr = 19,
20509 .pme_event = 2,
20510 .pme_chipno = 2,
20511 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20512 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20513 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20514 },
20515 {
20516 .pme_name = "MM1_ACCUM_BANK_BUSY@3",
20517 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)",
20518 .pme_code = 1443,
20519 .pme_flags = 0x0,
20520 .pme_numasks = 0,
20521 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20522 .pme_ctr = 19,
20523 .pme_event = 2,
20524 .pme_chipno = 3,
20525 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20526 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20527 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20528 },
20529 {
20530 .pme_name = "MM1_ACCUM_BANK_BUSY@4",
20531 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)",
20532 .pme_code = 1444,
20533 .pme_flags = 0x0,
20534 .pme_numasks = 0,
20535 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20536 .pme_ctr = 19,
20537 .pme_event = 2,
20538 .pme_chipno = 4,
20539 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20540 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20541 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20542 },
20543 {
20544 .pme_name = "MM1_ACCUM_BANK_BUSY@5",
20545 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)",
20546 .pme_code = 1445,
20547 .pme_flags = 0x0,
20548 .pme_numasks = 0,
20549 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20550 .pme_ctr = 19,
20551 .pme_event = 2,
20552 .pme_chipno = 5,
20553 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20554 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20555 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20556 },
20557 {
20558 .pme_name = "MM1_ACCUM_BANK_BUSY@6",
20559 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)",
20560 .pme_code = 1446,
20561 .pme_flags = 0x0,
20562 .pme_numasks = 0,
20563 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20564 .pme_ctr = 19,
20565 .pme_event = 2,
20566 .pme_chipno = 6,
20567 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20568 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20569 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20570 },
20571 {
20572 .pme_name = "MM1_ACCUM_BANK_BUSY@7",
20573 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)",
20574 .pme_code = 1447,
20575 .pme_flags = 0x0,
20576 .pme_numasks = 0,
20577 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20578 .pme_ctr = 19,
20579 .pme_event = 2,
20580 .pme_chipno = 7,
20581 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20582 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20583 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20584 },
20585 {
20586 .pme_name = "MM1_ACCUM_BANK_BUSY@8",
20587 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)",
20588 .pme_code = 1448,
20589 .pme_flags = 0x0,
20590 .pme_numasks = 0,
20591 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20592 .pme_ctr = 19,
20593 .pme_event = 2,
20594 .pme_chipno = 8,
20595 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20596 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20597 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20598 },
20599 {
20600 .pme_name = "MM1_ACCUM_BANK_BUSY@9",
20601 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)",
20602 .pme_code = 1449,
20603 .pme_flags = 0x0,
20604 .pme_numasks = 0,
20605 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20606 .pme_ctr = 19,
20607 .pme_event = 2,
20608 .pme_chipno = 9,
20609 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20610 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20611 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20612 },
20613 {
20614 .pme_name = "MM1_ACCUM_BANK_BUSY@10",
20615 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)",
20616 .pme_code = 1450,
20617 .pme_flags = 0x0,
20618 .pme_numasks = 0,
20619 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20620 .pme_ctr = 19,
20621 .pme_event = 2,
20622 .pme_chipno = 10,
20623 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20624 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20625 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20626 },
20627 {
20628 .pme_name = "MM1_ACCUM_BANK_BUSY@11",
20629 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)",
20630 .pme_code = 1451,
20631 .pme_flags = 0x0,
20632 .pme_numasks = 0,
20633 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20634 .pme_ctr = 19,
20635 .pme_event = 2,
20636 .pme_chipno = 11,
20637 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20638 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20639 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20640 },
20641 {
20642 .pme_name = "MM1_ACCUM_BANK_BUSY@12",
20643 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)",
20644 .pme_code = 1452,
20645 .pme_flags = 0x0,
20646 .pme_numasks = 0,
20647 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20648 .pme_ctr = 19,
20649 .pme_event = 2,
20650 .pme_chipno = 12,
20651 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20652 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20653 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20654 },
20655 {
20656 .pme_name = "MM1_ACCUM_BANK_BUSY@13",
20657 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)",
20658 .pme_code = 1453,
20659 .pme_flags = 0x0,
20660 .pme_numasks = 0,
20661 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20662 .pme_ctr = 19,
20663 .pme_event = 2,
20664 .pme_chipno = 13,
20665 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20666 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20667 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20668 },
20669 {
20670 .pme_name = "MM1_ACCUM_BANK_BUSY@14",
20671 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)",
20672 .pme_code = 1454,
20673 .pme_flags = 0x0,
20674 .pme_numasks = 0,
20675 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20676 .pme_ctr = 19,
20677 .pme_event = 2,
20678 .pme_chipno = 14,
20679 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20680 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20681 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20682 },
20683 {
20684 .pme_name = "MM1_ACCUM_BANK_BUSY@15",
20685 .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)",
20686 .pme_code = 1455,
20687 .pme_flags = 0x0,
20688 .pme_numasks = 0,
20689 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20690 .pme_ctr = 19,
20691 .pme_event = 2,
20692 .pme_chipno = 15,
20693 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20694 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20695 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20696 },
20697 /* M Counter 19 Event 3 */
20698 {
20699 .pme_name = "W_OUT_BLOCK_CHN_3@0",
20700 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 0)",
20701 .pme_code = 1456,
20702 .pme_flags = 0x0,
20703 .pme_numasks = 0,
20704 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20705 .pme_ctr = 19,
20706 .pme_event = 3,
20707 .pme_chipno = 0,
20708 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20709 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20710 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20711 },
20712 {
20713 .pme_name = "W_OUT_BLOCK_CHN_3@1",
20714 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 1)",
20715 .pme_code = 1457,
20716 .pme_flags = 0x0,
20717 .pme_numasks = 0,
20718 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20719 .pme_ctr = 19,
20720 .pme_event = 3,
20721 .pme_chipno = 1,
20722 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20723 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20724 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20725 },
20726 {
20727 .pme_name = "W_OUT_BLOCK_CHN_3@2",
20728 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 2)",
20729 .pme_code = 1458,
20730 .pme_flags = 0x0,
20731 .pme_numasks = 0,
20732 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20733 .pme_ctr = 19,
20734 .pme_event = 3,
20735 .pme_chipno = 2,
20736 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20737 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20738 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20739 },
20740 {
20741 .pme_name = "W_OUT_BLOCK_CHN_3@3",
20742 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 3)",
20743 .pme_code = 1459,
20744 .pme_flags = 0x0,
20745 .pme_numasks = 0,
20746 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20747 .pme_ctr = 19,
20748 .pme_event = 3,
20749 .pme_chipno = 3,
20750 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20751 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20752 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20753 },
20754 {
20755 .pme_name = "W_OUT_BLOCK_CHN_3@4",
20756 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 4)",
20757 .pme_code = 1460,
20758 .pme_flags = 0x0,
20759 .pme_numasks = 0,
20760 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20761 .pme_ctr = 19,
20762 .pme_event = 3,
20763 .pme_chipno = 4,
20764 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20765 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20766 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20767 },
20768 {
20769 .pme_name = "W_OUT_BLOCK_CHN_3@5",
20770 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 5)",
20771 .pme_code = 1461,
20772 .pme_flags = 0x0,
20773 .pme_numasks = 0,
20774 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20775 .pme_ctr = 19,
20776 .pme_event = 3,
20777 .pme_chipno = 5,
20778 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20779 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20780 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20781 },
20782 {
20783 .pme_name = "W_OUT_BLOCK_CHN_3@6",
20784 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 6)",
20785 .pme_code = 1462,
20786 .pme_flags = 0x0,
20787 .pme_numasks = 0,
20788 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20789 .pme_ctr = 19,
20790 .pme_event = 3,
20791 .pme_chipno = 6,
20792 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20793 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20794 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20795 },
20796 {
20797 .pme_name = "W_OUT_BLOCK_CHN_3@7",
20798 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 7)",
20799 .pme_code = 1463,
20800 .pme_flags = 0x0,
20801 .pme_numasks = 0,
20802 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20803 .pme_ctr = 19,
20804 .pme_event = 3,
20805 .pme_chipno = 7,
20806 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20807 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20808 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20809 },
20810 {
20811 .pme_name = "W_OUT_BLOCK_CHN_3@8",
20812 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 8)",
20813 .pme_code = 1464,
20814 .pme_flags = 0x0,
20815 .pme_numasks = 0,
20816 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20817 .pme_ctr = 19,
20818 .pme_event = 3,
20819 .pme_chipno = 8,
20820 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20821 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20822 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20823 },
20824 {
20825 .pme_name = "W_OUT_BLOCK_CHN_3@9",
20826 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 9)",
20827 .pme_code = 1465,
20828 .pme_flags = 0x0,
20829 .pme_numasks = 0,
20830 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20831 .pme_ctr = 19,
20832 .pme_event = 3,
20833 .pme_chipno = 9,
20834 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20835 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20836 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20837 },
20838 {
20839 .pme_name = "W_OUT_BLOCK_CHN_3@10",
20840 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 10)",
20841 .pme_code = 1466,
20842 .pme_flags = 0x0,
20843 .pme_numasks = 0,
20844 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20845 .pme_ctr = 19,
20846 .pme_event = 3,
20847 .pme_chipno = 10,
20848 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20849 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20850 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20851 },
20852 {
20853 .pme_name = "W_OUT_BLOCK_CHN_3@11",
20854 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 11)",
20855 .pme_code = 1467,
20856 .pme_flags = 0x0,
20857 .pme_numasks = 0,
20858 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20859 .pme_ctr = 19,
20860 .pme_event = 3,
20861 .pme_chipno = 11,
20862 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20863 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20864 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20865 },
20866 {
20867 .pme_name = "W_OUT_BLOCK_CHN_3@12",
20868 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 12)",
20869 .pme_code = 1468,
20870 .pme_flags = 0x0,
20871 .pme_numasks = 0,
20872 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20873 .pme_ctr = 19,
20874 .pme_event = 3,
20875 .pme_chipno = 12,
20876 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20877 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20878 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20879 },
20880 {
20881 .pme_name = "W_OUT_BLOCK_CHN_3@13",
20882 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 13)",
20883 .pme_code = 1469,
20884 .pme_flags = 0x0,
20885 .pme_numasks = 0,
20886 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20887 .pme_ctr = 19,
20888 .pme_event = 3,
20889 .pme_chipno = 13,
20890 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20891 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20892 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20893 },
20894 {
20895 .pme_name = "W_OUT_BLOCK_CHN_3@14",
20896 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 14)",
20897 .pme_code = 1470,
20898 .pme_flags = 0x0,
20899 .pme_numasks = 0,
20900 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20901 .pme_ctr = 19,
20902 .pme_event = 3,
20903 .pme_chipno = 14,
20904 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20905 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20906 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20907 },
20908 {
20909 .pme_name = "W_OUT_BLOCK_CHN_3@15",
20910 .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 15)",
20911 .pme_code = 1471,
20912 .pme_flags = 0x0,
20913 .pme_numasks = 0,
20914 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20915 .pme_ctr = 19,
20916 .pme_event = 3,
20917 .pme_chipno = 15,
20918 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20919 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20920 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20921 },
20922 /* M Counter 20 Event 0 */
20923 {
20924 .pme_name = "REQUESTS_0@0",
20925 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 0)",
20926 .pme_code = 1472,
20927 .pme_flags = 0x0,
20928 .pme_numasks = 0,
20929 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20930 .pme_ctr = 20,
20931 .pme_event = 0,
20932 .pme_chipno = 0,
20933 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20934 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20935 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20936 },
20937 {
20938 .pme_name = "REQUESTS_0@1",
20939 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 1)",
20940 .pme_code = 1473,
20941 .pme_flags = 0x0,
20942 .pme_numasks = 0,
20943 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20944 .pme_ctr = 20,
20945 .pme_event = 0,
20946 .pme_chipno = 1,
20947 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20948 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20949 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20950 },
20951 {
20952 .pme_name = "REQUESTS_0@2",
20953 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 2)",
20954 .pme_code = 1474,
20955 .pme_flags = 0x0,
20956 .pme_numasks = 0,
20957 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20958 .pme_ctr = 20,
20959 .pme_event = 0,
20960 .pme_chipno = 2,
20961 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20962 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20963 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20964 },
20965 {
20966 .pme_name = "REQUESTS_0@3",
20967 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 3)",
20968 .pme_code = 1475,
20969 .pme_flags = 0x0,
20970 .pme_numasks = 0,
20971 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20972 .pme_ctr = 20,
20973 .pme_event = 0,
20974 .pme_chipno = 3,
20975 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20976 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20977 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20978 },
20979 {
20980 .pme_name = "REQUESTS_0@4",
20981 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 4)",
20982 .pme_code = 1476,
20983 .pme_flags = 0x0,
20984 .pme_numasks = 0,
20985 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
20986 .pme_ctr = 20,
20987 .pme_event = 0,
20988 .pme_chipno = 4,
20989 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
20990 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
20991 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
20992 },
20993 {
20994 .pme_name = "REQUESTS_0@5",
20995 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 5)",
20996 .pme_code = 1477,
20997 .pme_flags = 0x0,
20998 .pme_numasks = 0,
20999 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21000 .pme_ctr = 20,
21001 .pme_event = 0,
21002 .pme_chipno = 5,
21003 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21004 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21005 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21006 },
21007 {
21008 .pme_name = "REQUESTS_0@6",
21009 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 6)",
21010 .pme_code = 1478,
21011 .pme_flags = 0x0,
21012 .pme_numasks = 0,
21013 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21014 .pme_ctr = 20,
21015 .pme_event = 0,
21016 .pme_chipno = 6,
21017 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21018 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21019 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21020 },
21021 {
21022 .pme_name = "REQUESTS_0@7",
21023 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 7)",
21024 .pme_code = 1479,
21025 .pme_flags = 0x0,
21026 .pme_numasks = 0,
21027 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21028 .pme_ctr = 20,
21029 .pme_event = 0,
21030 .pme_chipno = 7,
21031 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21032 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21033 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21034 },
21035 {
21036 .pme_name = "REQUESTS_0@8",
21037 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 8)",
21038 .pme_code = 1480,
21039 .pme_flags = 0x0,
21040 .pme_numasks = 0,
21041 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21042 .pme_ctr = 20,
21043 .pme_event = 0,
21044 .pme_chipno = 8,
21045 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21046 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21047 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21048 },
21049 {
21050 .pme_name = "REQUESTS_0@9",
21051 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 9)",
21052 .pme_code = 1481,
21053 .pme_flags = 0x0,
21054 .pme_numasks = 0,
21055 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21056 .pme_ctr = 20,
21057 .pme_event = 0,
21058 .pme_chipno = 9,
21059 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21060 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21061 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21062 },
21063 {
21064 .pme_name = "REQUESTS_0@10",
21065 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 10)",
21066 .pme_code = 1482,
21067 .pme_flags = 0x0,
21068 .pme_numasks = 0,
21069 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21070 .pme_ctr = 20,
21071 .pme_event = 0,
21072 .pme_chipno = 10,
21073 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21074 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21075 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21076 },
21077 {
21078 .pme_name = "REQUESTS_0@11",
21079 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 11)",
21080 .pme_code = 1483,
21081 .pme_flags = 0x0,
21082 .pme_numasks = 0,
21083 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21084 .pme_ctr = 20,
21085 .pme_event = 0,
21086 .pme_chipno = 11,
21087 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21088 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21089 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21090 },
21091 {
21092 .pme_name = "REQUESTS_0@12",
21093 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 12)",
21094 .pme_code = 1484,
21095 .pme_flags = 0x0,
21096 .pme_numasks = 0,
21097 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21098 .pme_ctr = 20,
21099 .pme_event = 0,
21100 .pme_chipno = 12,
21101 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21102 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21103 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21104 },
21105 {
21106 .pme_name = "REQUESTS_0@13",
21107 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 13)",
21108 .pme_code = 1485,
21109 .pme_flags = 0x0,
21110 .pme_numasks = 0,
21111 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21112 .pme_ctr = 20,
21113 .pme_event = 0,
21114 .pme_chipno = 13,
21115 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21116 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21117 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21118 },
21119 {
21120 .pme_name = "REQUESTS_0@14",
21121 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 14)",
21122 .pme_code = 1486,
21123 .pme_flags = 0x0,
21124 .pme_numasks = 0,
21125 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21126 .pme_ctr = 20,
21127 .pme_event = 0,
21128 .pme_chipno = 14,
21129 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21130 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21131 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21132 },
21133 {
21134 .pme_name = "REQUESTS_0@15",
21135 .pme_desc = "Read or write requests from port 0 to MDs. (M chip 15)",
21136 .pme_code = 1487,
21137 .pme_flags = 0x0,
21138 .pme_numasks = 0,
21139 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21140 .pme_ctr = 20,
21141 .pme_event = 0,
21142 .pme_chipno = 15,
21143 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21144 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21145 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21146 },
21147 /* M Counter 20 Event 1 */
21148 {
21149 .pme_name = "REQUEST_1DWORD_L3_MISS@0",
21150 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 0)",
21151 .pme_code = 1488,
21152 .pme_flags = 0x0,
21153 .pme_numasks = 0,
21154 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21155 .pme_ctr = 20,
21156 .pme_event = 1,
21157 .pme_chipno = 0,
21158 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21159 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21160 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21161 },
21162 {
21163 .pme_name = "REQUEST_1DWORD_L3_MISS@1",
21164 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 1)",
21165 .pme_code = 1489,
21166 .pme_flags = 0x0,
21167 .pme_numasks = 0,
21168 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21169 .pme_ctr = 20,
21170 .pme_event = 1,
21171 .pme_chipno = 1,
21172 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21173 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21174 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21175 },
21176 {
21177 .pme_name = "REQUEST_1DWORD_L3_MISS@2",
21178 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 2)",
21179 .pme_code = 1490,
21180 .pme_flags = 0x0,
21181 .pme_numasks = 0,
21182 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21183 .pme_ctr = 20,
21184 .pme_event = 1,
21185 .pme_chipno = 2,
21186 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21187 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21188 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21189 },
21190 {
21191 .pme_name = "REQUEST_1DWORD_L3_MISS@3",
21192 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 3)",
21193 .pme_code = 1491,
21194 .pme_flags = 0x0,
21195 .pme_numasks = 0,
21196 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21197 .pme_ctr = 20,
21198 .pme_event = 1,
21199 .pme_chipno = 3,
21200 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21201 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21202 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21203 },
21204 {
21205 .pme_name = "REQUEST_1DWORD_L3_MISS@4",
21206 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 4)",
21207 .pme_code = 1492,
21208 .pme_flags = 0x0,
21209 .pme_numasks = 0,
21210 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21211 .pme_ctr = 20,
21212 .pme_event = 1,
21213 .pme_chipno = 4,
21214 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21215 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21216 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21217 },
21218 {
21219 .pme_name = "REQUEST_1DWORD_L3_MISS@5",
21220 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 5)",
21221 .pme_code = 1493,
21222 .pme_flags = 0x0,
21223 .pme_numasks = 0,
21224 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21225 .pme_ctr = 20,
21226 .pme_event = 1,
21227 .pme_chipno = 5,
21228 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21229 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21230 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21231 },
21232 {
21233 .pme_name = "REQUEST_1DWORD_L3_MISS@6",
21234 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 6)",
21235 .pme_code = 1494,
21236 .pme_flags = 0x0,
21237 .pme_numasks = 0,
21238 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21239 .pme_ctr = 20,
21240 .pme_event = 1,
21241 .pme_chipno = 6,
21242 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21243 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21244 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21245 },
21246 {
21247 .pme_name = "REQUEST_1DWORD_L3_MISS@7",
21248 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 7)",
21249 .pme_code = 1495,
21250 .pme_flags = 0x0,
21251 .pme_numasks = 0,
21252 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21253 .pme_ctr = 20,
21254 .pme_event = 1,
21255 .pme_chipno = 7,
21256 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21257 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21258 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21259 },
21260 {
21261 .pme_name = "REQUEST_1DWORD_L3_MISS@8",
21262 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 8)",
21263 .pme_code = 1496,
21264 .pme_flags = 0x0,
21265 .pme_numasks = 0,
21266 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21267 .pme_ctr = 20,
21268 .pme_event = 1,
21269 .pme_chipno = 8,
21270 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21271 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21272 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21273 },
21274 {
21275 .pme_name = "REQUEST_1DWORD_L3_MISS@9",
21276 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 9)",
21277 .pme_code = 1497,
21278 .pme_flags = 0x0,
21279 .pme_numasks = 0,
21280 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21281 .pme_ctr = 20,
21282 .pme_event = 1,
21283 .pme_chipno = 9,
21284 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21285 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21286 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21287 },
21288 {
21289 .pme_name = "REQUEST_1DWORD_L3_MISS@10",
21290 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 10)",
21291 .pme_code = 1498,
21292 .pme_flags = 0x0,
21293 .pme_numasks = 0,
21294 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21295 .pme_ctr = 20,
21296 .pme_event = 1,
21297 .pme_chipno = 10,
21298 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21299 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21300 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21301 },
21302 {
21303 .pme_name = "REQUEST_1DWORD_L3_MISS@11",
21304 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 11)",
21305 .pme_code = 1499,
21306 .pme_flags = 0x0,
21307 .pme_numasks = 0,
21308 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21309 .pme_ctr = 20,
21310 .pme_event = 1,
21311 .pme_chipno = 11,
21312 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21313 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21314 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21315 },
21316 {
21317 .pme_name = "REQUEST_1DWORD_L3_MISS@12",
21318 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 12)",
21319 .pme_code = 1500,
21320 .pme_flags = 0x0,
21321 .pme_numasks = 0,
21322 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21323 .pme_ctr = 20,
21324 .pme_event = 1,
21325 .pme_chipno = 12,
21326 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21327 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21328 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21329 },
21330 {
21331 .pme_name = "REQUEST_1DWORD_L3_MISS@13",
21332 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 13)",
21333 .pme_code = 1501,
21334 .pme_flags = 0x0,
21335 .pme_numasks = 0,
21336 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21337 .pme_ctr = 20,
21338 .pme_event = 1,
21339 .pme_chipno = 13,
21340 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21341 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21342 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21343 },
21344 {
21345 .pme_name = "REQUEST_1DWORD_L3_MISS@14",
21346 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 14)",
21347 .pme_code = 1502,
21348 .pme_flags = 0x0,
21349 .pme_numasks = 0,
21350 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21351 .pme_ctr = 20,
21352 .pme_event = 1,
21353 .pme_chipno = 14,
21354 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21355 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21356 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21357 },
21358 {
21359 .pme_name = "REQUEST_1DWORD_L3_MISS@15",
21360 .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 15)",
21361 .pme_code = 1503,
21362 .pme_flags = 0x0,
21363 .pme_numasks = 0,
21364 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21365 .pme_ctr = 20,
21366 .pme_event = 1,
21367 .pme_chipno = 15,
21368 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21369 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21370 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21371 },
21372 /* M Counter 20 Event 2 */
21373 {
21374 .pme_name = "MM2_ANY_BANK_BUSY@0",
21375 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 0)",
21376 .pme_code = 1504,
21377 .pme_flags = 0x0,
21378 .pme_numasks = 0,
21379 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21380 .pme_ctr = 20,
21381 .pme_event = 2,
21382 .pme_chipno = 0,
21383 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21384 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21385 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21386 },
21387 {
21388 .pme_name = "MM2_ANY_BANK_BUSY@1",
21389 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 1)",
21390 .pme_code = 1505,
21391 .pme_flags = 0x0,
21392 .pme_numasks = 0,
21393 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21394 .pme_ctr = 20,
21395 .pme_event = 2,
21396 .pme_chipno = 1,
21397 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21398 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21399 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21400 },
21401 {
21402 .pme_name = "MM2_ANY_BANK_BUSY@2",
21403 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 2)",
21404 .pme_code = 1506,
21405 .pme_flags = 0x0,
21406 .pme_numasks = 0,
21407 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21408 .pme_ctr = 20,
21409 .pme_event = 2,
21410 .pme_chipno = 2,
21411 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21412 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21413 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21414 },
21415 {
21416 .pme_name = "MM2_ANY_BANK_BUSY@3",
21417 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 3)",
21418 .pme_code = 1507,
21419 .pme_flags = 0x0,
21420 .pme_numasks = 0,
21421 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21422 .pme_ctr = 20,
21423 .pme_event = 2,
21424 .pme_chipno = 3,
21425 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21426 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21427 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21428 },
21429 {
21430 .pme_name = "MM2_ANY_BANK_BUSY@4",
21431 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 4)",
21432 .pme_code = 1508,
21433 .pme_flags = 0x0,
21434 .pme_numasks = 0,
21435 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21436 .pme_ctr = 20,
21437 .pme_event = 2,
21438 .pme_chipno = 4,
21439 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21440 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21441 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21442 },
21443 {
21444 .pme_name = "MM2_ANY_BANK_BUSY@5",
21445 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 5)",
21446 .pme_code = 1509,
21447 .pme_flags = 0x0,
21448 .pme_numasks = 0,
21449 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21450 .pme_ctr = 20,
21451 .pme_event = 2,
21452 .pme_chipno = 5,
21453 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21454 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21455 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21456 },
21457 {
21458 .pme_name = "MM2_ANY_BANK_BUSY@6",
21459 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 6)",
21460 .pme_code = 1510,
21461 .pme_flags = 0x0,
21462 .pme_numasks = 0,
21463 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21464 .pme_ctr = 20,
21465 .pme_event = 2,
21466 .pme_chipno = 6,
21467 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21468 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21469 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21470 },
21471 {
21472 .pme_name = "MM2_ANY_BANK_BUSY@7",
21473 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 7)",
21474 .pme_code = 1511,
21475 .pme_flags = 0x0,
21476 .pme_numasks = 0,
21477 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21478 .pme_ctr = 20,
21479 .pme_event = 2,
21480 .pme_chipno = 7,
21481 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21482 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21483 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21484 },
21485 {
21486 .pme_name = "MM2_ANY_BANK_BUSY@8",
21487 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 8)",
21488 .pme_code = 1512,
21489 .pme_flags = 0x0,
21490 .pme_numasks = 0,
21491 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21492 .pme_ctr = 20,
21493 .pme_event = 2,
21494 .pme_chipno = 8,
21495 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21496 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21497 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21498 },
21499 {
21500 .pme_name = "MM2_ANY_BANK_BUSY@9",
21501 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 9)",
21502 .pme_code = 1513,
21503 .pme_flags = 0x0,
21504 .pme_numasks = 0,
21505 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21506 .pme_ctr = 20,
21507 .pme_event = 2,
21508 .pme_chipno = 9,
21509 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21510 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21511 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21512 },
21513 {
21514 .pme_name = "MM2_ANY_BANK_BUSY@10",
21515 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 10)",
21516 .pme_code = 1514,
21517 .pme_flags = 0x0,
21518 .pme_numasks = 0,
21519 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21520 .pme_ctr = 20,
21521 .pme_event = 2,
21522 .pme_chipno = 10,
21523 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21524 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21525 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21526 },
21527 {
21528 .pme_name = "MM2_ANY_BANK_BUSY@11",
21529 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 11)",
21530 .pme_code = 1515,
21531 .pme_flags = 0x0,
21532 .pme_numasks = 0,
21533 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21534 .pme_ctr = 20,
21535 .pme_event = 2,
21536 .pme_chipno = 11,
21537 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21538 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21539 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21540 },
21541 {
21542 .pme_name = "MM2_ANY_BANK_BUSY@12",
21543 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 12)",
21544 .pme_code = 1516,
21545 .pme_flags = 0x0,
21546 .pme_numasks = 0,
21547 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21548 .pme_ctr = 20,
21549 .pme_event = 2,
21550 .pme_chipno = 12,
21551 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21552 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21553 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21554 },
21555 {
21556 .pme_name = "MM2_ANY_BANK_BUSY@13",
21557 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 13)",
21558 .pme_code = 1517,
21559 .pme_flags = 0x0,
21560 .pme_numasks = 0,
21561 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21562 .pme_ctr = 20,
21563 .pme_event = 2,
21564 .pme_chipno = 13,
21565 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21566 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21567 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21568 },
21569 {
21570 .pme_name = "MM2_ANY_BANK_BUSY@14",
21571 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 14)",
21572 .pme_code = 1518,
21573 .pme_flags = 0x0,
21574 .pme_numasks = 0,
21575 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21576 .pme_ctr = 20,
21577 .pme_event = 2,
21578 .pme_chipno = 14,
21579 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21580 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21581 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21582 },
21583 {
21584 .pme_name = "MM2_ANY_BANK_BUSY@15",
21585 .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 15)",
21586 .pme_code = 1519,
21587 .pme_flags = 0x0,
21588 .pme_numasks = 0,
21589 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21590 .pme_ctr = 20,
21591 .pme_event = 2,
21592 .pme_chipno = 15,
21593 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21594 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21595 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21596 },
21597 /* M Counter 20 Event 3 */
21598 {
21599 .pme_name = "W_OUT_QUEUE_BP_0@0",
21600 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)",
21601 .pme_code = 1520,
21602 .pme_flags = 0x0,
21603 .pme_numasks = 0,
21604 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21605 .pme_ctr = 20,
21606 .pme_event = 3,
21607 .pme_chipno = 0,
21608 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21609 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21610 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21611 },
21612 {
21613 .pme_name = "W_OUT_QUEUE_BP_0@1",
21614 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)",
21615 .pme_code = 1521,
21616 .pme_flags = 0x0,
21617 .pme_numasks = 0,
21618 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21619 .pme_ctr = 20,
21620 .pme_event = 3,
21621 .pme_chipno = 1,
21622 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21623 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21624 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21625 },
21626 {
21627 .pme_name = "W_OUT_QUEUE_BP_0@2",
21628 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)",
21629 .pme_code = 1522,
21630 .pme_flags = 0x0,
21631 .pme_numasks = 0,
21632 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21633 .pme_ctr = 20,
21634 .pme_event = 3,
21635 .pme_chipno = 2,
21636 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21637 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21638 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21639 },
21640 {
21641 .pme_name = "W_OUT_QUEUE_BP_0@3",
21642 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)",
21643 .pme_code = 1523,
21644 .pme_flags = 0x0,
21645 .pme_numasks = 0,
21646 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21647 .pme_ctr = 20,
21648 .pme_event = 3,
21649 .pme_chipno = 3,
21650 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21651 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21652 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21653 },
21654 {
21655 .pme_name = "W_OUT_QUEUE_BP_0@4",
21656 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)",
21657 .pme_code = 1524,
21658 .pme_flags = 0x0,
21659 .pme_numasks = 0,
21660 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21661 .pme_ctr = 20,
21662 .pme_event = 3,
21663 .pme_chipno = 4,
21664 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21665 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21666 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21667 },
21668 {
21669 .pme_name = "W_OUT_QUEUE_BP_0@5",
21670 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)",
21671 .pme_code = 1525,
21672 .pme_flags = 0x0,
21673 .pme_numasks = 0,
21674 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21675 .pme_ctr = 20,
21676 .pme_event = 3,
21677 .pme_chipno = 5,
21678 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21679 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21680 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21681 },
21682 {
21683 .pme_name = "W_OUT_QUEUE_BP_0@6",
21684 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)",
21685 .pme_code = 1526,
21686 .pme_flags = 0x0,
21687 .pme_numasks = 0,
21688 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21689 .pme_ctr = 20,
21690 .pme_event = 3,
21691 .pme_chipno = 6,
21692 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21693 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21694 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21695 },
21696 {
21697 .pme_name = "W_OUT_QUEUE_BP_0@7",
21698 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)",
21699 .pme_code = 1527,
21700 .pme_flags = 0x0,
21701 .pme_numasks = 0,
21702 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21703 .pme_ctr = 20,
21704 .pme_event = 3,
21705 .pme_chipno = 7,
21706 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21707 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21708 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21709 },
21710 {
21711 .pme_name = "W_OUT_QUEUE_BP_0@8",
21712 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)",
21713 .pme_code = 1528,
21714 .pme_flags = 0x0,
21715 .pme_numasks = 0,
21716 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21717 .pme_ctr = 20,
21718 .pme_event = 3,
21719 .pme_chipno = 8,
21720 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21721 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21722 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21723 },
21724 {
21725 .pme_name = "W_OUT_QUEUE_BP_0@9",
21726 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)",
21727 .pme_code = 1529,
21728 .pme_flags = 0x0,
21729 .pme_numasks = 0,
21730 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21731 .pme_ctr = 20,
21732 .pme_event = 3,
21733 .pme_chipno = 9,
21734 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21735 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21736 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21737 },
21738 {
21739 .pme_name = "W_OUT_QUEUE_BP_0@10",
21740 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)",
21741 .pme_code = 1530,
21742 .pme_flags = 0x0,
21743 .pme_numasks = 0,
21744 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21745 .pme_ctr = 20,
21746 .pme_event = 3,
21747 .pme_chipno = 10,
21748 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21749 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21750 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21751 },
21752 {
21753 .pme_name = "W_OUT_QUEUE_BP_0@11",
21754 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)",
21755 .pme_code = 1531,
21756 .pme_flags = 0x0,
21757 .pme_numasks = 0,
21758 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21759 .pme_ctr = 20,
21760 .pme_event = 3,
21761 .pme_chipno = 11,
21762 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21763 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21764 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21765 },
21766 {
21767 .pme_name = "W_OUT_QUEUE_BP_0@12",
21768 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)",
21769 .pme_code = 1532,
21770 .pme_flags = 0x0,
21771 .pme_numasks = 0,
21772 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21773 .pme_ctr = 20,
21774 .pme_event = 3,
21775 .pme_chipno = 12,
21776 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21777 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21778 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21779 },
21780 {
21781 .pme_name = "W_OUT_QUEUE_BP_0@13",
21782 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)",
21783 .pme_code = 1533,
21784 .pme_flags = 0x0,
21785 .pme_numasks = 0,
21786 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21787 .pme_ctr = 20,
21788 .pme_event = 3,
21789 .pme_chipno = 13,
21790 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21791 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21792 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21793 },
21794 {
21795 .pme_name = "W_OUT_QUEUE_BP_0@14",
21796 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)",
21797 .pme_code = 1534,
21798 .pme_flags = 0x0,
21799 .pme_numasks = 0,
21800 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21801 .pme_ctr = 20,
21802 .pme_event = 3,
21803 .pme_chipno = 14,
21804 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21805 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21806 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21807 },
21808 {
21809 .pme_name = "W_OUT_QUEUE_BP_0@15",
21810 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)",
21811 .pme_code = 1535,
21812 .pme_flags = 0x0,
21813 .pme_numasks = 0,
21814 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21815 .pme_ctr = 20,
21816 .pme_event = 3,
21817 .pme_chipno = 15,
21818 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21819 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21820 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21821 },
21822 /* M Counter 21 Event 0 */
21823 {
21824 .pme_name = "REQUESTS_1@0",
21825 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 0)",
21826 .pme_code = 1536,
21827 .pme_flags = 0x0,
21828 .pme_numasks = 0,
21829 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21830 .pme_ctr = 21,
21831 .pme_event = 0,
21832 .pme_chipno = 0,
21833 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21834 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21835 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21836 },
21837 {
21838 .pme_name = "REQUESTS_1@1",
21839 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 1)",
21840 .pme_code = 1537,
21841 .pme_flags = 0x0,
21842 .pme_numasks = 0,
21843 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21844 .pme_ctr = 21,
21845 .pme_event = 0,
21846 .pme_chipno = 1,
21847 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21848 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21849 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21850 },
21851 {
21852 .pme_name = "REQUESTS_1@2",
21853 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 2)",
21854 .pme_code = 1538,
21855 .pme_flags = 0x0,
21856 .pme_numasks = 0,
21857 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21858 .pme_ctr = 21,
21859 .pme_event = 0,
21860 .pme_chipno = 2,
21861 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21862 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21863 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21864 },
21865 {
21866 .pme_name = "REQUESTS_1@3",
21867 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 3)",
21868 .pme_code = 1539,
21869 .pme_flags = 0x0,
21870 .pme_numasks = 0,
21871 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21872 .pme_ctr = 21,
21873 .pme_event = 0,
21874 .pme_chipno = 3,
21875 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21876 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21877 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21878 },
21879 {
21880 .pme_name = "REQUESTS_1@4",
21881 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 4)",
21882 .pme_code = 1540,
21883 .pme_flags = 0x0,
21884 .pme_numasks = 0,
21885 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21886 .pme_ctr = 21,
21887 .pme_event = 0,
21888 .pme_chipno = 4,
21889 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21890 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21891 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21892 },
21893 {
21894 .pme_name = "REQUESTS_1@5",
21895 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 5)",
21896 .pme_code = 1541,
21897 .pme_flags = 0x0,
21898 .pme_numasks = 0,
21899 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21900 .pme_ctr = 21,
21901 .pme_event = 0,
21902 .pme_chipno = 5,
21903 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21904 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21905 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21906 },
21907 {
21908 .pme_name = "REQUESTS_1@6",
21909 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 6)",
21910 .pme_code = 1542,
21911 .pme_flags = 0x0,
21912 .pme_numasks = 0,
21913 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21914 .pme_ctr = 21,
21915 .pme_event = 0,
21916 .pme_chipno = 6,
21917 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21918 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21919 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21920 },
21921 {
21922 .pme_name = "REQUESTS_1@7",
21923 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 7)",
21924 .pme_code = 1543,
21925 .pme_flags = 0x0,
21926 .pme_numasks = 0,
21927 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21928 .pme_ctr = 21,
21929 .pme_event = 0,
21930 .pme_chipno = 7,
21931 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21932 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21933 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21934 },
21935 {
21936 .pme_name = "REQUESTS_1@8",
21937 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 8)",
21938 .pme_code = 1544,
21939 .pme_flags = 0x0,
21940 .pme_numasks = 0,
21941 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21942 .pme_ctr = 21,
21943 .pme_event = 0,
21944 .pme_chipno = 8,
21945 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21946 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21947 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21948 },
21949 {
21950 .pme_name = "REQUESTS_1@9",
21951 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 9)",
21952 .pme_code = 1545,
21953 .pme_flags = 0x0,
21954 .pme_numasks = 0,
21955 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21956 .pme_ctr = 21,
21957 .pme_event = 0,
21958 .pme_chipno = 9,
21959 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21960 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21961 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21962 },
21963 {
21964 .pme_name = "REQUESTS_1@10",
21965 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 10)",
21966 .pme_code = 1546,
21967 .pme_flags = 0x0,
21968 .pme_numasks = 0,
21969 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21970 .pme_ctr = 21,
21971 .pme_event = 0,
21972 .pme_chipno = 10,
21973 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21974 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21975 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21976 },
21977 {
21978 .pme_name = "REQUESTS_1@11",
21979 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 11)",
21980 .pme_code = 1547,
21981 .pme_flags = 0x0,
21982 .pme_numasks = 0,
21983 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21984 .pme_ctr = 21,
21985 .pme_event = 0,
21986 .pme_chipno = 11,
21987 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
21988 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
21989 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
21990 },
21991 {
21992 .pme_name = "REQUESTS_1@12",
21993 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 12)",
21994 .pme_code = 1548,
21995 .pme_flags = 0x0,
21996 .pme_numasks = 0,
21997 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
21998 .pme_ctr = 21,
21999 .pme_event = 0,
22000 .pme_chipno = 12,
22001 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22002 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22003 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22004 },
22005 {
22006 .pme_name = "REQUESTS_1@13",
22007 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 13)",
22008 .pme_code = 1549,
22009 .pme_flags = 0x0,
22010 .pme_numasks = 0,
22011 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22012 .pme_ctr = 21,
22013 .pme_event = 0,
22014 .pme_chipno = 13,
22015 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22016 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22017 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22018 },
22019 {
22020 .pme_name = "REQUESTS_1@14",
22021 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 14)",
22022 .pme_code = 1550,
22023 .pme_flags = 0x0,
22024 .pme_numasks = 0,
22025 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22026 .pme_ctr = 21,
22027 .pme_event = 0,
22028 .pme_chipno = 14,
22029 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22030 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22031 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22032 },
22033 {
22034 .pme_name = "REQUESTS_1@15",
22035 .pme_desc = "Read or write requests from port 1 to MDs. (M chip 15)",
22036 .pme_code = 1551,
22037 .pme_flags = 0x0,
22038 .pme_numasks = 0,
22039 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22040 .pme_ctr = 21,
22041 .pme_event = 0,
22042 .pme_chipno = 15,
22043 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22044 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22045 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22046 },
22047 /* M Counter 21 Event 1 */
22048 {
22049 .pme_name = "REQUEST_4DWORDS_L3_MISS@0",
22050 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 0)",
22051 .pme_code = 1552,
22052 .pme_flags = 0x0,
22053 .pme_numasks = 0,
22054 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22055 .pme_ctr = 21,
22056 .pme_event = 1,
22057 .pme_chipno = 0,
22058 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22059 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22060 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22061 },
22062 {
22063 .pme_name = "REQUEST_4DWORDS_L3_MISS@1",
22064 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 1)",
22065 .pme_code = 1553,
22066 .pme_flags = 0x0,
22067 .pme_numasks = 0,
22068 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22069 .pme_ctr = 21,
22070 .pme_event = 1,
22071 .pme_chipno = 1,
22072 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22073 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22074 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22075 },
22076 {
22077 .pme_name = "REQUEST_4DWORDS_L3_MISS@2",
22078 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 2)",
22079 .pme_code = 1554,
22080 .pme_flags = 0x0,
22081 .pme_numasks = 0,
22082 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22083 .pme_ctr = 21,
22084 .pme_event = 1,
22085 .pme_chipno = 2,
22086 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22087 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22088 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22089 },
22090 {
22091 .pme_name = "REQUEST_4DWORDS_L3_MISS@3",
22092 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 3)",
22093 .pme_code = 1555,
22094 .pme_flags = 0x0,
22095 .pme_numasks = 0,
22096 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22097 .pme_ctr = 21,
22098 .pme_event = 1,
22099 .pme_chipno = 3,
22100 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22101 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22102 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22103 },
22104 {
22105 .pme_name = "REQUEST_4DWORDS_L3_MISS@4",
22106 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 4)",
22107 .pme_code = 1556,
22108 .pme_flags = 0x0,
22109 .pme_numasks = 0,
22110 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22111 .pme_ctr = 21,
22112 .pme_event = 1,
22113 .pme_chipno = 4,
22114 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22115 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22116 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22117 },
22118 {
22119 .pme_name = "REQUEST_4DWORDS_L3_MISS@5",
22120 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 5)",
22121 .pme_code = 1557,
22122 .pme_flags = 0x0,
22123 .pme_numasks = 0,
22124 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22125 .pme_ctr = 21,
22126 .pme_event = 1,
22127 .pme_chipno = 5,
22128 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22129 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22130 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22131 },
22132 {
22133 .pme_name = "REQUEST_4DWORDS_L3_MISS@6",
22134 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 6)",
22135 .pme_code = 1558,
22136 .pme_flags = 0x0,
22137 .pme_numasks = 0,
22138 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22139 .pme_ctr = 21,
22140 .pme_event = 1,
22141 .pme_chipno = 6,
22142 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22143 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22144 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22145 },
22146 {
22147 .pme_name = "REQUEST_4DWORDS_L3_MISS@7",
22148 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 7)",
22149 .pme_code = 1559,
22150 .pme_flags = 0x0,
22151 .pme_numasks = 0,
22152 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22153 .pme_ctr = 21,
22154 .pme_event = 1,
22155 .pme_chipno = 7,
22156 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22157 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22158 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22159 },
22160 {
22161 .pme_name = "REQUEST_4DWORDS_L3_MISS@8",
22162 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 8)",
22163 .pme_code = 1560,
22164 .pme_flags = 0x0,
22165 .pme_numasks = 0,
22166 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22167 .pme_ctr = 21,
22168 .pme_event = 1,
22169 .pme_chipno = 8,
22170 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22171 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22172 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22173 },
22174 {
22175 .pme_name = "REQUEST_4DWORDS_L3_MISS@9",
22176 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 9)",
22177 .pme_code = 1561,
22178 .pme_flags = 0x0,
22179 .pme_numasks = 0,
22180 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22181 .pme_ctr = 21,
22182 .pme_event = 1,
22183 .pme_chipno = 9,
22184 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22185 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22186 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22187 },
22188 {
22189 .pme_name = "REQUEST_4DWORDS_L3_MISS@10",
22190 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 10)",
22191 .pme_code = 1562,
22192 .pme_flags = 0x0,
22193 .pme_numasks = 0,
22194 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22195 .pme_ctr = 21,
22196 .pme_event = 1,
22197 .pme_chipno = 10,
22198 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22199 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22200 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22201 },
22202 {
22203 .pme_name = "REQUEST_4DWORDS_L3_MISS@11",
22204 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 11)",
22205 .pme_code = 1563,
22206 .pme_flags = 0x0,
22207 .pme_numasks = 0,
22208 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22209 .pme_ctr = 21,
22210 .pme_event = 1,
22211 .pme_chipno = 11,
22212 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22213 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22214 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22215 },
22216 {
22217 .pme_name = "REQUEST_4DWORDS_L3_MISS@12",
22218 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 12)",
22219 .pme_code = 1564,
22220 .pme_flags = 0x0,
22221 .pme_numasks = 0,
22222 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22223 .pme_ctr = 21,
22224 .pme_event = 1,
22225 .pme_chipno = 12,
22226 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22227 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22228 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22229 },
22230 {
22231 .pme_name = "REQUEST_4DWORDS_L3_MISS@13",
22232 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 13)",
22233 .pme_code = 1565,
22234 .pme_flags = 0x0,
22235 .pme_numasks = 0,
22236 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22237 .pme_ctr = 21,
22238 .pme_event = 1,
22239 .pme_chipno = 13,
22240 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22241 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22242 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22243 },
22244 {
22245 .pme_name = "REQUEST_4DWORDS_L3_MISS@14",
22246 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 14)",
22247 .pme_code = 1566,
22248 .pme_flags = 0x0,
22249 .pme_numasks = 0,
22250 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22251 .pme_ctr = 21,
22252 .pme_event = 1,
22253 .pme_chipno = 14,
22254 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22255 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22256 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22257 },
22258 {
22259 .pme_name = "REQUEST_4DWORDS_L3_MISS@15",
22260 .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 15)",
22261 .pme_code = 1567,
22262 .pme_flags = 0x0,
22263 .pme_numasks = 0,
22264 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22265 .pme_ctr = 21,
22266 .pme_event = 1,
22267 .pme_chipno = 15,
22268 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22269 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22270 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22271 },
22272 /* M Counter 21 Event 2 */
22273 {
22274 .pme_name = "MM2_ACCUM_BANK_BUSY@0",
22275 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)",
22276 .pme_code = 1568,
22277 .pme_flags = 0x0,
22278 .pme_numasks = 0,
22279 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22280 .pme_ctr = 21,
22281 .pme_event = 2,
22282 .pme_chipno = 0,
22283 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22284 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22285 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22286 },
22287 {
22288 .pme_name = "MM2_ACCUM_BANK_BUSY@1",
22289 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)",
22290 .pme_code = 1569,
22291 .pme_flags = 0x0,
22292 .pme_numasks = 0,
22293 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22294 .pme_ctr = 21,
22295 .pme_event = 2,
22296 .pme_chipno = 1,
22297 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22298 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22299 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22300 },
22301 {
22302 .pme_name = "MM2_ACCUM_BANK_BUSY@2",
22303 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)",
22304 .pme_code = 1570,
22305 .pme_flags = 0x0,
22306 .pme_numasks = 0,
22307 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22308 .pme_ctr = 21,
22309 .pme_event = 2,
22310 .pme_chipno = 2,
22311 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22312 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22313 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22314 },
22315 {
22316 .pme_name = "MM2_ACCUM_BANK_BUSY@3",
22317 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)",
22318 .pme_code = 1571,
22319 .pme_flags = 0x0,
22320 .pme_numasks = 0,
22321 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22322 .pme_ctr = 21,
22323 .pme_event = 2,
22324 .pme_chipno = 3,
22325 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22326 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22327 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22328 },
22329 {
22330 .pme_name = "MM2_ACCUM_BANK_BUSY@4",
22331 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)",
22332 .pme_code = 1572,
22333 .pme_flags = 0x0,
22334 .pme_numasks = 0,
22335 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22336 .pme_ctr = 21,
22337 .pme_event = 2,
22338 .pme_chipno = 4,
22339 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22340 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22341 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22342 },
22343 {
22344 .pme_name = "MM2_ACCUM_BANK_BUSY@5",
22345 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)",
22346 .pme_code = 1573,
22347 .pme_flags = 0x0,
22348 .pme_numasks = 0,
22349 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22350 .pme_ctr = 21,
22351 .pme_event = 2,
22352 .pme_chipno = 5,
22353 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22354 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22355 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22356 },
22357 {
22358 .pme_name = "MM2_ACCUM_BANK_BUSY@6",
22359 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)",
22360 .pme_code = 1574,
22361 .pme_flags = 0x0,
22362 .pme_numasks = 0,
22363 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22364 .pme_ctr = 21,
22365 .pme_event = 2,
22366 .pme_chipno = 6,
22367 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22368 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22369 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22370 },
22371 {
22372 .pme_name = "MM2_ACCUM_BANK_BUSY@7",
22373 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)",
22374 .pme_code = 1575,
22375 .pme_flags = 0x0,
22376 .pme_numasks = 0,
22377 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22378 .pme_ctr = 21,
22379 .pme_event = 2,
22380 .pme_chipno = 7,
22381 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22382 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22383 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22384 },
22385 {
22386 .pme_name = "MM2_ACCUM_BANK_BUSY@8",
22387 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)",
22388 .pme_code = 1576,
22389 .pme_flags = 0x0,
22390 .pme_numasks = 0,
22391 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22392 .pme_ctr = 21,
22393 .pme_event = 2,
22394 .pme_chipno = 8,
22395 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22396 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22397 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22398 },
22399 {
22400 .pme_name = "MM2_ACCUM_BANK_BUSY@9",
22401 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)",
22402 .pme_code = 1577,
22403 .pme_flags = 0x0,
22404 .pme_numasks = 0,
22405 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22406 .pme_ctr = 21,
22407 .pme_event = 2,
22408 .pme_chipno = 9,
22409 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22410 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22411 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22412 },
22413 {
22414 .pme_name = "MM2_ACCUM_BANK_BUSY@10",
22415 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)",
22416 .pme_code = 1578,
22417 .pme_flags = 0x0,
22418 .pme_numasks = 0,
22419 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22420 .pme_ctr = 21,
22421 .pme_event = 2,
22422 .pme_chipno = 10,
22423 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22424 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22425 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22426 },
22427 {
22428 .pme_name = "MM2_ACCUM_BANK_BUSY@11",
22429 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)",
22430 .pme_code = 1579,
22431 .pme_flags = 0x0,
22432 .pme_numasks = 0,
22433 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22434 .pme_ctr = 21,
22435 .pme_event = 2,
22436 .pme_chipno = 11,
22437 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22438 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22439 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22440 },
22441 {
22442 .pme_name = "MM2_ACCUM_BANK_BUSY@12",
22443 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)",
22444 .pme_code = 1580,
22445 .pme_flags = 0x0,
22446 .pme_numasks = 0,
22447 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22448 .pme_ctr = 21,
22449 .pme_event = 2,
22450 .pme_chipno = 12,
22451 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22452 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22453 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22454 },
22455 {
22456 .pme_name = "MM2_ACCUM_BANK_BUSY@13",
22457 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)",
22458 .pme_code = 1581,
22459 .pme_flags = 0x0,
22460 .pme_numasks = 0,
22461 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22462 .pme_ctr = 21,
22463 .pme_event = 2,
22464 .pme_chipno = 13,
22465 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22466 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22467 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22468 },
22469 {
22470 .pme_name = "MM2_ACCUM_BANK_BUSY@14",
22471 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)",
22472 .pme_code = 1582,
22473 .pme_flags = 0x0,
22474 .pme_numasks = 0,
22475 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22476 .pme_ctr = 21,
22477 .pme_event = 2,
22478 .pme_chipno = 14,
22479 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22480 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22481 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22482 },
22483 {
22484 .pme_name = "MM2_ACCUM_BANK_BUSY@15",
22485 .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)",
22486 .pme_code = 1583,
22487 .pme_flags = 0x0,
22488 .pme_numasks = 0,
22489 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22490 .pme_ctr = 21,
22491 .pme_event = 2,
22492 .pme_chipno = 15,
22493 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22494 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22495 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22496 },
22497 /* M Counter 21 Event 3 */
22498 {
22499 .pme_name = "W_OUT_QUEUE_BP_1@0",
22500 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)",
22501 .pme_code = 1584,
22502 .pme_flags = 0x0,
22503 .pme_numasks = 0,
22504 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22505 .pme_ctr = 21,
22506 .pme_event = 3,
22507 .pme_chipno = 0,
22508 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22509 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22510 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22511 },
22512 {
22513 .pme_name = "W_OUT_QUEUE_BP_1@1",
22514 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)",
22515 .pme_code = 1585,
22516 .pme_flags = 0x0,
22517 .pme_numasks = 0,
22518 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22519 .pme_ctr = 21,
22520 .pme_event = 3,
22521 .pme_chipno = 1,
22522 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22523 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22524 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22525 },
22526 {
22527 .pme_name = "W_OUT_QUEUE_BP_1@2",
22528 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)",
22529 .pme_code = 1586,
22530 .pme_flags = 0x0,
22531 .pme_numasks = 0,
22532 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22533 .pme_ctr = 21,
22534 .pme_event = 3,
22535 .pme_chipno = 2,
22536 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22537 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22538 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22539 },
22540 {
22541 .pme_name = "W_OUT_QUEUE_BP_1@3",
22542 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)",
22543 .pme_code = 1587,
22544 .pme_flags = 0x0,
22545 .pme_numasks = 0,
22546 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22547 .pme_ctr = 21,
22548 .pme_event = 3,
22549 .pme_chipno = 3,
22550 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22551 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22552 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22553 },
22554 {
22555 .pme_name = "W_OUT_QUEUE_BP_1@4",
22556 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)",
22557 .pme_code = 1588,
22558 .pme_flags = 0x0,
22559 .pme_numasks = 0,
22560 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22561 .pme_ctr = 21,
22562 .pme_event = 3,
22563 .pme_chipno = 4,
22564 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22565 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22566 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22567 },
22568 {
22569 .pme_name = "W_OUT_QUEUE_BP_1@5",
22570 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)",
22571 .pme_code = 1589,
22572 .pme_flags = 0x0,
22573 .pme_numasks = 0,
22574 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22575 .pme_ctr = 21,
22576 .pme_event = 3,
22577 .pme_chipno = 5,
22578 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22579 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22580 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22581 },
22582 {
22583 .pme_name = "W_OUT_QUEUE_BP_1@6",
22584 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)",
22585 .pme_code = 1590,
22586 .pme_flags = 0x0,
22587 .pme_numasks = 0,
22588 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22589 .pme_ctr = 21,
22590 .pme_event = 3,
22591 .pme_chipno = 6,
22592 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22593 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22594 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22595 },
22596 {
22597 .pme_name = "W_OUT_QUEUE_BP_1@7",
22598 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)",
22599 .pme_code = 1591,
22600 .pme_flags = 0x0,
22601 .pme_numasks = 0,
22602 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22603 .pme_ctr = 21,
22604 .pme_event = 3,
22605 .pme_chipno = 7,
22606 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22607 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22608 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22609 },
22610 {
22611 .pme_name = "W_OUT_QUEUE_BP_1@8",
22612 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)",
22613 .pme_code = 1592,
22614 .pme_flags = 0x0,
22615 .pme_numasks = 0,
22616 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22617 .pme_ctr = 21,
22618 .pme_event = 3,
22619 .pme_chipno = 8,
22620 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22621 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22622 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22623 },
22624 {
22625 .pme_name = "W_OUT_QUEUE_BP_1@9",
22626 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)",
22627 .pme_code = 1593,
22628 .pme_flags = 0x0,
22629 .pme_numasks = 0,
22630 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22631 .pme_ctr = 21,
22632 .pme_event = 3,
22633 .pme_chipno = 9,
22634 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22635 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22636 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22637 },
22638 {
22639 .pme_name = "W_OUT_QUEUE_BP_1@10",
22640 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)",
22641 .pme_code = 1594,
22642 .pme_flags = 0x0,
22643 .pme_numasks = 0,
22644 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22645 .pme_ctr = 21,
22646 .pme_event = 3,
22647 .pme_chipno = 10,
22648 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22649 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22650 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22651 },
22652 {
22653 .pme_name = "W_OUT_QUEUE_BP_1@11",
22654 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)",
22655 .pme_code = 1595,
22656 .pme_flags = 0x0,
22657 .pme_numasks = 0,
22658 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22659 .pme_ctr = 21,
22660 .pme_event = 3,
22661 .pme_chipno = 11,
22662 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22663 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22664 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22665 },
22666 {
22667 .pme_name = "W_OUT_QUEUE_BP_1@12",
22668 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)",
22669 .pme_code = 1596,
22670 .pme_flags = 0x0,
22671 .pme_numasks = 0,
22672 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22673 .pme_ctr = 21,
22674 .pme_event = 3,
22675 .pme_chipno = 12,
22676 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22677 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22678 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22679 },
22680 {
22681 .pme_name = "W_OUT_QUEUE_BP_1@13",
22682 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)",
22683 .pme_code = 1597,
22684 .pme_flags = 0x0,
22685 .pme_numasks = 0,
22686 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22687 .pme_ctr = 21,
22688 .pme_event = 3,
22689 .pme_chipno = 13,
22690 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22691 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22692 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22693 },
22694 {
22695 .pme_name = "W_OUT_QUEUE_BP_1@14",
22696 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)",
22697 .pme_code = 1598,
22698 .pme_flags = 0x0,
22699 .pme_numasks = 0,
22700 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22701 .pme_ctr = 21,
22702 .pme_event = 3,
22703 .pme_chipno = 14,
22704 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22705 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22706 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22707 },
22708 {
22709 .pme_name = "W_OUT_QUEUE_BP_1@15",
22710 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)",
22711 .pme_code = 1599,
22712 .pme_flags = 0x0,
22713 .pme_numasks = 0,
22714 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22715 .pme_ctr = 21,
22716 .pme_event = 3,
22717 .pme_chipno = 15,
22718 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22719 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22720 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22721 },
22722 /* M Counter 22 Event 0 */
22723 {
22724 .pme_name = "REQUESTS_2@0",
22725 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 0)",
22726 .pme_code = 1600,
22727 .pme_flags = 0x0,
22728 .pme_numasks = 0,
22729 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22730 .pme_ctr = 22,
22731 .pme_event = 0,
22732 .pme_chipno = 0,
22733 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22734 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22735 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22736 },
22737 {
22738 .pme_name = "REQUESTS_2@1",
22739 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 1)",
22740 .pme_code = 1601,
22741 .pme_flags = 0x0,
22742 .pme_numasks = 0,
22743 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22744 .pme_ctr = 22,
22745 .pme_event = 0,
22746 .pme_chipno = 1,
22747 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22748 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22749 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22750 },
22751 {
22752 .pme_name = "REQUESTS_2@2",
22753 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 2)",
22754 .pme_code = 1602,
22755 .pme_flags = 0x0,
22756 .pme_numasks = 0,
22757 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22758 .pme_ctr = 22,
22759 .pme_event = 0,
22760 .pme_chipno = 2,
22761 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22762 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22763 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22764 },
22765 {
22766 .pme_name = "REQUESTS_2@3",
22767 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 3)",
22768 .pme_code = 1603,
22769 .pme_flags = 0x0,
22770 .pme_numasks = 0,
22771 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22772 .pme_ctr = 22,
22773 .pme_event = 0,
22774 .pme_chipno = 3,
22775 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22776 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22777 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22778 },
22779 {
22780 .pme_name = "REQUESTS_2@4",
22781 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 4)",
22782 .pme_code = 1604,
22783 .pme_flags = 0x0,
22784 .pme_numasks = 0,
22785 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22786 .pme_ctr = 22,
22787 .pme_event = 0,
22788 .pme_chipno = 4,
22789 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22790 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22791 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22792 },
22793 {
22794 .pme_name = "REQUESTS_2@5",
22795 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 5)",
22796 .pme_code = 1605,
22797 .pme_flags = 0x0,
22798 .pme_numasks = 0,
22799 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22800 .pme_ctr = 22,
22801 .pme_event = 0,
22802 .pme_chipno = 5,
22803 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22804 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22805 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22806 },
22807 {
22808 .pme_name = "REQUESTS_2@6",
22809 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 6)",
22810 .pme_code = 1606,
22811 .pme_flags = 0x0,
22812 .pme_numasks = 0,
22813 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22814 .pme_ctr = 22,
22815 .pme_event = 0,
22816 .pme_chipno = 6,
22817 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22818 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22819 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22820 },
22821 {
22822 .pme_name = "REQUESTS_2@7",
22823 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 7)",
22824 .pme_code = 1607,
22825 .pme_flags = 0x0,
22826 .pme_numasks = 0,
22827 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22828 .pme_ctr = 22,
22829 .pme_event = 0,
22830 .pme_chipno = 7,
22831 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22832 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22833 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22834 },
22835 {
22836 .pme_name = "REQUESTS_2@8",
22837 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 8)",
22838 .pme_code = 1608,
22839 .pme_flags = 0x0,
22840 .pme_numasks = 0,
22841 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22842 .pme_ctr = 22,
22843 .pme_event = 0,
22844 .pme_chipno = 8,
22845 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22846 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22847 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22848 },
22849 {
22850 .pme_name = "REQUESTS_2@9",
22851 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 9)",
22852 .pme_code = 1609,
22853 .pme_flags = 0x0,
22854 .pme_numasks = 0,
22855 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22856 .pme_ctr = 22,
22857 .pme_event = 0,
22858 .pme_chipno = 9,
22859 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22860 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22861 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22862 },
22863 {
22864 .pme_name = "REQUESTS_2@10",
22865 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 10)",
22866 .pme_code = 1610,
22867 .pme_flags = 0x0,
22868 .pme_numasks = 0,
22869 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22870 .pme_ctr = 22,
22871 .pme_event = 0,
22872 .pme_chipno = 10,
22873 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22874 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22875 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22876 },
22877 {
22878 .pme_name = "REQUESTS_2@11",
22879 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 11)",
22880 .pme_code = 1611,
22881 .pme_flags = 0x0,
22882 .pme_numasks = 0,
22883 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22884 .pme_ctr = 22,
22885 .pme_event = 0,
22886 .pme_chipno = 11,
22887 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22888 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22889 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22890 },
22891 {
22892 .pme_name = "REQUESTS_2@12",
22893 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 12)",
22894 .pme_code = 1612,
22895 .pme_flags = 0x0,
22896 .pme_numasks = 0,
22897 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22898 .pme_ctr = 22,
22899 .pme_event = 0,
22900 .pme_chipno = 12,
22901 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22902 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22903 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22904 },
22905 {
22906 .pme_name = "REQUESTS_2@13",
22907 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 13)",
22908 .pme_code = 1613,
22909 .pme_flags = 0x0,
22910 .pme_numasks = 0,
22911 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22912 .pme_ctr = 22,
22913 .pme_event = 0,
22914 .pme_chipno = 13,
22915 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22916 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22917 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22918 },
22919 {
22920 .pme_name = "REQUESTS_2@14",
22921 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 14)",
22922 .pme_code = 1614,
22923 .pme_flags = 0x0,
22924 .pme_numasks = 0,
22925 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22926 .pme_ctr = 22,
22927 .pme_event = 0,
22928 .pme_chipno = 14,
22929 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22930 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22931 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22932 },
22933 {
22934 .pme_name = "REQUESTS_2@15",
22935 .pme_desc = "Read or write requests from port 2 to MDs. (M chip 15)",
22936 .pme_code = 1615,
22937 .pme_flags = 0x0,
22938 .pme_numasks = 0,
22939 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22940 .pme_ctr = 22,
22941 .pme_event = 0,
22942 .pme_chipno = 15,
22943 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22944 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22945 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22946 },
22947 /* M Counter 22 Event 1 */
22948 {
22949 .pme_name = "REQUEST_1SWORD@0",
22950 .pme_desc = "Single SWord requests to MDs. (M chip 0)",
22951 .pme_code = 1616,
22952 .pme_flags = 0x0,
22953 .pme_numasks = 0,
22954 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22955 .pme_ctr = 22,
22956 .pme_event = 1,
22957 .pme_chipno = 0,
22958 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22959 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22960 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22961 },
22962 {
22963 .pme_name = "REQUEST_1SWORD@1",
22964 .pme_desc = "Single SWord requests to MDs. (M chip 1)",
22965 .pme_code = 1617,
22966 .pme_flags = 0x0,
22967 .pme_numasks = 0,
22968 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22969 .pme_ctr = 22,
22970 .pme_event = 1,
22971 .pme_chipno = 1,
22972 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22973 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22974 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22975 },
22976 {
22977 .pme_name = "REQUEST_1SWORD@2",
22978 .pme_desc = "Single SWord requests to MDs. (M chip 2)",
22979 .pme_code = 1618,
22980 .pme_flags = 0x0,
22981 .pme_numasks = 0,
22982 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22983 .pme_ctr = 22,
22984 .pme_event = 1,
22985 .pme_chipno = 2,
22986 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
22987 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
22988 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
22989 },
22990 {
22991 .pme_name = "REQUEST_1SWORD@3",
22992 .pme_desc = "Single SWord requests to MDs. (M chip 3)",
22993 .pme_code = 1619,
22994 .pme_flags = 0x0,
22995 .pme_numasks = 0,
22996 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
22997 .pme_ctr = 22,
22998 .pme_event = 1,
22999 .pme_chipno = 3,
23000 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23001 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23002 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23003 },
23004 {
23005 .pme_name = "REQUEST_1SWORD@4",
23006 .pme_desc = "Single SWord requests to MDs. (M chip 4)",
23007 .pme_code = 1620,
23008 .pme_flags = 0x0,
23009 .pme_numasks = 0,
23010 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23011 .pme_ctr = 22,
23012 .pme_event = 1,
23013 .pme_chipno = 4,
23014 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23015 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23016 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23017 },
23018 {
23019 .pme_name = "REQUEST_1SWORD@5",
23020 .pme_desc = "Single SWord requests to MDs. (M chip 5)",
23021 .pme_code = 1621,
23022 .pme_flags = 0x0,
23023 .pme_numasks = 0,
23024 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23025 .pme_ctr = 22,
23026 .pme_event = 1,
23027 .pme_chipno = 5,
23028 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23029 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23030 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23031 },
23032 {
23033 .pme_name = "REQUEST_1SWORD@6",
23034 .pme_desc = "Single SWord requests to MDs. (M chip 6)",
23035 .pme_code = 1622,
23036 .pme_flags = 0x0,
23037 .pme_numasks = 0,
23038 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23039 .pme_ctr = 22,
23040 .pme_event = 1,
23041 .pme_chipno = 6,
23042 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23043 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23044 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23045 },
23046 {
23047 .pme_name = "REQUEST_1SWORD@7",
23048 .pme_desc = "Single SWord requests to MDs. (M chip 7)",
23049 .pme_code = 1623,
23050 .pme_flags = 0x0,
23051 .pme_numasks = 0,
23052 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23053 .pme_ctr = 22,
23054 .pme_event = 1,
23055 .pme_chipno = 7,
23056 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23057 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23058 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23059 },
23060 {
23061 .pme_name = "REQUEST_1SWORD@8",
23062 .pme_desc = "Single SWord requests to MDs. (M chip 8)",
23063 .pme_code = 1624,
23064 .pme_flags = 0x0,
23065 .pme_numasks = 0,
23066 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23067 .pme_ctr = 22,
23068 .pme_event = 1,
23069 .pme_chipno = 8,
23070 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23071 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23072 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23073 },
23074 {
23075 .pme_name = "REQUEST_1SWORD@9",
23076 .pme_desc = "Single SWord requests to MDs. (M chip 9)",
23077 .pme_code = 1625,
23078 .pme_flags = 0x0,
23079 .pme_numasks = 0,
23080 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23081 .pme_ctr = 22,
23082 .pme_event = 1,
23083 .pme_chipno = 9,
23084 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23085 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23086 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23087 },
23088 {
23089 .pme_name = "REQUEST_1SWORD@10",
23090 .pme_desc = "Single SWord requests to MDs. (M chip 10)",
23091 .pme_code = 1626,
23092 .pme_flags = 0x0,
23093 .pme_numasks = 0,
23094 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23095 .pme_ctr = 22,
23096 .pme_event = 1,
23097 .pme_chipno = 10,
23098 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23099 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23100 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23101 },
23102 {
23103 .pme_name = "REQUEST_1SWORD@11",
23104 .pme_desc = "Single SWord requests to MDs. (M chip 11)",
23105 .pme_code = 1627,
23106 .pme_flags = 0x0,
23107 .pme_numasks = 0,
23108 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23109 .pme_ctr = 22,
23110 .pme_event = 1,
23111 .pme_chipno = 11,
23112 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23113 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23114 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23115 },
23116 {
23117 .pme_name = "REQUEST_1SWORD@12",
23118 .pme_desc = "Single SWord requests to MDs. (M chip 12)",
23119 .pme_code = 1628,
23120 .pme_flags = 0x0,
23121 .pme_numasks = 0,
23122 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23123 .pme_ctr = 22,
23124 .pme_event = 1,
23125 .pme_chipno = 12,
23126 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23127 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23128 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23129 },
23130 {
23131 .pme_name = "REQUEST_1SWORD@13",
23132 .pme_desc = "Single SWord requests to MDs. (M chip 13)",
23133 .pme_code = 1629,
23134 .pme_flags = 0x0,
23135 .pme_numasks = 0,
23136 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23137 .pme_ctr = 22,
23138 .pme_event = 1,
23139 .pme_chipno = 13,
23140 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23141 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23142 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23143 },
23144 {
23145 .pme_name = "REQUEST_1SWORD@14",
23146 .pme_desc = "Single SWord requests to MDs. (M chip 14)",
23147 .pme_code = 1630,
23148 .pme_flags = 0x0,
23149 .pme_numasks = 0,
23150 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23151 .pme_ctr = 22,
23152 .pme_event = 1,
23153 .pme_chipno = 14,
23154 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23155 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23156 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23157 },
23158 {
23159 .pme_name = "REQUEST_1SWORD@15",
23160 .pme_desc = "Single SWord requests to MDs. (M chip 15)",
23161 .pme_code = 1631,
23162 .pme_flags = 0x0,
23163 .pme_numasks = 0,
23164 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23165 .pme_ctr = 22,
23166 .pme_event = 1,
23167 .pme_chipno = 15,
23168 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23169 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23170 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23171 },
23172 /* M Counter 22 Event 2 */
23173 {
23174 .pme_name = "MM3_ANY_BANK_BUSY@0",
23175 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 0)",
23176 .pme_code = 1632,
23177 .pme_flags = 0x0,
23178 .pme_numasks = 0,
23179 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23180 .pme_ctr = 22,
23181 .pme_event = 2,
23182 .pme_chipno = 0,
23183 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23184 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23185 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23186 },
23187 {
23188 .pme_name = "MM3_ANY_BANK_BUSY@1",
23189 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 1)",
23190 .pme_code = 1633,
23191 .pme_flags = 0x0,
23192 .pme_numasks = 0,
23193 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23194 .pme_ctr = 22,
23195 .pme_event = 2,
23196 .pme_chipno = 1,
23197 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23198 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23199 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23200 },
23201 {
23202 .pme_name = "MM3_ANY_BANK_BUSY@2",
23203 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 2)",
23204 .pme_code = 1634,
23205 .pme_flags = 0x0,
23206 .pme_numasks = 0,
23207 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23208 .pme_ctr = 22,
23209 .pme_event = 2,
23210 .pme_chipno = 2,
23211 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23212 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23213 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23214 },
23215 {
23216 .pme_name = "MM3_ANY_BANK_BUSY@3",
23217 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 3)",
23218 .pme_code = 1635,
23219 .pme_flags = 0x0,
23220 .pme_numasks = 0,
23221 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23222 .pme_ctr = 22,
23223 .pme_event = 2,
23224 .pme_chipno = 3,
23225 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23226 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23227 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23228 },
23229 {
23230 .pme_name = "MM3_ANY_BANK_BUSY@4",
23231 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 4)",
23232 .pme_code = 1636,
23233 .pme_flags = 0x0,
23234 .pme_numasks = 0,
23235 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23236 .pme_ctr = 22,
23237 .pme_event = 2,
23238 .pme_chipno = 4,
23239 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23240 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23241 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23242 },
23243 {
23244 .pme_name = "MM3_ANY_BANK_BUSY@5",
23245 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 5)",
23246 .pme_code = 1637,
23247 .pme_flags = 0x0,
23248 .pme_numasks = 0,
23249 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23250 .pme_ctr = 22,
23251 .pme_event = 2,
23252 .pme_chipno = 5,
23253 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23254 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23255 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23256 },
23257 {
23258 .pme_name = "MM3_ANY_BANK_BUSY@6",
23259 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 6)",
23260 .pme_code = 1638,
23261 .pme_flags = 0x0,
23262 .pme_numasks = 0,
23263 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23264 .pme_ctr = 22,
23265 .pme_event = 2,
23266 .pme_chipno = 6,
23267 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23268 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23269 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23270 },
23271 {
23272 .pme_name = "MM3_ANY_BANK_BUSY@7",
23273 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 7)",
23274 .pme_code = 1639,
23275 .pme_flags = 0x0,
23276 .pme_numasks = 0,
23277 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23278 .pme_ctr = 22,
23279 .pme_event = 2,
23280 .pme_chipno = 7,
23281 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23282 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23283 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23284 },
23285 {
23286 .pme_name = "MM3_ANY_BANK_BUSY@8",
23287 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 8)",
23288 .pme_code = 1640,
23289 .pme_flags = 0x0,
23290 .pme_numasks = 0,
23291 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23292 .pme_ctr = 22,
23293 .pme_event = 2,
23294 .pme_chipno = 8,
23295 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23296 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23297 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23298 },
23299 {
23300 .pme_name = "MM3_ANY_BANK_BUSY@9",
23301 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 9)",
23302 .pme_code = 1641,
23303 .pme_flags = 0x0,
23304 .pme_numasks = 0,
23305 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23306 .pme_ctr = 22,
23307 .pme_event = 2,
23308 .pme_chipno = 9,
23309 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23310 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23311 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23312 },
23313 {
23314 .pme_name = "MM3_ANY_BANK_BUSY@10",
23315 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 10)",
23316 .pme_code = 1642,
23317 .pme_flags = 0x0,
23318 .pme_numasks = 0,
23319 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23320 .pme_ctr = 22,
23321 .pme_event = 2,
23322 .pme_chipno = 10,
23323 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23324 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23325 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23326 },
23327 {
23328 .pme_name = "MM3_ANY_BANK_BUSY@11",
23329 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 11)",
23330 .pme_code = 1643,
23331 .pme_flags = 0x0,
23332 .pme_numasks = 0,
23333 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23334 .pme_ctr = 22,
23335 .pme_event = 2,
23336 .pme_chipno = 11,
23337 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23338 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23339 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23340 },
23341 {
23342 .pme_name = "MM3_ANY_BANK_BUSY@12",
23343 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 12)",
23344 .pme_code = 1644,
23345 .pme_flags = 0x0,
23346 .pme_numasks = 0,
23347 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23348 .pme_ctr = 22,
23349 .pme_event = 2,
23350 .pme_chipno = 12,
23351 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23352 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23353 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23354 },
23355 {
23356 .pme_name = "MM3_ANY_BANK_BUSY@13",
23357 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 13)",
23358 .pme_code = 1645,
23359 .pme_flags = 0x0,
23360 .pme_numasks = 0,
23361 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23362 .pme_ctr = 22,
23363 .pme_event = 2,
23364 .pme_chipno = 13,
23365 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23366 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23367 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23368 },
23369 {
23370 .pme_name = "MM3_ANY_BANK_BUSY@14",
23371 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 14)",
23372 .pme_code = 1646,
23373 .pme_flags = 0x0,
23374 .pme_numasks = 0,
23375 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23376 .pme_ctr = 22,
23377 .pme_event = 2,
23378 .pme_chipno = 14,
23379 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23380 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23381 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23382 },
23383 {
23384 .pme_name = "MM3_ANY_BANK_BUSY@15",
23385 .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 15)",
23386 .pme_code = 1647,
23387 .pme_flags = 0x0,
23388 .pme_numasks = 0,
23389 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23390 .pme_ctr = 22,
23391 .pme_event = 2,
23392 .pme_chipno = 15,
23393 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23394 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23395 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23396 },
23397 /* M Counter 22 Event 3 */
23398 {
23399 .pme_name = "W_OUT_QUEUE_BP_2@0",
23400 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)",
23401 .pme_code = 1648,
23402 .pme_flags = 0x0,
23403 .pme_numasks = 0,
23404 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23405 .pme_ctr = 22,
23406 .pme_event = 3,
23407 .pme_chipno = 0,
23408 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23409 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23410 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23411 },
23412 {
23413 .pme_name = "W_OUT_QUEUE_BP_2@1",
23414 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)",
23415 .pme_code = 1649,
23416 .pme_flags = 0x0,
23417 .pme_numasks = 0,
23418 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23419 .pme_ctr = 22,
23420 .pme_event = 3,
23421 .pme_chipno = 1,
23422 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23423 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23424 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23425 },
23426 {
23427 .pme_name = "W_OUT_QUEUE_BP_2@2",
23428 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)",
23429 .pme_code = 1650,
23430 .pme_flags = 0x0,
23431 .pme_numasks = 0,
23432 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23433 .pme_ctr = 22,
23434 .pme_event = 3,
23435 .pme_chipno = 2,
23436 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23437 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23438 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23439 },
23440 {
23441 .pme_name = "W_OUT_QUEUE_BP_2@3",
23442 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)",
23443 .pme_code = 1651,
23444 .pme_flags = 0x0,
23445 .pme_numasks = 0,
23446 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23447 .pme_ctr = 22,
23448 .pme_event = 3,
23449 .pme_chipno = 3,
23450 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23451 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23452 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23453 },
23454 {
23455 .pme_name = "W_OUT_QUEUE_BP_2@4",
23456 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)",
23457 .pme_code = 1652,
23458 .pme_flags = 0x0,
23459 .pme_numasks = 0,
23460 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23461 .pme_ctr = 22,
23462 .pme_event = 3,
23463 .pme_chipno = 4,
23464 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23465 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23466 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23467 },
23468 {
23469 .pme_name = "W_OUT_QUEUE_BP_2@5",
23470 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)",
23471 .pme_code = 1653,
23472 .pme_flags = 0x0,
23473 .pme_numasks = 0,
23474 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23475 .pme_ctr = 22,
23476 .pme_event = 3,
23477 .pme_chipno = 5,
23478 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23479 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23480 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23481 },
23482 {
23483 .pme_name = "W_OUT_QUEUE_BP_2@6",
23484 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)",
23485 .pme_code = 1654,
23486 .pme_flags = 0x0,
23487 .pme_numasks = 0,
23488 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23489 .pme_ctr = 22,
23490 .pme_event = 3,
23491 .pme_chipno = 6,
23492 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23493 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23494 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23495 },
23496 {
23497 .pme_name = "W_OUT_QUEUE_BP_2@7",
23498 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)",
23499 .pme_code = 1655,
23500 .pme_flags = 0x0,
23501 .pme_numasks = 0,
23502 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23503 .pme_ctr = 22,
23504 .pme_event = 3,
23505 .pme_chipno = 7,
23506 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23507 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23508 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23509 },
23510 {
23511 .pme_name = "W_OUT_QUEUE_BP_2@8",
23512 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)",
23513 .pme_code = 1656,
23514 .pme_flags = 0x0,
23515 .pme_numasks = 0,
23516 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23517 .pme_ctr = 22,
23518 .pme_event = 3,
23519 .pme_chipno = 8,
23520 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23521 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23522 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23523 },
23524 {
23525 .pme_name = "W_OUT_QUEUE_BP_2@9",
23526 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)",
23527 .pme_code = 1657,
23528 .pme_flags = 0x0,
23529 .pme_numasks = 0,
23530 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23531 .pme_ctr = 22,
23532 .pme_event = 3,
23533 .pme_chipno = 9,
23534 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23535 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23536 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23537 },
23538 {
23539 .pme_name = "W_OUT_QUEUE_BP_2@10",
23540 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)",
23541 .pme_code = 1658,
23542 .pme_flags = 0x0,
23543 .pme_numasks = 0,
23544 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23545 .pme_ctr = 22,
23546 .pme_event = 3,
23547 .pme_chipno = 10,
23548 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23549 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23550 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23551 },
23552 {
23553 .pme_name = "W_OUT_QUEUE_BP_2@11",
23554 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)",
23555 .pme_code = 1659,
23556 .pme_flags = 0x0,
23557 .pme_numasks = 0,
23558 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23559 .pme_ctr = 22,
23560 .pme_event = 3,
23561 .pme_chipno = 11,
23562 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23563 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23564 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23565 },
23566 {
23567 .pme_name = "W_OUT_QUEUE_BP_2@12",
23568 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)",
23569 .pme_code = 1660,
23570 .pme_flags = 0x0,
23571 .pme_numasks = 0,
23572 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23573 .pme_ctr = 22,
23574 .pme_event = 3,
23575 .pme_chipno = 12,
23576 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23577 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23578 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23579 },
23580 {
23581 .pme_name = "W_OUT_QUEUE_BP_2@13",
23582 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)",
23583 .pme_code = 1661,
23584 .pme_flags = 0x0,
23585 .pme_numasks = 0,
23586 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23587 .pme_ctr = 22,
23588 .pme_event = 3,
23589 .pme_chipno = 13,
23590 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23591 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23592 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23593 },
23594 {
23595 .pme_name = "W_OUT_QUEUE_BP_2@14",
23596 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)",
23597 .pme_code = 1662,
23598 .pme_flags = 0x0,
23599 .pme_numasks = 0,
23600 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23601 .pme_ctr = 22,
23602 .pme_event = 3,
23603 .pme_chipno = 14,
23604 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23605 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23606 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23607 },
23608 {
23609 .pme_name = "W_OUT_QUEUE_BP_2@15",
23610 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)",
23611 .pme_code = 1663,
23612 .pme_flags = 0x0,
23613 .pme_numasks = 0,
23614 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23615 .pme_ctr = 22,
23616 .pme_event = 3,
23617 .pme_chipno = 15,
23618 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23619 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23620 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23621 },
23622 /* M Counter 23 Event 0 */
23623 {
23624 .pme_name = "REQUESTS_3@0",
23625 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 0)",
23626 .pme_code = 1664,
23627 .pme_flags = 0x0,
23628 .pme_numasks = 0,
23629 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23630 .pme_ctr = 23,
23631 .pme_event = 0,
23632 .pme_chipno = 0,
23633 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23634 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23635 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23636 },
23637 {
23638 .pme_name = "REQUESTS_3@1",
23639 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 1)",
23640 .pme_code = 1665,
23641 .pme_flags = 0x0,
23642 .pme_numasks = 0,
23643 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23644 .pme_ctr = 23,
23645 .pme_event = 0,
23646 .pme_chipno = 1,
23647 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23648 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23649 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23650 },
23651 {
23652 .pme_name = "REQUESTS_3@2",
23653 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 2)",
23654 .pme_code = 1666,
23655 .pme_flags = 0x0,
23656 .pme_numasks = 0,
23657 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23658 .pme_ctr = 23,
23659 .pme_event = 0,
23660 .pme_chipno = 2,
23661 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23662 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23663 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23664 },
23665 {
23666 .pme_name = "REQUESTS_3@3",
23667 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 3)",
23668 .pme_code = 1667,
23669 .pme_flags = 0x0,
23670 .pme_numasks = 0,
23671 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23672 .pme_ctr = 23,
23673 .pme_event = 0,
23674 .pme_chipno = 3,
23675 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23676 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23677 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23678 },
23679 {
23680 .pme_name = "REQUESTS_3@4",
23681 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 4)",
23682 .pme_code = 1668,
23683 .pme_flags = 0x0,
23684 .pme_numasks = 0,
23685 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23686 .pme_ctr = 23,
23687 .pme_event = 0,
23688 .pme_chipno = 4,
23689 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23690 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23691 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23692 },
23693 {
23694 .pme_name = "REQUESTS_3@5",
23695 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 5)",
23696 .pme_code = 1669,
23697 .pme_flags = 0x0,
23698 .pme_numasks = 0,
23699 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23700 .pme_ctr = 23,
23701 .pme_event = 0,
23702 .pme_chipno = 5,
23703 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23704 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23705 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23706 },
23707 {
23708 .pme_name = "REQUESTS_3@6",
23709 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 6)",
23710 .pme_code = 1670,
23711 .pme_flags = 0x0,
23712 .pme_numasks = 0,
23713 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23714 .pme_ctr = 23,
23715 .pme_event = 0,
23716 .pme_chipno = 6,
23717 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23718 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23719 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23720 },
23721 {
23722 .pme_name = "REQUESTS_3@7",
23723 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 7)",
23724 .pme_code = 1671,
23725 .pme_flags = 0x0,
23726 .pme_numasks = 0,
23727 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23728 .pme_ctr = 23,
23729 .pme_event = 0,
23730 .pme_chipno = 7,
23731 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23732 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23733 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23734 },
23735 {
23736 .pme_name = "REQUESTS_3@8",
23737 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 8)",
23738 .pme_code = 1672,
23739 .pme_flags = 0x0,
23740 .pme_numasks = 0,
23741 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23742 .pme_ctr = 23,
23743 .pme_event = 0,
23744 .pme_chipno = 8,
23745 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23746 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23747 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23748 },
23749 {
23750 .pme_name = "REQUESTS_3@9",
23751 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 9)",
23752 .pme_code = 1673,
23753 .pme_flags = 0x0,
23754 .pme_numasks = 0,
23755 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23756 .pme_ctr = 23,
23757 .pme_event = 0,
23758 .pme_chipno = 9,
23759 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23760 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23761 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23762 },
23763 {
23764 .pme_name = "REQUESTS_3@10",
23765 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 10)",
23766 .pme_code = 1674,
23767 .pme_flags = 0x0,
23768 .pme_numasks = 0,
23769 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23770 .pme_ctr = 23,
23771 .pme_event = 0,
23772 .pme_chipno = 10,
23773 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23774 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23775 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23776 },
23777 {
23778 .pme_name = "REQUESTS_3@11",
23779 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 11)",
23780 .pme_code = 1675,
23781 .pme_flags = 0x0,
23782 .pme_numasks = 0,
23783 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23784 .pme_ctr = 23,
23785 .pme_event = 0,
23786 .pme_chipno = 11,
23787 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23788 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23789 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23790 },
23791 {
23792 .pme_name = "REQUESTS_3@12",
23793 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 12)",
23794 .pme_code = 1676,
23795 .pme_flags = 0x0,
23796 .pme_numasks = 0,
23797 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23798 .pme_ctr = 23,
23799 .pme_event = 0,
23800 .pme_chipno = 12,
23801 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23802 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23803 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23804 },
23805 {
23806 .pme_name = "REQUESTS_3@13",
23807 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 13)",
23808 .pme_code = 1677,
23809 .pme_flags = 0x0,
23810 .pme_numasks = 0,
23811 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23812 .pme_ctr = 23,
23813 .pme_event = 0,
23814 .pme_chipno = 13,
23815 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23816 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23817 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23818 },
23819 {
23820 .pme_name = "REQUESTS_3@14",
23821 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 14)",
23822 .pme_code = 1678,
23823 .pme_flags = 0x0,
23824 .pme_numasks = 0,
23825 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23826 .pme_ctr = 23,
23827 .pme_event = 0,
23828 .pme_chipno = 14,
23829 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23830 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23831 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23832 },
23833 {
23834 .pme_name = "REQUESTS_3@15",
23835 .pme_desc = "Read or write requests from port 3 to MDs. (M chip 15)",
23836 .pme_code = 1679,
23837 .pme_flags = 0x0,
23838 .pme_numasks = 0,
23839 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23840 .pme_ctr = 23,
23841 .pme_event = 0,
23842 .pme_chipno = 15,
23843 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23844 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23845 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23846 },
23847 /* M Counter 23 Event 1 */
23848 {
23849 .pme_name = "<M:23:1>@0",
23850 .pme_desc = "<NA>",
23851 .pme_code = 1680,
23852 .pme_flags = 0x0,
23853 .pme_numasks = 0,
23854 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23855 .pme_ctr = 23,
23856 .pme_event = 1,
23857 .pme_chipno = 0,
23858 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23859 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23860 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23861 },
23862 {
23863 .pme_name = "<M:23:1>@1",
23864 .pme_desc = "<NA>",
23865 .pme_code = 1681,
23866 .pme_flags = 0x0,
23867 .pme_numasks = 0,
23868 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23869 .pme_ctr = 23,
23870 .pme_event = 1,
23871 .pme_chipno = 1,
23872 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23873 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23874 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23875 },
23876 {
23877 .pme_name = "<M:23:1>@2",
23878 .pme_desc = "<NA>",
23879 .pme_code = 1682,
23880 .pme_flags = 0x0,
23881 .pme_numasks = 0,
23882 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23883 .pme_ctr = 23,
23884 .pme_event = 1,
23885 .pme_chipno = 2,
23886 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23887 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23888 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23889 },
23890 {
23891 .pme_name = "<M:23:1>@3",
23892 .pme_desc = "<NA>",
23893 .pme_code = 1683,
23894 .pme_flags = 0x0,
23895 .pme_numasks = 0,
23896 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23897 .pme_ctr = 23,
23898 .pme_event = 1,
23899 .pme_chipno = 3,
23900 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23901 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23902 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23903 },
23904 {
23905 .pme_name = "<M:23:1>@4",
23906 .pme_desc = "<NA>",
23907 .pme_code = 1684,
23908 .pme_flags = 0x0,
23909 .pme_numasks = 0,
23910 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23911 .pme_ctr = 23,
23912 .pme_event = 1,
23913 .pme_chipno = 4,
23914 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23915 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23916 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23917 },
23918 {
23919 .pme_name = "<M:23:1>@5",
23920 .pme_desc = "<NA>",
23921 .pme_code = 1685,
23922 .pme_flags = 0x0,
23923 .pme_numasks = 0,
23924 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23925 .pme_ctr = 23,
23926 .pme_event = 1,
23927 .pme_chipno = 5,
23928 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23929 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23930 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23931 },
23932 {
23933 .pme_name = "<M:23:1>@6",
23934 .pme_desc = "<NA>",
23935 .pme_code = 1686,
23936 .pme_flags = 0x0,
23937 .pme_numasks = 0,
23938 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23939 .pme_ctr = 23,
23940 .pme_event = 1,
23941 .pme_chipno = 6,
23942 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23943 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23944 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23945 },
23946 {
23947 .pme_name = "<M:23:1>@7",
23948 .pme_desc = "<NA>",
23949 .pme_code = 1687,
23950 .pme_flags = 0x0,
23951 .pme_numasks = 0,
23952 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23953 .pme_ctr = 23,
23954 .pme_event = 1,
23955 .pme_chipno = 7,
23956 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23957 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23958 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23959 },
23960 {
23961 .pme_name = "<M:23:1>@8",
23962 .pme_desc = "<NA>",
23963 .pme_code = 1688,
23964 .pme_flags = 0x0,
23965 .pme_numasks = 0,
23966 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23967 .pme_ctr = 23,
23968 .pme_event = 1,
23969 .pme_chipno = 8,
23970 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23971 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23972 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23973 },
23974 {
23975 .pme_name = "<M:23:1>@9",
23976 .pme_desc = "<NA>",
23977 .pme_code = 1689,
23978 .pme_flags = 0x0,
23979 .pme_numasks = 0,
23980 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23981 .pme_ctr = 23,
23982 .pme_event = 1,
23983 .pme_chipno = 9,
23984 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23985 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
23986 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
23987 },
23988 {
23989 .pme_name = "<M:23:1>@10",
23990 .pme_desc = "<NA>",
23991 .pme_code = 1690,
23992 .pme_flags = 0x0,
23993 .pme_numasks = 0,
23994 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
23995 .pme_ctr = 23,
23996 .pme_event = 1,
23997 .pme_chipno = 10,
23998 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
23999 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24000 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24001 },
24002 {
24003 .pme_name = "<M:23:1>@11",
24004 .pme_desc = "<NA>",
24005 .pme_code = 1691,
24006 .pme_flags = 0x0,
24007 .pme_numasks = 0,
24008 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24009 .pme_ctr = 23,
24010 .pme_event = 1,
24011 .pme_chipno = 11,
24012 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24013 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24014 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24015 },
24016 {
24017 .pme_name = "<M:23:1>@12",
24018 .pme_desc = "<NA>",
24019 .pme_code = 1692,
24020 .pme_flags = 0x0,
24021 .pme_numasks = 0,
24022 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24023 .pme_ctr = 23,
24024 .pme_event = 1,
24025 .pme_chipno = 12,
24026 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24027 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24028 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24029 },
24030 {
24031 .pme_name = "<M:23:1>@13",
24032 .pme_desc = "<NA>",
24033 .pme_code = 1693,
24034 .pme_flags = 0x0,
24035 .pme_numasks = 0,
24036 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24037 .pme_ctr = 23,
24038 .pme_event = 1,
24039 .pme_chipno = 13,
24040 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24041 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24042 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24043 },
24044 {
24045 .pme_name = "<M:23:1>@14",
24046 .pme_desc = "<NA>",
24047 .pme_code = 1694,
24048 .pme_flags = 0x0,
24049 .pme_numasks = 0,
24050 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24051 .pme_ctr = 23,
24052 .pme_event = 1,
24053 .pme_chipno = 14,
24054 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24055 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24056 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24057 },
24058 {
24059 .pme_name = "<M:23:1>@15",
24060 .pme_desc = "<NA>",
24061 .pme_code = 1695,
24062 .pme_flags = 0x0,
24063 .pme_numasks = 0,
24064 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24065 .pme_ctr = 23,
24066 .pme_event = 1,
24067 .pme_chipno = 15,
24068 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24069 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24070 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24071 },
24072 /* M Counter 23 Event 2 */
24073 {
24074 .pme_name = "MM3_ACCUM_BANK_BUSY@0",
24075 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)",
24076 .pme_code = 1696,
24077 .pme_flags = 0x0,
24078 .pme_numasks = 0,
24079 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24080 .pme_ctr = 23,
24081 .pme_event = 2,
24082 .pme_chipno = 0,
24083 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24084 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24085 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24086 },
24087 {
24088 .pme_name = "MM3_ACCUM_BANK_BUSY@1",
24089 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)",
24090 .pme_code = 1697,
24091 .pme_flags = 0x0,
24092 .pme_numasks = 0,
24093 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24094 .pme_ctr = 23,
24095 .pme_event = 2,
24096 .pme_chipno = 1,
24097 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24098 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24099 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24100 },
24101 {
24102 .pme_name = "MM3_ACCUM_BANK_BUSY@2",
24103 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)",
24104 .pme_code = 1698,
24105 .pme_flags = 0x0,
24106 .pme_numasks = 0,
24107 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24108 .pme_ctr = 23,
24109 .pme_event = 2,
24110 .pme_chipno = 2,
24111 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24112 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24113 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24114 },
24115 {
24116 .pme_name = "MM3_ACCUM_BANK_BUSY@3",
24117 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)",
24118 .pme_code = 1699,
24119 .pme_flags = 0x0,
24120 .pme_numasks = 0,
24121 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24122 .pme_ctr = 23,
24123 .pme_event = 2,
24124 .pme_chipno = 3,
24125 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24126 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24127 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24128 },
24129 {
24130 .pme_name = "MM3_ACCUM_BANK_BUSY@4",
24131 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)",
24132 .pme_code = 1700,
24133 .pme_flags = 0x0,
24134 .pme_numasks = 0,
24135 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24136 .pme_ctr = 23,
24137 .pme_event = 2,
24138 .pme_chipno = 4,
24139 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24140 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24141 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24142 },
24143 {
24144 .pme_name = "MM3_ACCUM_BANK_BUSY@5",
24145 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)",
24146 .pme_code = 1701,
24147 .pme_flags = 0x0,
24148 .pme_numasks = 0,
24149 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24150 .pme_ctr = 23,
24151 .pme_event = 2,
24152 .pme_chipno = 5,
24153 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24154 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24155 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24156 },
24157 {
24158 .pme_name = "MM3_ACCUM_BANK_BUSY@6",
24159 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)",
24160 .pme_code = 1702,
24161 .pme_flags = 0x0,
24162 .pme_numasks = 0,
24163 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24164 .pme_ctr = 23,
24165 .pme_event = 2,
24166 .pme_chipno = 6,
24167 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24168 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24169 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24170 },
24171 {
24172 .pme_name = "MM3_ACCUM_BANK_BUSY@7",
24173 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)",
24174 .pme_code = 1703,
24175 .pme_flags = 0x0,
24176 .pme_numasks = 0,
24177 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24178 .pme_ctr = 23,
24179 .pme_event = 2,
24180 .pme_chipno = 7,
24181 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24182 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24183 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24184 },
24185 {
24186 .pme_name = "MM3_ACCUM_BANK_BUSY@8",
24187 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)",
24188 .pme_code = 1704,
24189 .pme_flags = 0x0,
24190 .pme_numasks = 0,
24191 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24192 .pme_ctr = 23,
24193 .pme_event = 2,
24194 .pme_chipno = 8,
24195 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24196 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24197 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24198 },
24199 {
24200 .pme_name = "MM3_ACCUM_BANK_BUSY@9",
24201 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)",
24202 .pme_code = 1705,
24203 .pme_flags = 0x0,
24204 .pme_numasks = 0,
24205 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24206 .pme_ctr = 23,
24207 .pme_event = 2,
24208 .pme_chipno = 9,
24209 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24210 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24211 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24212 },
24213 {
24214 .pme_name = "MM3_ACCUM_BANK_BUSY@10",
24215 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)",
24216 .pme_code = 1706,
24217 .pme_flags = 0x0,
24218 .pme_numasks = 0,
24219 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24220 .pme_ctr = 23,
24221 .pme_event = 2,
24222 .pme_chipno = 10,
24223 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24224 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24225 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24226 },
24227 {
24228 .pme_name = "MM3_ACCUM_BANK_BUSY@11",
24229 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)",
24230 .pme_code = 1707,
24231 .pme_flags = 0x0,
24232 .pme_numasks = 0,
24233 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24234 .pme_ctr = 23,
24235 .pme_event = 2,
24236 .pme_chipno = 11,
24237 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24238 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24239 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24240 },
24241 {
24242 .pme_name = "MM3_ACCUM_BANK_BUSY@12",
24243 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)",
24244 .pme_code = 1708,
24245 .pme_flags = 0x0,
24246 .pme_numasks = 0,
24247 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24248 .pme_ctr = 23,
24249 .pme_event = 2,
24250 .pme_chipno = 12,
24251 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24252 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24253 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24254 },
24255 {
24256 .pme_name = "MM3_ACCUM_BANK_BUSY@13",
24257 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)",
24258 .pme_code = 1709,
24259 .pme_flags = 0x0,
24260 .pme_numasks = 0,
24261 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24262 .pme_ctr = 23,
24263 .pme_event = 2,
24264 .pme_chipno = 13,
24265 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24266 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24267 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24268 },
24269 {
24270 .pme_name = "MM3_ACCUM_BANK_BUSY@14",
24271 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)",
24272 .pme_code = 1710,
24273 .pme_flags = 0x0,
24274 .pme_numasks = 0,
24275 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24276 .pme_ctr = 23,
24277 .pme_event = 2,
24278 .pme_chipno = 14,
24279 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24280 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24281 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24282 },
24283 {
24284 .pme_name = "MM3_ACCUM_BANK_BUSY@15",
24285 .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)",
24286 .pme_code = 1711,
24287 .pme_flags = 0x0,
24288 .pme_numasks = 0,
24289 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24290 .pme_ctr = 23,
24291 .pme_event = 2,
24292 .pme_chipno = 15,
24293 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24294 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24295 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24296 },
24297 /* M Counter 23 Event 3 */
24298 {
24299 .pme_name = "W_OUT_QUEUE_BP_3@0",
24300 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)",
24301 .pme_code = 1712,
24302 .pme_flags = 0x0,
24303 .pme_numasks = 0,
24304 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24305 .pme_ctr = 23,
24306 .pme_event = 3,
24307 .pme_chipno = 0,
24308 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24309 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24310 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24311 },
24312 {
24313 .pme_name = "W_OUT_QUEUE_BP_3@1",
24314 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)",
24315 .pme_code = 1713,
24316 .pme_flags = 0x0,
24317 .pme_numasks = 0,
24318 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24319 .pme_ctr = 23,
24320 .pme_event = 3,
24321 .pme_chipno = 1,
24322 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24323 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24324 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24325 },
24326 {
24327 .pme_name = "W_OUT_QUEUE_BP_3@2",
24328 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)",
24329 .pme_code = 1714,
24330 .pme_flags = 0x0,
24331 .pme_numasks = 0,
24332 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24333 .pme_ctr = 23,
24334 .pme_event = 3,
24335 .pme_chipno = 2,
24336 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24337 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24338 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24339 },
24340 {
24341 .pme_name = "W_OUT_QUEUE_BP_3@3",
24342 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)",
24343 .pme_code = 1715,
24344 .pme_flags = 0x0,
24345 .pme_numasks = 0,
24346 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24347 .pme_ctr = 23,
24348 .pme_event = 3,
24349 .pme_chipno = 3,
24350 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24351 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24352 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24353 },
24354 {
24355 .pme_name = "W_OUT_QUEUE_BP_3@4",
24356 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)",
24357 .pme_code = 1716,
24358 .pme_flags = 0x0,
24359 .pme_numasks = 0,
24360 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24361 .pme_ctr = 23,
24362 .pme_event = 3,
24363 .pme_chipno = 4,
24364 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24365 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24366 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24367 },
24368 {
24369 .pme_name = "W_OUT_QUEUE_BP_3@5",
24370 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)",
24371 .pme_code = 1717,
24372 .pme_flags = 0x0,
24373 .pme_numasks = 0,
24374 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24375 .pme_ctr = 23,
24376 .pme_event = 3,
24377 .pme_chipno = 5,
24378 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24379 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24380 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24381 },
24382 {
24383 .pme_name = "W_OUT_QUEUE_BP_3@6",
24384 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)",
24385 .pme_code = 1718,
24386 .pme_flags = 0x0,
24387 .pme_numasks = 0,
24388 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24389 .pme_ctr = 23,
24390 .pme_event = 3,
24391 .pme_chipno = 6,
24392 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24393 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24394 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24395 },
24396 {
24397 .pme_name = "W_OUT_QUEUE_BP_3@7",
24398 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)",
24399 .pme_code = 1719,
24400 .pme_flags = 0x0,
24401 .pme_numasks = 0,
24402 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24403 .pme_ctr = 23,
24404 .pme_event = 3,
24405 .pme_chipno = 7,
24406 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24407 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24408 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24409 },
24410 {
24411 .pme_name = "W_OUT_QUEUE_BP_3@8",
24412 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)",
24413 .pme_code = 1720,
24414 .pme_flags = 0x0,
24415 .pme_numasks = 0,
24416 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24417 .pme_ctr = 23,
24418 .pme_event = 3,
24419 .pme_chipno = 8,
24420 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24421 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24422 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24423 },
24424 {
24425 .pme_name = "W_OUT_QUEUE_BP_3@9",
24426 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)",
24427 .pme_code = 1721,
24428 .pme_flags = 0x0,
24429 .pme_numasks = 0,
24430 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24431 .pme_ctr = 23,
24432 .pme_event = 3,
24433 .pme_chipno = 9,
24434 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24435 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24436 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24437 },
24438 {
24439 .pme_name = "W_OUT_QUEUE_BP_3@10",
24440 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)",
24441 .pme_code = 1722,
24442 .pme_flags = 0x0,
24443 .pme_numasks = 0,
24444 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24445 .pme_ctr = 23,
24446 .pme_event = 3,
24447 .pme_chipno = 10,
24448 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24449 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24450 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24451 },
24452 {
24453 .pme_name = "W_OUT_QUEUE_BP_3@11",
24454 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)",
24455 .pme_code = 1723,
24456 .pme_flags = 0x0,
24457 .pme_numasks = 0,
24458 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24459 .pme_ctr = 23,
24460 .pme_event = 3,
24461 .pme_chipno = 11,
24462 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24463 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24464 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24465 },
24466 {
24467 .pme_name = "W_OUT_QUEUE_BP_3@12",
24468 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)",
24469 .pme_code = 1724,
24470 .pme_flags = 0x0,
24471 .pme_numasks = 0,
24472 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24473 .pme_ctr = 23,
24474 .pme_event = 3,
24475 .pme_chipno = 12,
24476 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24477 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24478 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24479 },
24480 {
24481 .pme_name = "W_OUT_QUEUE_BP_3@13",
24482 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)",
24483 .pme_code = 1725,
24484 .pme_flags = 0x0,
24485 .pme_numasks = 0,
24486 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24487 .pme_ctr = 23,
24488 .pme_event = 3,
24489 .pme_chipno = 13,
24490 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24491 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24492 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24493 },
24494 {
24495 .pme_name = "W_OUT_QUEUE_BP_3@14",
24496 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)",
24497 .pme_code = 1726,
24498 .pme_flags = 0x0,
24499 .pme_numasks = 0,
24500 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24501 .pme_ctr = 23,
24502 .pme_event = 3,
24503 .pme_chipno = 14,
24504 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24505 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24506 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24507 },
24508 {
24509 .pme_name = "W_OUT_QUEUE_BP_3@15",
24510 .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)",
24511 .pme_code = 1727,
24512 .pme_flags = 0x0,
24513 .pme_numasks = 0,
24514 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24515 .pme_ctr = 23,
24516 .pme_event = 3,
24517 .pme_chipno = 15,
24518 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24519 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24520 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24521 },
24522 /* M Counter 24 Event 0 */
24523 {
24524 .pme_name = "W_SWORD_PUTS@0",
24525 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)",
24526 .pme_code = 1728,
24527 .pme_flags = 0x0,
24528 .pme_numasks = 0,
24529 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24530 .pme_ctr = 24,
24531 .pme_event = 0,
24532 .pme_chipno = 0,
24533 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24534 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24535 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24536 },
24537 {
24538 .pme_name = "W_SWORD_PUTS@1",
24539 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)",
24540 .pme_code = 1729,
24541 .pme_flags = 0x0,
24542 .pme_numasks = 0,
24543 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24544 .pme_ctr = 24,
24545 .pme_event = 0,
24546 .pme_chipno = 1,
24547 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24548 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24549 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24550 },
24551 {
24552 .pme_name = "W_SWORD_PUTS@2",
24553 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)",
24554 .pme_code = 1730,
24555 .pme_flags = 0x0,
24556 .pme_numasks = 0,
24557 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24558 .pme_ctr = 24,
24559 .pme_event = 0,
24560 .pme_chipno = 2,
24561 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24562 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24563 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24564 },
24565 {
24566 .pme_name = "W_SWORD_PUTS@3",
24567 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)",
24568 .pme_code = 1731,
24569 .pme_flags = 0x0,
24570 .pme_numasks = 0,
24571 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24572 .pme_ctr = 24,
24573 .pme_event = 0,
24574 .pme_chipno = 3,
24575 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24576 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24577 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24578 },
24579 {
24580 .pme_name = "W_SWORD_PUTS@4",
24581 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)",
24582 .pme_code = 1732,
24583 .pme_flags = 0x0,
24584 .pme_numasks = 0,
24585 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24586 .pme_ctr = 24,
24587 .pme_event = 0,
24588 .pme_chipno = 4,
24589 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24590 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24591 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24592 },
24593 {
24594 .pme_name = "W_SWORD_PUTS@5",
24595 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)",
24596 .pme_code = 1733,
24597 .pme_flags = 0x0,
24598 .pme_numasks = 0,
24599 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24600 .pme_ctr = 24,
24601 .pme_event = 0,
24602 .pme_chipno = 5,
24603 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24604 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24605 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24606 },
24607 {
24608 .pme_name = "W_SWORD_PUTS@6",
24609 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)",
24610 .pme_code = 1734,
24611 .pme_flags = 0x0,
24612 .pme_numasks = 0,
24613 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24614 .pme_ctr = 24,
24615 .pme_event = 0,
24616 .pme_chipno = 6,
24617 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24618 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24619 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24620 },
24621 {
24622 .pme_name = "W_SWORD_PUTS@7",
24623 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)",
24624 .pme_code = 1735,
24625 .pme_flags = 0x0,
24626 .pme_numasks = 0,
24627 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24628 .pme_ctr = 24,
24629 .pme_event = 0,
24630 .pme_chipno = 7,
24631 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24632 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24633 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24634 },
24635 {
24636 .pme_name = "W_SWORD_PUTS@8",
24637 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)",
24638 .pme_code = 1736,
24639 .pme_flags = 0x0,
24640 .pme_numasks = 0,
24641 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24642 .pme_ctr = 24,
24643 .pme_event = 0,
24644 .pme_chipno = 8,
24645 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24646 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24647 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24648 },
24649 {
24650 .pme_name = "W_SWORD_PUTS@9",
24651 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)",
24652 .pme_code = 1737,
24653 .pme_flags = 0x0,
24654 .pme_numasks = 0,
24655 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24656 .pme_ctr = 24,
24657 .pme_event = 0,
24658 .pme_chipno = 9,
24659 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24660 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24661 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24662 },
24663 {
24664 .pme_name = "W_SWORD_PUTS@10",
24665 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)",
24666 .pme_code = 1738,
24667 .pme_flags = 0x0,
24668 .pme_numasks = 0,
24669 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24670 .pme_ctr = 24,
24671 .pme_event = 0,
24672 .pme_chipno = 10,
24673 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24674 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24675 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24676 },
24677 {
24678 .pme_name = "W_SWORD_PUTS@11",
24679 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)",
24680 .pme_code = 1739,
24681 .pme_flags = 0x0,
24682 .pme_numasks = 0,
24683 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24684 .pme_ctr = 24,
24685 .pme_event = 0,
24686 .pme_chipno = 11,
24687 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24688 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24689 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24690 },
24691 {
24692 .pme_name = "W_SWORD_PUTS@12",
24693 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)",
24694 .pme_code = 1740,
24695 .pme_flags = 0x0,
24696 .pme_numasks = 0,
24697 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24698 .pme_ctr = 24,
24699 .pme_event = 0,
24700 .pme_chipno = 12,
24701 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24702 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24703 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24704 },
24705 {
24706 .pme_name = "W_SWORD_PUTS@13",
24707 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)",
24708 .pme_code = 1741,
24709 .pme_flags = 0x0,
24710 .pme_numasks = 0,
24711 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24712 .pme_ctr = 24,
24713 .pme_event = 0,
24714 .pme_chipno = 13,
24715 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24716 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24717 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24718 },
24719 {
24720 .pme_name = "W_SWORD_PUTS@14",
24721 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)",
24722 .pme_code = 1742,
24723 .pme_flags = 0x0,
24724 .pme_numasks = 0,
24725 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24726 .pme_ctr = 24,
24727 .pme_event = 0,
24728 .pme_chipno = 14,
24729 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24730 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24731 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24732 },
24733 {
24734 .pme_name = "W_SWORD_PUTS@15",
24735 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)",
24736 .pme_code = 1743,
24737 .pme_flags = 0x0,
24738 .pme_numasks = 0,
24739 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24740 .pme_ctr = 24,
24741 .pme_event = 0,
24742 .pme_chipno = 15,
24743 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24744 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24745 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24746 },
24747 /* M Counter 24 Event 1 */
24748 {
24749 .pme_name = "<M:24:1>@0",
24750 .pme_desc = "<NA>",
24751 .pme_code = 1744,
24752 .pme_flags = 0x0,
24753 .pme_numasks = 0,
24754 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24755 .pme_ctr = 24,
24756 .pme_event = 1,
24757 .pme_chipno = 0,
24758 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24759 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24760 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24761 },
24762 {
24763 .pme_name = "<M:24:1>@1",
24764 .pme_desc = "<NA>",
24765 .pme_code = 1745,
24766 .pme_flags = 0x0,
24767 .pme_numasks = 0,
24768 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24769 .pme_ctr = 24,
24770 .pme_event = 1,
24771 .pme_chipno = 1,
24772 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24773 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24774 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24775 },
24776 {
24777 .pme_name = "<M:24:1>@2",
24778 .pme_desc = "<NA>",
24779 .pme_code = 1746,
24780 .pme_flags = 0x0,
24781 .pme_numasks = 0,
24782 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24783 .pme_ctr = 24,
24784 .pme_event = 1,
24785 .pme_chipno = 2,
24786 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24787 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24788 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24789 },
24790 {
24791 .pme_name = "<M:24:1>@3",
24792 .pme_desc = "<NA>",
24793 .pme_code = 1747,
24794 .pme_flags = 0x0,
24795 .pme_numasks = 0,
24796 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24797 .pme_ctr = 24,
24798 .pme_event = 1,
24799 .pme_chipno = 3,
24800 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24801 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24802 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24803 },
24804 {
24805 .pme_name = "<M:24:1>@4",
24806 .pme_desc = "<NA>",
24807 .pme_code = 1748,
24808 .pme_flags = 0x0,
24809 .pme_numasks = 0,
24810 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24811 .pme_ctr = 24,
24812 .pme_event = 1,
24813 .pme_chipno = 4,
24814 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24815 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24816 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24817 },
24818 {
24819 .pme_name = "<M:24:1>@5",
24820 .pme_desc = "<NA>",
24821 .pme_code = 1749,
24822 .pme_flags = 0x0,
24823 .pme_numasks = 0,
24824 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24825 .pme_ctr = 24,
24826 .pme_event = 1,
24827 .pme_chipno = 5,
24828 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24829 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24830 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24831 },
24832 {
24833 .pme_name = "<M:24:1>@6",
24834 .pme_desc = "<NA>",
24835 .pme_code = 1750,
24836 .pme_flags = 0x0,
24837 .pme_numasks = 0,
24838 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24839 .pme_ctr = 24,
24840 .pme_event = 1,
24841 .pme_chipno = 6,
24842 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24843 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24844 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24845 },
24846 {
24847 .pme_name = "<M:24:1>@7",
24848 .pme_desc = "<NA>",
24849 .pme_code = 1751,
24850 .pme_flags = 0x0,
24851 .pme_numasks = 0,
24852 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24853 .pme_ctr = 24,
24854 .pme_event = 1,
24855 .pme_chipno = 7,
24856 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24857 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24858 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24859 },
24860 {
24861 .pme_name = "<M:24:1>@8",
24862 .pme_desc = "<NA>",
24863 .pme_code = 1752,
24864 .pme_flags = 0x0,
24865 .pme_numasks = 0,
24866 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24867 .pme_ctr = 24,
24868 .pme_event = 1,
24869 .pme_chipno = 8,
24870 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24871 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24872 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24873 },
24874 {
24875 .pme_name = "<M:24:1>@9",
24876 .pme_desc = "<NA>",
24877 .pme_code = 1753,
24878 .pme_flags = 0x0,
24879 .pme_numasks = 0,
24880 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24881 .pme_ctr = 24,
24882 .pme_event = 1,
24883 .pme_chipno = 9,
24884 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24885 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24886 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24887 },
24888 {
24889 .pme_name = "<M:24:1>@10",
24890 .pme_desc = "<NA>",
24891 .pme_code = 1754,
24892 .pme_flags = 0x0,
24893 .pme_numasks = 0,
24894 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24895 .pme_ctr = 24,
24896 .pme_event = 1,
24897 .pme_chipno = 10,
24898 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24899 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24900 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24901 },
24902 {
24903 .pme_name = "<M:24:1>@11",
24904 .pme_desc = "<NA>",
24905 .pme_code = 1755,
24906 .pme_flags = 0x0,
24907 .pme_numasks = 0,
24908 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24909 .pme_ctr = 24,
24910 .pme_event = 1,
24911 .pme_chipno = 11,
24912 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24913 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24914 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24915 },
24916 {
24917 .pme_name = "<M:24:1>@12",
24918 .pme_desc = "<NA>",
24919 .pme_code = 1756,
24920 .pme_flags = 0x0,
24921 .pme_numasks = 0,
24922 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24923 .pme_ctr = 24,
24924 .pme_event = 1,
24925 .pme_chipno = 12,
24926 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24927 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24928 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24929 },
24930 {
24931 .pme_name = "<M:24:1>@13",
24932 .pme_desc = "<NA>",
24933 .pme_code = 1757,
24934 .pme_flags = 0x0,
24935 .pme_numasks = 0,
24936 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24937 .pme_ctr = 24,
24938 .pme_event = 1,
24939 .pme_chipno = 13,
24940 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24941 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24942 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24943 },
24944 {
24945 .pme_name = "<M:24:1>@14",
24946 .pme_desc = "<NA>",
24947 .pme_code = 1758,
24948 .pme_flags = 0x0,
24949 .pme_numasks = 0,
24950 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24951 .pme_ctr = 24,
24952 .pme_event = 1,
24953 .pme_chipno = 14,
24954 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24955 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24956 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24957 },
24958 {
24959 .pme_name = "<M:24:1>@15",
24960 .pme_desc = "<NA>",
24961 .pme_code = 1759,
24962 .pme_flags = 0x0,
24963 .pme_numasks = 0,
24964 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24965 .pme_ctr = 24,
24966 .pme_event = 1,
24967 .pme_chipno = 15,
24968 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24969 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24970 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24971 },
24972 /* M Counter 24 Event 2 */
24973 {
24974 .pme_name = "<M:24:2>@0",
24975 .pme_desc = "<NA>",
24976 .pme_code = 1760,
24977 .pme_flags = 0x0,
24978 .pme_numasks = 0,
24979 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24980 .pme_ctr = 24,
24981 .pme_event = 2,
24982 .pme_chipno = 0,
24983 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24984 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24985 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
24986 },
24987 {
24988 .pme_name = "<M:24:2>@1",
24989 .pme_desc = "<NA>",
24990 .pme_code = 1761,
24991 .pme_flags = 0x0,
24992 .pme_numasks = 0,
24993 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
24994 .pme_ctr = 24,
24995 .pme_event = 2,
24996 .pme_chipno = 1,
24997 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
24998 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
24999 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25000 },
25001 {
25002 .pme_name = "<M:24:2>@2",
25003 .pme_desc = "<NA>",
25004 .pme_code = 1762,
25005 .pme_flags = 0x0,
25006 .pme_numasks = 0,
25007 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25008 .pme_ctr = 24,
25009 .pme_event = 2,
25010 .pme_chipno = 2,
25011 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25012 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25013 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25014 },
25015 {
25016 .pme_name = "<M:24:2>@3",
25017 .pme_desc = "<NA>",
25018 .pme_code = 1763,
25019 .pme_flags = 0x0,
25020 .pme_numasks = 0,
25021 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25022 .pme_ctr = 24,
25023 .pme_event = 2,
25024 .pme_chipno = 3,
25025 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25026 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25027 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25028 },
25029 {
25030 .pme_name = "<M:24:2>@4",
25031 .pme_desc = "<NA>",
25032 .pme_code = 1764,
25033 .pme_flags = 0x0,
25034 .pme_numasks = 0,
25035 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25036 .pme_ctr = 24,
25037 .pme_event = 2,
25038 .pme_chipno = 4,
25039 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25040 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25041 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25042 },
25043 {
25044 .pme_name = "<M:24:2>@5",
25045 .pme_desc = "<NA>",
25046 .pme_code = 1765,
25047 .pme_flags = 0x0,
25048 .pme_numasks = 0,
25049 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25050 .pme_ctr = 24,
25051 .pme_event = 2,
25052 .pme_chipno = 5,
25053 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25054 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25055 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25056 },
25057 {
25058 .pme_name = "<M:24:2>@6",
25059 .pme_desc = "<NA>",
25060 .pme_code = 1766,
25061 .pme_flags = 0x0,
25062 .pme_numasks = 0,
25063 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25064 .pme_ctr = 24,
25065 .pme_event = 2,
25066 .pme_chipno = 6,
25067 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25068 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25069 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25070 },
25071 {
25072 .pme_name = "<M:24:2>@7",
25073 .pme_desc = "<NA>",
25074 .pme_code = 1767,
25075 .pme_flags = 0x0,
25076 .pme_numasks = 0,
25077 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25078 .pme_ctr = 24,
25079 .pme_event = 2,
25080 .pme_chipno = 7,
25081 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25082 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25083 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25084 },
25085 {
25086 .pme_name = "<M:24:2>@8",
25087 .pme_desc = "<NA>",
25088 .pme_code = 1768,
25089 .pme_flags = 0x0,
25090 .pme_numasks = 0,
25091 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25092 .pme_ctr = 24,
25093 .pme_event = 2,
25094 .pme_chipno = 8,
25095 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25096 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25097 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25098 },
25099 {
25100 .pme_name = "<M:24:2>@9",
25101 .pme_desc = "<NA>",
25102 .pme_code = 1769,
25103 .pme_flags = 0x0,
25104 .pme_numasks = 0,
25105 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25106 .pme_ctr = 24,
25107 .pme_event = 2,
25108 .pme_chipno = 9,
25109 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25110 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25111 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25112 },
25113 {
25114 .pme_name = "<M:24:2>@10",
25115 .pme_desc = "<NA>",
25116 .pme_code = 1770,
25117 .pme_flags = 0x0,
25118 .pme_numasks = 0,
25119 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25120 .pme_ctr = 24,
25121 .pme_event = 2,
25122 .pme_chipno = 10,
25123 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25124 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25125 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25126 },
25127 {
25128 .pme_name = "<M:24:2>@11",
25129 .pme_desc = "<NA>",
25130 .pme_code = 1771,
25131 .pme_flags = 0x0,
25132 .pme_numasks = 0,
25133 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25134 .pme_ctr = 24,
25135 .pme_event = 2,
25136 .pme_chipno = 11,
25137 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25138 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25139 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25140 },
25141 {
25142 .pme_name = "<M:24:2>@12",
25143 .pme_desc = "<NA>",
25144 .pme_code = 1772,
25145 .pme_flags = 0x0,
25146 .pme_numasks = 0,
25147 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25148 .pme_ctr = 24,
25149 .pme_event = 2,
25150 .pme_chipno = 12,
25151 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25152 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25153 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25154 },
25155 {
25156 .pme_name = "<M:24:2>@13",
25157 .pme_desc = "<NA>",
25158 .pme_code = 1773,
25159 .pme_flags = 0x0,
25160 .pme_numasks = 0,
25161 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25162 .pme_ctr = 24,
25163 .pme_event = 2,
25164 .pme_chipno = 13,
25165 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25166 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25167 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25168 },
25169 {
25170 .pme_name = "<M:24:2>@14",
25171 .pme_desc = "<NA>",
25172 .pme_code = 1774,
25173 .pme_flags = 0x0,
25174 .pme_numasks = 0,
25175 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25176 .pme_ctr = 24,
25177 .pme_event = 2,
25178 .pme_chipno = 14,
25179 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25180 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25181 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25182 },
25183 {
25184 .pme_name = "<M:24:2>@15",
25185 .pme_desc = "<NA>",
25186 .pme_code = 1775,
25187 .pme_flags = 0x0,
25188 .pme_numasks = 0,
25189 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25190 .pme_ctr = 24,
25191 .pme_event = 2,
25192 .pme_chipno = 15,
25193 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25194 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25195 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25196 },
25197 /* M Counter 24 Event 3 */
25198 {
25199 .pme_name = "<M:24:3>@0",
25200 .pme_desc = "<NA>",
25201 .pme_code = 1776,
25202 .pme_flags = 0x0,
25203 .pme_numasks = 0,
25204 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25205 .pme_ctr = 24,
25206 .pme_event = 3,
25207 .pme_chipno = 0,
25208 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25209 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25210 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25211 },
25212 {
25213 .pme_name = "<M:24:3>@1",
25214 .pme_desc = "<NA>",
25215 .pme_code = 1777,
25216 .pme_flags = 0x0,
25217 .pme_numasks = 0,
25218 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25219 .pme_ctr = 24,
25220 .pme_event = 3,
25221 .pme_chipno = 1,
25222 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25223 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25224 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25225 },
25226 {
25227 .pme_name = "<M:24:3>@2",
25228 .pme_desc = "<NA>",
25229 .pme_code = 1778,
25230 .pme_flags = 0x0,
25231 .pme_numasks = 0,
25232 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25233 .pme_ctr = 24,
25234 .pme_event = 3,
25235 .pme_chipno = 2,
25236 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25237 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25238 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25239 },
25240 {
25241 .pme_name = "<M:24:3>@3",
25242 .pme_desc = "<NA>",
25243 .pme_code = 1779,
25244 .pme_flags = 0x0,
25245 .pme_numasks = 0,
25246 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25247 .pme_ctr = 24,
25248 .pme_event = 3,
25249 .pme_chipno = 3,
25250 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25251 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25252 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25253 },
25254 {
25255 .pme_name = "<M:24:3>@4",
25256 .pme_desc = "<NA>",
25257 .pme_code = 1780,
25258 .pme_flags = 0x0,
25259 .pme_numasks = 0,
25260 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25261 .pme_ctr = 24,
25262 .pme_event = 3,
25263 .pme_chipno = 4,
25264 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25265 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25266 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25267 },
25268 {
25269 .pme_name = "<M:24:3>@5",
25270 .pme_desc = "<NA>",
25271 .pme_code = 1781,
25272 .pme_flags = 0x0,
25273 .pme_numasks = 0,
25274 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25275 .pme_ctr = 24,
25276 .pme_event = 3,
25277 .pme_chipno = 5,
25278 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25279 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25280 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25281 },
25282 {
25283 .pme_name = "<M:24:3>@6",
25284 .pme_desc = "<NA>",
25285 .pme_code = 1782,
25286 .pme_flags = 0x0,
25287 .pme_numasks = 0,
25288 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25289 .pme_ctr = 24,
25290 .pme_event = 3,
25291 .pme_chipno = 6,
25292 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25293 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25294 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25295 },
25296 {
25297 .pme_name = "<M:24:3>@7",
25298 .pme_desc = "<NA>",
25299 .pme_code = 1783,
25300 .pme_flags = 0x0,
25301 .pme_numasks = 0,
25302 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25303 .pme_ctr = 24,
25304 .pme_event = 3,
25305 .pme_chipno = 7,
25306 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25307 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25308 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25309 },
25310 {
25311 .pme_name = "<M:24:3>@8",
25312 .pme_desc = "<NA>",
25313 .pme_code = 1784,
25314 .pme_flags = 0x0,
25315 .pme_numasks = 0,
25316 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25317 .pme_ctr = 24,
25318 .pme_event = 3,
25319 .pme_chipno = 8,
25320 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25321 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25322 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25323 },
25324 {
25325 .pme_name = "<M:24:3>@9",
25326 .pme_desc = "<NA>",
25327 .pme_code = 1785,
25328 .pme_flags = 0x0,
25329 .pme_numasks = 0,
25330 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25331 .pme_ctr = 24,
25332 .pme_event = 3,
25333 .pme_chipno = 9,
25334 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25335 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25336 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25337 },
25338 {
25339 .pme_name = "<M:24:3>@10",
25340 .pme_desc = "<NA>",
25341 .pme_code = 1786,
25342 .pme_flags = 0x0,
25343 .pme_numasks = 0,
25344 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25345 .pme_ctr = 24,
25346 .pme_event = 3,
25347 .pme_chipno = 10,
25348 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25349 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25350 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25351 },
25352 {
25353 .pme_name = "<M:24:3>@11",
25354 .pme_desc = "<NA>",
25355 .pme_code = 1787,
25356 .pme_flags = 0x0,
25357 .pme_numasks = 0,
25358 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25359 .pme_ctr = 24,
25360 .pme_event = 3,
25361 .pme_chipno = 11,
25362 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25363 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25364 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25365 },
25366 {
25367 .pme_name = "<M:24:3>@12",
25368 .pme_desc = "<NA>",
25369 .pme_code = 1788,
25370 .pme_flags = 0x0,
25371 .pme_numasks = 0,
25372 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25373 .pme_ctr = 24,
25374 .pme_event = 3,
25375 .pme_chipno = 12,
25376 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25377 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25378 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25379 },
25380 {
25381 .pme_name = "<M:24:3>@13",
25382 .pme_desc = "<NA>",
25383 .pme_code = 1789,
25384 .pme_flags = 0x0,
25385 .pme_numasks = 0,
25386 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25387 .pme_ctr = 24,
25388 .pme_event = 3,
25389 .pme_chipno = 13,
25390 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25391 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25392 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25393 },
25394 {
25395 .pme_name = "<M:24:3>@14",
25396 .pme_desc = "<NA>",
25397 .pme_code = 1790,
25398 .pme_flags = 0x0,
25399 .pme_numasks = 0,
25400 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25401 .pme_ctr = 24,
25402 .pme_event = 3,
25403 .pme_chipno = 14,
25404 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25405 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25406 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25407 },
25408 {
25409 .pme_name = "<M:24:3>@15",
25410 .pme_desc = "<NA>",
25411 .pme_code = 1791,
25412 .pme_flags = 0x0,
25413 .pme_numasks = 0,
25414 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25415 .pme_ctr = 24,
25416 .pme_event = 3,
25417 .pme_chipno = 15,
25418 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25419 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25420 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25421 },
25422 /* M Counter 25 Event 0 */
25423 {
25424 .pme_name = "W_SWORD_NPUTS@0",
25425 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)",
25426 .pme_code = 1792,
25427 .pme_flags = 0x0,
25428 .pme_numasks = 0,
25429 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25430 .pme_ctr = 25,
25431 .pme_event = 0,
25432 .pme_chipno = 0,
25433 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25434 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25435 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25436 },
25437 {
25438 .pme_name = "W_SWORD_NPUTS@1",
25439 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)",
25440 .pme_code = 1793,
25441 .pme_flags = 0x0,
25442 .pme_numasks = 0,
25443 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25444 .pme_ctr = 25,
25445 .pme_event = 0,
25446 .pme_chipno = 1,
25447 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25448 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25449 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25450 },
25451 {
25452 .pme_name = "W_SWORD_NPUTS@2",
25453 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)",
25454 .pme_code = 1794,
25455 .pme_flags = 0x0,
25456 .pme_numasks = 0,
25457 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25458 .pme_ctr = 25,
25459 .pme_event = 0,
25460 .pme_chipno = 2,
25461 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25462 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25463 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25464 },
25465 {
25466 .pme_name = "W_SWORD_NPUTS@3",
25467 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)",
25468 .pme_code = 1795,
25469 .pme_flags = 0x0,
25470 .pme_numasks = 0,
25471 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25472 .pme_ctr = 25,
25473 .pme_event = 0,
25474 .pme_chipno = 3,
25475 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25476 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25477 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25478 },
25479 {
25480 .pme_name = "W_SWORD_NPUTS@4",
25481 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)",
25482 .pme_code = 1796,
25483 .pme_flags = 0x0,
25484 .pme_numasks = 0,
25485 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25486 .pme_ctr = 25,
25487 .pme_event = 0,
25488 .pme_chipno = 4,
25489 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25490 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25491 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25492 },
25493 {
25494 .pme_name = "W_SWORD_NPUTS@5",
25495 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)",
25496 .pme_code = 1797,
25497 .pme_flags = 0x0,
25498 .pme_numasks = 0,
25499 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25500 .pme_ctr = 25,
25501 .pme_event = 0,
25502 .pme_chipno = 5,
25503 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25504 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25505 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25506 },
25507 {
25508 .pme_name = "W_SWORD_NPUTS@6",
25509 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)",
25510 .pme_code = 1798,
25511 .pme_flags = 0x0,
25512 .pme_numasks = 0,
25513 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25514 .pme_ctr = 25,
25515 .pme_event = 0,
25516 .pme_chipno = 6,
25517 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25518 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25519 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25520 },
25521 {
25522 .pme_name = "W_SWORD_NPUTS@7",
25523 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)",
25524 .pme_code = 1799,
25525 .pme_flags = 0x0,
25526 .pme_numasks = 0,
25527 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25528 .pme_ctr = 25,
25529 .pme_event = 0,
25530 .pme_chipno = 7,
25531 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25532 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25533 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25534 },
25535 {
25536 .pme_name = "W_SWORD_NPUTS@8",
25537 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)",
25538 .pme_code = 1800,
25539 .pme_flags = 0x0,
25540 .pme_numasks = 0,
25541 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25542 .pme_ctr = 25,
25543 .pme_event = 0,
25544 .pme_chipno = 8,
25545 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25546 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25547 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25548 },
25549 {
25550 .pme_name = "W_SWORD_NPUTS@9",
25551 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)",
25552 .pme_code = 1801,
25553 .pme_flags = 0x0,
25554 .pme_numasks = 0,
25555 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25556 .pme_ctr = 25,
25557 .pme_event = 0,
25558 .pme_chipno = 9,
25559 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25560 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25561 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25562 },
25563 {
25564 .pme_name = "W_SWORD_NPUTS@10",
25565 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)",
25566 .pme_code = 1802,
25567 .pme_flags = 0x0,
25568 .pme_numasks = 0,
25569 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25570 .pme_ctr = 25,
25571 .pme_event = 0,
25572 .pme_chipno = 10,
25573 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25574 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25575 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25576 },
25577 {
25578 .pme_name = "W_SWORD_NPUTS@11",
25579 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)",
25580 .pme_code = 1803,
25581 .pme_flags = 0x0,
25582 .pme_numasks = 0,
25583 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25584 .pme_ctr = 25,
25585 .pme_event = 0,
25586 .pme_chipno = 11,
25587 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25588 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25589 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25590 },
25591 {
25592 .pme_name = "W_SWORD_NPUTS@12",
25593 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)",
25594 .pme_code = 1804,
25595 .pme_flags = 0x0,
25596 .pme_numasks = 0,
25597 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25598 .pme_ctr = 25,
25599 .pme_event = 0,
25600 .pme_chipno = 12,
25601 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25602 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25603 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25604 },
25605 {
25606 .pme_name = "W_SWORD_NPUTS@13",
25607 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)",
25608 .pme_code = 1805,
25609 .pme_flags = 0x0,
25610 .pme_numasks = 0,
25611 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25612 .pme_ctr = 25,
25613 .pme_event = 0,
25614 .pme_chipno = 13,
25615 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25616 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25617 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25618 },
25619 {
25620 .pme_name = "W_SWORD_NPUTS@14",
25621 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)",
25622 .pme_code = 1806,
25623 .pme_flags = 0x0,
25624 .pme_numasks = 0,
25625 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25626 .pme_ctr = 25,
25627 .pme_event = 0,
25628 .pme_chipno = 14,
25629 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25630 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25631 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25632 },
25633 {
25634 .pme_name = "W_SWORD_NPUTS@15",
25635 .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)",
25636 .pme_code = 1807,
25637 .pme_flags = 0x0,
25638 .pme_numasks = 0,
25639 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25640 .pme_ctr = 25,
25641 .pme_event = 0,
25642 .pme_chipno = 15,
25643 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25644 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25645 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25646 },
25647 /* M Counter 25 Event 1 */
25648 {
25649 .pme_name = "<M:25:1>@0",
25650 .pme_desc = "<NA>",
25651 .pme_code = 1808,
25652 .pme_flags = 0x0,
25653 .pme_numasks = 0,
25654 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25655 .pme_ctr = 25,
25656 .pme_event = 1,
25657 .pme_chipno = 0,
25658 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25659 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25660 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25661 },
25662 {
25663 .pme_name = "<M:25:1>@1",
25664 .pme_desc = "<NA>",
25665 .pme_code = 1809,
25666 .pme_flags = 0x0,
25667 .pme_numasks = 0,
25668 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25669 .pme_ctr = 25,
25670 .pme_event = 1,
25671 .pme_chipno = 1,
25672 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25673 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25674 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25675 },
25676 {
25677 .pme_name = "<M:25:1>@2",
25678 .pme_desc = "<NA>",
25679 .pme_code = 1810,
25680 .pme_flags = 0x0,
25681 .pme_numasks = 0,
25682 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25683 .pme_ctr = 25,
25684 .pme_event = 1,
25685 .pme_chipno = 2,
25686 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25687 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25688 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25689 },
25690 {
25691 .pme_name = "<M:25:1>@3",
25692 .pme_desc = "<NA>",
25693 .pme_code = 1811,
25694 .pme_flags = 0x0,
25695 .pme_numasks = 0,
25696 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25697 .pme_ctr = 25,
25698 .pme_event = 1,
25699 .pme_chipno = 3,
25700 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25701 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25702 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25703 },
25704 {
25705 .pme_name = "<M:25:1>@4",
25706 .pme_desc = "<NA>",
25707 .pme_code = 1812,
25708 .pme_flags = 0x0,
25709 .pme_numasks = 0,
25710 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25711 .pme_ctr = 25,
25712 .pme_event = 1,
25713 .pme_chipno = 4,
25714 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25715 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25716 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25717 },
25718 {
25719 .pme_name = "<M:25:1>@5",
25720 .pme_desc = "<NA>",
25721 .pme_code = 1813,
25722 .pme_flags = 0x0,
25723 .pme_numasks = 0,
25724 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25725 .pme_ctr = 25,
25726 .pme_event = 1,
25727 .pme_chipno = 5,
25728 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25729 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25730 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25731 },
25732 {
25733 .pme_name = "<M:25:1>@6",
25734 .pme_desc = "<NA>",
25735 .pme_code = 1814,
25736 .pme_flags = 0x0,
25737 .pme_numasks = 0,
25738 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25739 .pme_ctr = 25,
25740 .pme_event = 1,
25741 .pme_chipno = 6,
25742 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25743 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25744 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25745 },
25746 {
25747 .pme_name = "<M:25:1>@7",
25748 .pme_desc = "<NA>",
25749 .pme_code = 1815,
25750 .pme_flags = 0x0,
25751 .pme_numasks = 0,
25752 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25753 .pme_ctr = 25,
25754 .pme_event = 1,
25755 .pme_chipno = 7,
25756 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25757 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25758 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25759 },
25760 {
25761 .pme_name = "<M:25:1>@8",
25762 .pme_desc = "<NA>",
25763 .pme_code = 1816,
25764 .pme_flags = 0x0,
25765 .pme_numasks = 0,
25766 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25767 .pme_ctr = 25,
25768 .pme_event = 1,
25769 .pme_chipno = 8,
25770 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25771 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25772 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25773 },
25774 {
25775 .pme_name = "<M:25:1>@9",
25776 .pme_desc = "<NA>",
25777 .pme_code = 1817,
25778 .pme_flags = 0x0,
25779 .pme_numasks = 0,
25780 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25781 .pme_ctr = 25,
25782 .pme_event = 1,
25783 .pme_chipno = 9,
25784 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25785 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25786 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25787 },
25788 {
25789 .pme_name = "<M:25:1>@10",
25790 .pme_desc = "<NA>",
25791 .pme_code = 1818,
25792 .pme_flags = 0x0,
25793 .pme_numasks = 0,
25794 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25795 .pme_ctr = 25,
25796 .pme_event = 1,
25797 .pme_chipno = 10,
25798 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25799 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25800 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25801 },
25802 {
25803 .pme_name = "<M:25:1>@11",
25804 .pme_desc = "<NA>",
25805 .pme_code = 1819,
25806 .pme_flags = 0x0,
25807 .pme_numasks = 0,
25808 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25809 .pme_ctr = 25,
25810 .pme_event = 1,
25811 .pme_chipno = 11,
25812 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25813 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25814 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25815 },
25816 {
25817 .pme_name = "<M:25:1>@12",
25818 .pme_desc = "<NA>",
25819 .pme_code = 1820,
25820 .pme_flags = 0x0,
25821 .pme_numasks = 0,
25822 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25823 .pme_ctr = 25,
25824 .pme_event = 1,
25825 .pme_chipno = 12,
25826 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25827 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25828 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25829 },
25830 {
25831 .pme_name = "<M:25:1>@13",
25832 .pme_desc = "<NA>",
25833 .pme_code = 1821,
25834 .pme_flags = 0x0,
25835 .pme_numasks = 0,
25836 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25837 .pme_ctr = 25,
25838 .pme_event = 1,
25839 .pme_chipno = 13,
25840 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25841 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25842 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25843 },
25844 {
25845 .pme_name = "<M:25:1>@14",
25846 .pme_desc = "<NA>",
25847 .pme_code = 1822,
25848 .pme_flags = 0x0,
25849 .pme_numasks = 0,
25850 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25851 .pme_ctr = 25,
25852 .pme_event = 1,
25853 .pme_chipno = 14,
25854 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25855 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25856 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25857 },
25858 {
25859 .pme_name = "<M:25:1>@15",
25860 .pme_desc = "<NA>",
25861 .pme_code = 1823,
25862 .pme_flags = 0x0,
25863 .pme_numasks = 0,
25864 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25865 .pme_ctr = 25,
25866 .pme_event = 1,
25867 .pme_chipno = 15,
25868 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25869 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25870 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25871 },
25872 /* M Counter 25 Event 2 */
25873 {
25874 .pme_name = "<M:25:2>@0",
25875 .pme_desc = "<NA>",
25876 .pme_code = 1824,
25877 .pme_flags = 0x0,
25878 .pme_numasks = 0,
25879 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25880 .pme_ctr = 25,
25881 .pme_event = 2,
25882 .pme_chipno = 0,
25883 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25884 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25885 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25886 },
25887 {
25888 .pme_name = "<M:25:2>@1",
25889 .pme_desc = "<NA>",
25890 .pme_code = 1825,
25891 .pme_flags = 0x0,
25892 .pme_numasks = 0,
25893 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25894 .pme_ctr = 25,
25895 .pme_event = 2,
25896 .pme_chipno = 1,
25897 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25898 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25899 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25900 },
25901 {
25902 .pme_name = "<M:25:2>@2",
25903 .pme_desc = "<NA>",
25904 .pme_code = 1826,
25905 .pme_flags = 0x0,
25906 .pme_numasks = 0,
25907 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25908 .pme_ctr = 25,
25909 .pme_event = 2,
25910 .pme_chipno = 2,
25911 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25912 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25913 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25914 },
25915 {
25916 .pme_name = "<M:25:2>@3",
25917 .pme_desc = "<NA>",
25918 .pme_code = 1827,
25919 .pme_flags = 0x0,
25920 .pme_numasks = 0,
25921 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25922 .pme_ctr = 25,
25923 .pme_event = 2,
25924 .pme_chipno = 3,
25925 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25926 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25927 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25928 },
25929 {
25930 .pme_name = "<M:25:2>@4",
25931 .pme_desc = "<NA>",
25932 .pme_code = 1828,
25933 .pme_flags = 0x0,
25934 .pme_numasks = 0,
25935 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25936 .pme_ctr = 25,
25937 .pme_event = 2,
25938 .pme_chipno = 4,
25939 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25940 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25941 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25942 },
25943 {
25944 .pme_name = "<M:25:2>@5",
25945 .pme_desc = "<NA>",
25946 .pme_code = 1829,
25947 .pme_flags = 0x0,
25948 .pme_numasks = 0,
25949 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25950 .pme_ctr = 25,
25951 .pme_event = 2,
25952 .pme_chipno = 5,
25953 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25954 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25955 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25956 },
25957 {
25958 .pme_name = "<M:25:2>@6",
25959 .pme_desc = "<NA>",
25960 .pme_code = 1830,
25961 .pme_flags = 0x0,
25962 .pme_numasks = 0,
25963 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25964 .pme_ctr = 25,
25965 .pme_event = 2,
25966 .pme_chipno = 6,
25967 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25968 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25969 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25970 },
25971 {
25972 .pme_name = "<M:25:2>@7",
25973 .pme_desc = "<NA>",
25974 .pme_code = 1831,
25975 .pme_flags = 0x0,
25976 .pme_numasks = 0,
25977 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25978 .pme_ctr = 25,
25979 .pme_event = 2,
25980 .pme_chipno = 7,
25981 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25982 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25983 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25984 },
25985 {
25986 .pme_name = "<M:25:2>@8",
25987 .pme_desc = "<NA>",
25988 .pme_code = 1832,
25989 .pme_flags = 0x0,
25990 .pme_numasks = 0,
25991 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
25992 .pme_ctr = 25,
25993 .pme_event = 2,
25994 .pme_chipno = 8,
25995 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
25996 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
25997 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
25998 },
25999 {
26000 .pme_name = "<M:25:2>@9",
26001 .pme_desc = "<NA>",
26002 .pme_code = 1833,
26003 .pme_flags = 0x0,
26004 .pme_numasks = 0,
26005 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26006 .pme_ctr = 25,
26007 .pme_event = 2,
26008 .pme_chipno = 9,
26009 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26010 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26011 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26012 },
26013 {
26014 .pme_name = "<M:25:2>@10",
26015 .pme_desc = "<NA>",
26016 .pme_code = 1834,
26017 .pme_flags = 0x0,
26018 .pme_numasks = 0,
26019 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26020 .pme_ctr = 25,
26021 .pme_event = 2,
26022 .pme_chipno = 10,
26023 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26024 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26025 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26026 },
26027 {
26028 .pme_name = "<M:25:2>@11",
26029 .pme_desc = "<NA>",
26030 .pme_code = 1835,
26031 .pme_flags = 0x0,
26032 .pme_numasks = 0,
26033 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26034 .pme_ctr = 25,
26035 .pme_event = 2,
26036 .pme_chipno = 11,
26037 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26038 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26039 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26040 },
26041 {
26042 .pme_name = "<M:25:2>@12",
26043 .pme_desc = "<NA>",
26044 .pme_code = 1836,
26045 .pme_flags = 0x0,
26046 .pme_numasks = 0,
26047 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26048 .pme_ctr = 25,
26049 .pme_event = 2,
26050 .pme_chipno = 12,
26051 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26052 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26053 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26054 },
26055 {
26056 .pme_name = "<M:25:2>@13",
26057 .pme_desc = "<NA>",
26058 .pme_code = 1837,
26059 .pme_flags = 0x0,
26060 .pme_numasks = 0,
26061 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26062 .pme_ctr = 25,
26063 .pme_event = 2,
26064 .pme_chipno = 13,
26065 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26066 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26067 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26068 },
26069 {
26070 .pme_name = "<M:25:2>@14",
26071 .pme_desc = "<NA>",
26072 .pme_code = 1838,
26073 .pme_flags = 0x0,
26074 .pme_numasks = 0,
26075 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26076 .pme_ctr = 25,
26077 .pme_event = 2,
26078 .pme_chipno = 14,
26079 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26080 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26081 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26082 },
26083 {
26084 .pme_name = "<M:25:2>@15",
26085 .pme_desc = "<NA>",
26086 .pme_code = 1839,
26087 .pme_flags = 0x0,
26088 .pme_numasks = 0,
26089 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26090 .pme_ctr = 25,
26091 .pme_event = 2,
26092 .pme_chipno = 15,
26093 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26094 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26095 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26096 },
26097 /* M Counter 25 Event 3 */
26098 {
26099 .pme_name = "<M:25:3>@0",
26100 .pme_desc = "<NA>",
26101 .pme_code = 1840,
26102 .pme_flags = 0x0,
26103 .pme_numasks = 0,
26104 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26105 .pme_ctr = 25,
26106 .pme_event = 3,
26107 .pme_chipno = 0,
26108 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26109 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26110 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26111 },
26112 {
26113 .pme_name = "<M:25:3>@1",
26114 .pme_desc = "<NA>",
26115 .pme_code = 1841,
26116 .pme_flags = 0x0,
26117 .pme_numasks = 0,
26118 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26119 .pme_ctr = 25,
26120 .pme_event = 3,
26121 .pme_chipno = 1,
26122 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26123 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26124 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26125 },
26126 {
26127 .pme_name = "<M:25:3>@2",
26128 .pme_desc = "<NA>",
26129 .pme_code = 1842,
26130 .pme_flags = 0x0,
26131 .pme_numasks = 0,
26132 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26133 .pme_ctr = 25,
26134 .pme_event = 3,
26135 .pme_chipno = 2,
26136 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26137 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26138 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26139 },
26140 {
26141 .pme_name = "<M:25:3>@3",
26142 .pme_desc = "<NA>",
26143 .pme_code = 1843,
26144 .pme_flags = 0x0,
26145 .pme_numasks = 0,
26146 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26147 .pme_ctr = 25,
26148 .pme_event = 3,
26149 .pme_chipno = 3,
26150 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26151 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26152 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26153 },
26154 {
26155 .pme_name = "<M:25:3>@4",
26156 .pme_desc = "<NA>",
26157 .pme_code = 1844,
26158 .pme_flags = 0x0,
26159 .pme_numasks = 0,
26160 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26161 .pme_ctr = 25,
26162 .pme_event = 3,
26163 .pme_chipno = 4,
26164 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26165 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26166 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26167 },
26168 {
26169 .pme_name = "<M:25:3>@5",
26170 .pme_desc = "<NA>",
26171 .pme_code = 1845,
26172 .pme_flags = 0x0,
26173 .pme_numasks = 0,
26174 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26175 .pme_ctr = 25,
26176 .pme_event = 3,
26177 .pme_chipno = 5,
26178 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26179 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26180 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26181 },
26182 {
26183 .pme_name = "<M:25:3>@6",
26184 .pme_desc = "<NA>",
26185 .pme_code = 1846,
26186 .pme_flags = 0x0,
26187 .pme_numasks = 0,
26188 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26189 .pme_ctr = 25,
26190 .pme_event = 3,
26191 .pme_chipno = 6,
26192 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26193 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26194 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26195 },
26196 {
26197 .pme_name = "<M:25:3>@7",
26198 .pme_desc = "<NA>",
26199 .pme_code = 1847,
26200 .pme_flags = 0x0,
26201 .pme_numasks = 0,
26202 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26203 .pme_ctr = 25,
26204 .pme_event = 3,
26205 .pme_chipno = 7,
26206 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26207 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26208 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26209 },
26210 {
26211 .pme_name = "<M:25:3>@8",
26212 .pme_desc = "<NA>",
26213 .pme_code = 1848,
26214 .pme_flags = 0x0,
26215 .pme_numasks = 0,
26216 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26217 .pme_ctr = 25,
26218 .pme_event = 3,
26219 .pme_chipno = 8,
26220 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26221 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26222 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26223 },
26224 {
26225 .pme_name = "<M:25:3>@9",
26226 .pme_desc = "<NA>",
26227 .pme_code = 1849,
26228 .pme_flags = 0x0,
26229 .pme_numasks = 0,
26230 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26231 .pme_ctr = 25,
26232 .pme_event = 3,
26233 .pme_chipno = 9,
26234 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26235 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26236 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26237 },
26238 {
26239 .pme_name = "<M:25:3>@10",
26240 .pme_desc = "<NA>",
26241 .pme_code = 1850,
26242 .pme_flags = 0x0,
26243 .pme_numasks = 0,
26244 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26245 .pme_ctr = 25,
26246 .pme_event = 3,
26247 .pme_chipno = 10,
26248 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26249 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26250 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26251 },
26252 {
26253 .pme_name = "<M:25:3>@11",
26254 .pme_desc = "<NA>",
26255 .pme_code = 1851,
26256 .pme_flags = 0x0,
26257 .pme_numasks = 0,
26258 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26259 .pme_ctr = 25,
26260 .pme_event = 3,
26261 .pme_chipno = 11,
26262 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26263 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26264 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26265 },
26266 {
26267 .pme_name = "<M:25:3>@12",
26268 .pme_desc = "<NA>",
26269 .pme_code = 1852,
26270 .pme_flags = 0x0,
26271 .pme_numasks = 0,
26272 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26273 .pme_ctr = 25,
26274 .pme_event = 3,
26275 .pme_chipno = 12,
26276 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26277 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26278 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26279 },
26280 {
26281 .pme_name = "<M:25:3>@13",
26282 .pme_desc = "<NA>",
26283 .pme_code = 1853,
26284 .pme_flags = 0x0,
26285 .pme_numasks = 0,
26286 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26287 .pme_ctr = 25,
26288 .pme_event = 3,
26289 .pme_chipno = 13,
26290 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26291 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26292 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26293 },
26294 {
26295 .pme_name = "<M:25:3>@14",
26296 .pme_desc = "<NA>",
26297 .pme_code = 1854,
26298 .pme_flags = 0x0,
26299 .pme_numasks = 0,
26300 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26301 .pme_ctr = 25,
26302 .pme_event = 3,
26303 .pme_chipno = 14,
26304 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26305 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26306 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26307 },
26308 {
26309 .pme_name = "<M:25:3>@15",
26310 .pme_desc = "<NA>",
26311 .pme_code = 1855,
26312 .pme_flags = 0x0,
26313 .pme_numasks = 0,
26314 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26315 .pme_ctr = 25,
26316 .pme_event = 3,
26317 .pme_chipno = 15,
26318 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26319 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26320 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26321 },
26322 /* M Counter 26 Event 0 */
26323 {
26324 .pme_name = "W_SWORD_GETS@0",
26325 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)",
26326 .pme_code = 1856,
26327 .pme_flags = 0x0,
26328 .pme_numasks = 0,
26329 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26330 .pme_ctr = 26,
26331 .pme_event = 0,
26332 .pme_chipno = 0,
26333 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26334 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26335 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26336 },
26337 {
26338 .pme_name = "W_SWORD_GETS@1",
26339 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)",
26340 .pme_code = 1857,
26341 .pme_flags = 0x0,
26342 .pme_numasks = 0,
26343 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26344 .pme_ctr = 26,
26345 .pme_event = 0,
26346 .pme_chipno = 1,
26347 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26348 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26349 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26350 },
26351 {
26352 .pme_name = "W_SWORD_GETS@2",
26353 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)",
26354 .pme_code = 1858,
26355 .pme_flags = 0x0,
26356 .pme_numasks = 0,
26357 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26358 .pme_ctr = 26,
26359 .pme_event = 0,
26360 .pme_chipno = 2,
26361 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26362 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26363 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26364 },
26365 {
26366 .pme_name = "W_SWORD_GETS@3",
26367 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)",
26368 .pme_code = 1859,
26369 .pme_flags = 0x0,
26370 .pme_numasks = 0,
26371 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26372 .pme_ctr = 26,
26373 .pme_event = 0,
26374 .pme_chipno = 3,
26375 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26376 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26377 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26378 },
26379 {
26380 .pme_name = "W_SWORD_GETS@4",
26381 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)",
26382 .pme_code = 1860,
26383 .pme_flags = 0x0,
26384 .pme_numasks = 0,
26385 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26386 .pme_ctr = 26,
26387 .pme_event = 0,
26388 .pme_chipno = 4,
26389 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26390 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26391 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26392 },
26393 {
26394 .pme_name = "W_SWORD_GETS@5",
26395 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)",
26396 .pme_code = 1861,
26397 .pme_flags = 0x0,
26398 .pme_numasks = 0,
26399 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26400 .pme_ctr = 26,
26401 .pme_event = 0,
26402 .pme_chipno = 5,
26403 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26404 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26405 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26406 },
26407 {
26408 .pme_name = "W_SWORD_GETS@6",
26409 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)",
26410 .pme_code = 1862,
26411 .pme_flags = 0x0,
26412 .pme_numasks = 0,
26413 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26414 .pme_ctr = 26,
26415 .pme_event = 0,
26416 .pme_chipno = 6,
26417 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26418 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26419 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26420 },
26421 {
26422 .pme_name = "W_SWORD_GETS@7",
26423 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)",
26424 .pme_code = 1863,
26425 .pme_flags = 0x0,
26426 .pme_numasks = 0,
26427 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26428 .pme_ctr = 26,
26429 .pme_event = 0,
26430 .pme_chipno = 7,
26431 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26432 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26433 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26434 },
26435 {
26436 .pme_name = "W_SWORD_GETS@8",
26437 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)",
26438 .pme_code = 1864,
26439 .pme_flags = 0x0,
26440 .pme_numasks = 0,
26441 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26442 .pme_ctr = 26,
26443 .pme_event = 0,
26444 .pme_chipno = 8,
26445 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26446 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26447 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26448 },
26449 {
26450 .pme_name = "W_SWORD_GETS@9",
26451 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)",
26452 .pme_code = 1865,
26453 .pme_flags = 0x0,
26454 .pme_numasks = 0,
26455 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26456 .pme_ctr = 26,
26457 .pme_event = 0,
26458 .pme_chipno = 9,
26459 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26460 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26461 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26462 },
26463 {
26464 .pme_name = "W_SWORD_GETS@10",
26465 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)",
26466 .pme_code = 1866,
26467 .pme_flags = 0x0,
26468 .pme_numasks = 0,
26469 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26470 .pme_ctr = 26,
26471 .pme_event = 0,
26472 .pme_chipno = 10,
26473 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26474 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26475 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26476 },
26477 {
26478 .pme_name = "W_SWORD_GETS@11",
26479 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)",
26480 .pme_code = 1867,
26481 .pme_flags = 0x0,
26482 .pme_numasks = 0,
26483 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26484 .pme_ctr = 26,
26485 .pme_event = 0,
26486 .pme_chipno = 11,
26487 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26488 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26489 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26490 },
26491 {
26492 .pme_name = "W_SWORD_GETS@12",
26493 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)",
26494 .pme_code = 1868,
26495 .pme_flags = 0x0,
26496 .pme_numasks = 0,
26497 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26498 .pme_ctr = 26,
26499 .pme_event = 0,
26500 .pme_chipno = 12,
26501 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26502 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26503 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26504 },
26505 {
26506 .pme_name = "W_SWORD_GETS@13",
26507 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)",
26508 .pme_code = 1869,
26509 .pme_flags = 0x0,
26510 .pme_numasks = 0,
26511 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26512 .pme_ctr = 26,
26513 .pme_event = 0,
26514 .pme_chipno = 13,
26515 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26516 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26517 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26518 },
26519 {
26520 .pme_name = "W_SWORD_GETS@14",
26521 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)",
26522 .pme_code = 1870,
26523 .pme_flags = 0x0,
26524 .pme_numasks = 0,
26525 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26526 .pme_ctr = 26,
26527 .pme_event = 0,
26528 .pme_chipno = 14,
26529 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26530 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26531 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26532 },
26533 {
26534 .pme_name = "W_SWORD_GETS@15",
26535 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)",
26536 .pme_code = 1871,
26537 .pme_flags = 0x0,
26538 .pme_numasks = 0,
26539 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26540 .pme_ctr = 26,
26541 .pme_event = 0,
26542 .pme_chipno = 15,
26543 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26544 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26545 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26546 },
26547 /* M Counter 26 Event 1 */
26548 {
26549 .pme_name = "<M:26:1>@0",
26550 .pme_desc = "<NA>",
26551 .pme_code = 1872,
26552 .pme_flags = 0x0,
26553 .pme_numasks = 0,
26554 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26555 .pme_ctr = 26,
26556 .pme_event = 1,
26557 .pme_chipno = 0,
26558 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26559 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26560 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26561 },
26562 {
26563 .pme_name = "<M:26:1>@1",
26564 .pme_desc = "<NA>",
26565 .pme_code = 1873,
26566 .pme_flags = 0x0,
26567 .pme_numasks = 0,
26568 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26569 .pme_ctr = 26,
26570 .pme_event = 1,
26571 .pme_chipno = 1,
26572 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26573 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26574 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26575 },
26576 {
26577 .pme_name = "<M:26:1>@2",
26578 .pme_desc = "<NA>",
26579 .pme_code = 1874,
26580 .pme_flags = 0x0,
26581 .pme_numasks = 0,
26582 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26583 .pme_ctr = 26,
26584 .pme_event = 1,
26585 .pme_chipno = 2,
26586 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26587 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26588 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26589 },
26590 {
26591 .pme_name = "<M:26:1>@3",
26592 .pme_desc = "<NA>",
26593 .pme_code = 1875,
26594 .pme_flags = 0x0,
26595 .pme_numasks = 0,
26596 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26597 .pme_ctr = 26,
26598 .pme_event = 1,
26599 .pme_chipno = 3,
26600 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26601 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26602 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26603 },
26604 {
26605 .pme_name = "<M:26:1>@4",
26606 .pme_desc = "<NA>",
26607 .pme_code = 1876,
26608 .pme_flags = 0x0,
26609 .pme_numasks = 0,
26610 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26611 .pme_ctr = 26,
26612 .pme_event = 1,
26613 .pme_chipno = 4,
26614 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26615 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26616 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26617 },
26618 {
26619 .pme_name = "<M:26:1>@5",
26620 .pme_desc = "<NA>",
26621 .pme_code = 1877,
26622 .pme_flags = 0x0,
26623 .pme_numasks = 0,
26624 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26625 .pme_ctr = 26,
26626 .pme_event = 1,
26627 .pme_chipno = 5,
26628 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26629 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26630 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26631 },
26632 {
26633 .pme_name = "<M:26:1>@6",
26634 .pme_desc = "<NA>",
26635 .pme_code = 1878,
26636 .pme_flags = 0x0,
26637 .pme_numasks = 0,
26638 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26639 .pme_ctr = 26,
26640 .pme_event = 1,
26641 .pme_chipno = 6,
26642 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26643 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26644 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26645 },
26646 {
26647 .pme_name = "<M:26:1>@7",
26648 .pme_desc = "<NA>",
26649 .pme_code = 1879,
26650 .pme_flags = 0x0,
26651 .pme_numasks = 0,
26652 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26653 .pme_ctr = 26,
26654 .pme_event = 1,
26655 .pme_chipno = 7,
26656 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26657 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26658 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26659 },
26660 {
26661 .pme_name = "<M:26:1>@8",
26662 .pme_desc = "<NA>",
26663 .pme_code = 1880,
26664 .pme_flags = 0x0,
26665 .pme_numasks = 0,
26666 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26667 .pme_ctr = 26,
26668 .pme_event = 1,
26669 .pme_chipno = 8,
26670 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26671 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26672 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26673 },
26674 {
26675 .pme_name = "<M:26:1>@9",
26676 .pme_desc = "<NA>",
26677 .pme_code = 1881,
26678 .pme_flags = 0x0,
26679 .pme_numasks = 0,
26680 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26681 .pme_ctr = 26,
26682 .pme_event = 1,
26683 .pme_chipno = 9,
26684 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26685 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26686 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26687 },
26688 {
26689 .pme_name = "<M:26:1>@10",
26690 .pme_desc = "<NA>",
26691 .pme_code = 1882,
26692 .pme_flags = 0x0,
26693 .pme_numasks = 0,
26694 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26695 .pme_ctr = 26,
26696 .pme_event = 1,
26697 .pme_chipno = 10,
26698 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26699 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26700 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26701 },
26702 {
26703 .pme_name = "<M:26:1>@11",
26704 .pme_desc = "<NA>",
26705 .pme_code = 1883,
26706 .pme_flags = 0x0,
26707 .pme_numasks = 0,
26708 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26709 .pme_ctr = 26,
26710 .pme_event = 1,
26711 .pme_chipno = 11,
26712 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26713 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26714 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26715 },
26716 {
26717 .pme_name = "<M:26:1>@12",
26718 .pme_desc = "<NA>",
26719 .pme_code = 1884,
26720 .pme_flags = 0x0,
26721 .pme_numasks = 0,
26722 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26723 .pme_ctr = 26,
26724 .pme_event = 1,
26725 .pme_chipno = 12,
26726 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26727 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26728 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26729 },
26730 {
26731 .pme_name = "<M:26:1>@13",
26732 .pme_desc = "<NA>",
26733 .pme_code = 1885,
26734 .pme_flags = 0x0,
26735 .pme_numasks = 0,
26736 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26737 .pme_ctr = 26,
26738 .pme_event = 1,
26739 .pme_chipno = 13,
26740 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26741 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26742 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26743 },
26744 {
26745 .pme_name = "<M:26:1>@14",
26746 .pme_desc = "<NA>",
26747 .pme_code = 1886,
26748 .pme_flags = 0x0,
26749 .pme_numasks = 0,
26750 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26751 .pme_ctr = 26,
26752 .pme_event = 1,
26753 .pme_chipno = 14,
26754 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26755 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26756 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26757 },
26758 {
26759 .pme_name = "<M:26:1>@15",
26760 .pme_desc = "<NA>",
26761 .pme_code = 1887,
26762 .pme_flags = 0x0,
26763 .pme_numasks = 0,
26764 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26765 .pme_ctr = 26,
26766 .pme_event = 1,
26767 .pme_chipno = 15,
26768 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26769 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26770 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26771 },
26772 /* M Counter 26 Event 2 */
26773 {
26774 .pme_name = "<M:26:2>@0",
26775 .pme_desc = "<NA>",
26776 .pme_code = 1888,
26777 .pme_flags = 0x0,
26778 .pme_numasks = 0,
26779 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26780 .pme_ctr = 26,
26781 .pme_event = 2,
26782 .pme_chipno = 0,
26783 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26784 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26785 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26786 },
26787 {
26788 .pme_name = "<M:26:2>@1",
26789 .pme_desc = "<NA>",
26790 .pme_code = 1889,
26791 .pme_flags = 0x0,
26792 .pme_numasks = 0,
26793 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26794 .pme_ctr = 26,
26795 .pme_event = 2,
26796 .pme_chipno = 1,
26797 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26798 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26799 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26800 },
26801 {
26802 .pme_name = "<M:26:2>@2",
26803 .pme_desc = "<NA>",
26804 .pme_code = 1890,
26805 .pme_flags = 0x0,
26806 .pme_numasks = 0,
26807 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26808 .pme_ctr = 26,
26809 .pme_event = 2,
26810 .pme_chipno = 2,
26811 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26812 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26813 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26814 },
26815 {
26816 .pme_name = "<M:26:2>@3",
26817 .pme_desc = "<NA>",
26818 .pme_code = 1891,
26819 .pme_flags = 0x0,
26820 .pme_numasks = 0,
26821 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26822 .pme_ctr = 26,
26823 .pme_event = 2,
26824 .pme_chipno = 3,
26825 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26826 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26827 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26828 },
26829 {
26830 .pme_name = "<M:26:2>@4",
26831 .pme_desc = "<NA>",
26832 .pme_code = 1892,
26833 .pme_flags = 0x0,
26834 .pme_numasks = 0,
26835 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26836 .pme_ctr = 26,
26837 .pme_event = 2,
26838 .pme_chipno = 4,
26839 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26840 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26841 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26842 },
26843 {
26844 .pme_name = "<M:26:2>@5",
26845 .pme_desc = "<NA>",
26846 .pme_code = 1893,
26847 .pme_flags = 0x0,
26848 .pme_numasks = 0,
26849 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26850 .pme_ctr = 26,
26851 .pme_event = 2,
26852 .pme_chipno = 5,
26853 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26854 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26855 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26856 },
26857 {
26858 .pme_name = "<M:26:2>@6",
26859 .pme_desc = "<NA>",
26860 .pme_code = 1894,
26861 .pme_flags = 0x0,
26862 .pme_numasks = 0,
26863 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26864 .pme_ctr = 26,
26865 .pme_event = 2,
26866 .pme_chipno = 6,
26867 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26868 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26869 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26870 },
26871 {
26872 .pme_name = "<M:26:2>@7",
26873 .pme_desc = "<NA>",
26874 .pme_code = 1895,
26875 .pme_flags = 0x0,
26876 .pme_numasks = 0,
26877 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26878 .pme_ctr = 26,
26879 .pme_event = 2,
26880 .pme_chipno = 7,
26881 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26882 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26883 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26884 },
26885 {
26886 .pme_name = "<M:26:2>@8",
26887 .pme_desc = "<NA>",
26888 .pme_code = 1896,
26889 .pme_flags = 0x0,
26890 .pme_numasks = 0,
26891 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26892 .pme_ctr = 26,
26893 .pme_event = 2,
26894 .pme_chipno = 8,
26895 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26896 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26897 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26898 },
26899 {
26900 .pme_name = "<M:26:2>@9",
26901 .pme_desc = "<NA>",
26902 .pme_code = 1897,
26903 .pme_flags = 0x0,
26904 .pme_numasks = 0,
26905 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26906 .pme_ctr = 26,
26907 .pme_event = 2,
26908 .pme_chipno = 9,
26909 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26910 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26911 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26912 },
26913 {
26914 .pme_name = "<M:26:2>@10",
26915 .pme_desc = "<NA>",
26916 .pme_code = 1898,
26917 .pme_flags = 0x0,
26918 .pme_numasks = 0,
26919 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26920 .pme_ctr = 26,
26921 .pme_event = 2,
26922 .pme_chipno = 10,
26923 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26924 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26925 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26926 },
26927 {
26928 .pme_name = "<M:26:2>@11",
26929 .pme_desc = "<NA>",
26930 .pme_code = 1899,
26931 .pme_flags = 0x0,
26932 .pme_numasks = 0,
26933 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26934 .pme_ctr = 26,
26935 .pme_event = 2,
26936 .pme_chipno = 11,
26937 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26938 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26939 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26940 },
26941 {
26942 .pme_name = "<M:26:2>@12",
26943 .pme_desc = "<NA>",
26944 .pme_code = 1900,
26945 .pme_flags = 0x0,
26946 .pme_numasks = 0,
26947 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26948 .pme_ctr = 26,
26949 .pme_event = 2,
26950 .pme_chipno = 12,
26951 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26952 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26953 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26954 },
26955 {
26956 .pme_name = "<M:26:2>@13",
26957 .pme_desc = "<NA>",
26958 .pme_code = 1901,
26959 .pme_flags = 0x0,
26960 .pme_numasks = 0,
26961 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26962 .pme_ctr = 26,
26963 .pme_event = 2,
26964 .pme_chipno = 13,
26965 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26966 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26967 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26968 },
26969 {
26970 .pme_name = "<M:26:2>@14",
26971 .pme_desc = "<NA>",
26972 .pme_code = 1902,
26973 .pme_flags = 0x0,
26974 .pme_numasks = 0,
26975 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26976 .pme_ctr = 26,
26977 .pme_event = 2,
26978 .pme_chipno = 14,
26979 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26980 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26981 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26982 },
26983 {
26984 .pme_name = "<M:26:2>@15",
26985 .pme_desc = "<NA>",
26986 .pme_code = 1903,
26987 .pme_flags = 0x0,
26988 .pme_numasks = 0,
26989 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
26990 .pme_ctr = 26,
26991 .pme_event = 2,
26992 .pme_chipno = 15,
26993 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
26994 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
26995 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
26996 },
26997 /* M Counter 26 Event 3 */
26998 {
26999 .pme_name = "<M:26:3>@0",
27000 .pme_desc = "<NA>",
27001 .pme_code = 1904,
27002 .pme_flags = 0x0,
27003 .pme_numasks = 0,
27004 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27005 .pme_ctr = 26,
27006 .pme_event = 3,
27007 .pme_chipno = 0,
27008 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27009 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27010 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27011 },
27012 {
27013 .pme_name = "<M:26:3>@1",
27014 .pme_desc = "<NA>",
27015 .pme_code = 1905,
27016 .pme_flags = 0x0,
27017 .pme_numasks = 0,
27018 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27019 .pme_ctr = 26,
27020 .pme_event = 3,
27021 .pme_chipno = 1,
27022 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27023 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27024 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27025 },
27026 {
27027 .pme_name = "<M:26:3>@2",
27028 .pme_desc = "<NA>",
27029 .pme_code = 1906,
27030 .pme_flags = 0x0,
27031 .pme_numasks = 0,
27032 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27033 .pme_ctr = 26,
27034 .pme_event = 3,
27035 .pme_chipno = 2,
27036 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27037 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27038 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27039 },
27040 {
27041 .pme_name = "<M:26:3>@3",
27042 .pme_desc = "<NA>",
27043 .pme_code = 1907,
27044 .pme_flags = 0x0,
27045 .pme_numasks = 0,
27046 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27047 .pme_ctr = 26,
27048 .pme_event = 3,
27049 .pme_chipno = 3,
27050 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27051 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27052 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27053 },
27054 {
27055 .pme_name = "<M:26:3>@4",
27056 .pme_desc = "<NA>",
27057 .pme_code = 1908,
27058 .pme_flags = 0x0,
27059 .pme_numasks = 0,
27060 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27061 .pme_ctr = 26,
27062 .pme_event = 3,
27063 .pme_chipno = 4,
27064 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27065 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27066 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27067 },
27068 {
27069 .pme_name = "<M:26:3>@5",
27070 .pme_desc = "<NA>",
27071 .pme_code = 1909,
27072 .pme_flags = 0x0,
27073 .pme_numasks = 0,
27074 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27075 .pme_ctr = 26,
27076 .pme_event = 3,
27077 .pme_chipno = 5,
27078 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27079 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27080 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27081 },
27082 {
27083 .pme_name = "<M:26:3>@6",
27084 .pme_desc = "<NA>",
27085 .pme_code = 1910,
27086 .pme_flags = 0x0,
27087 .pme_numasks = 0,
27088 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27089 .pme_ctr = 26,
27090 .pme_event = 3,
27091 .pme_chipno = 6,
27092 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27093 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27094 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27095 },
27096 {
27097 .pme_name = "<M:26:3>@7",
27098 .pme_desc = "<NA>",
27099 .pme_code = 1911,
27100 .pme_flags = 0x0,
27101 .pme_numasks = 0,
27102 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27103 .pme_ctr = 26,
27104 .pme_event = 3,
27105 .pme_chipno = 7,
27106 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27107 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27108 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27109 },
27110 {
27111 .pme_name = "<M:26:3>@8",
27112 .pme_desc = "<NA>",
27113 .pme_code = 1912,
27114 .pme_flags = 0x0,
27115 .pme_numasks = 0,
27116 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27117 .pme_ctr = 26,
27118 .pme_event = 3,
27119 .pme_chipno = 8,
27120 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27121 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27122 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27123 },
27124 {
27125 .pme_name = "<M:26:3>@9",
27126 .pme_desc = "<NA>",
27127 .pme_code = 1913,
27128 .pme_flags = 0x0,
27129 .pme_numasks = 0,
27130 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27131 .pme_ctr = 26,
27132 .pme_event = 3,
27133 .pme_chipno = 9,
27134 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27135 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27136 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27137 },
27138 {
27139 .pme_name = "<M:26:3>@10",
27140 .pme_desc = "<NA>",
27141 .pme_code = 1914,
27142 .pme_flags = 0x0,
27143 .pme_numasks = 0,
27144 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27145 .pme_ctr = 26,
27146 .pme_event = 3,
27147 .pme_chipno = 10,
27148 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27149 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27150 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27151 },
27152 {
27153 .pme_name = "<M:26:3>@11",
27154 .pme_desc = "<NA>",
27155 .pme_code = 1915,
27156 .pme_flags = 0x0,
27157 .pme_numasks = 0,
27158 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27159 .pme_ctr = 26,
27160 .pme_event = 3,
27161 .pme_chipno = 11,
27162 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27163 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27164 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27165 },
27166 {
27167 .pme_name = "<M:26:3>@12",
27168 .pme_desc = "<NA>",
27169 .pme_code = 1916,
27170 .pme_flags = 0x0,
27171 .pme_numasks = 0,
27172 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27173 .pme_ctr = 26,
27174 .pme_event = 3,
27175 .pme_chipno = 12,
27176 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27177 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27178 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27179 },
27180 {
27181 .pme_name = "<M:26:3>@13",
27182 .pme_desc = "<NA>",
27183 .pme_code = 1917,
27184 .pme_flags = 0x0,
27185 .pme_numasks = 0,
27186 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27187 .pme_ctr = 26,
27188 .pme_event = 3,
27189 .pme_chipno = 13,
27190 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27191 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27192 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27193 },
27194 {
27195 .pme_name = "<M:26:3>@14",
27196 .pme_desc = "<NA>",
27197 .pme_code = 1918,
27198 .pme_flags = 0x0,
27199 .pme_numasks = 0,
27200 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27201 .pme_ctr = 26,
27202 .pme_event = 3,
27203 .pme_chipno = 14,
27204 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27205 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27206 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27207 },
27208 {
27209 .pme_name = "<M:26:3>@15",
27210 .pme_desc = "<NA>",
27211 .pme_code = 1919,
27212 .pme_flags = 0x0,
27213 .pme_numasks = 0,
27214 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27215 .pme_ctr = 26,
27216 .pme_event = 3,
27217 .pme_chipno = 15,
27218 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27219 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27220 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27221 },
27222 /* M Counter 27 Event 0 */
27223 {
27224 .pme_name = "W_SWORD_NGETS@0",
27225 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)",
27226 .pme_code = 1920,
27227 .pme_flags = 0x0,
27228 .pme_numasks = 0,
27229 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27230 .pme_ctr = 27,
27231 .pme_event = 0,
27232 .pme_chipno = 0,
27233 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27234 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27235 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27236 },
27237 {
27238 .pme_name = "W_SWORD_NGETS@1",
27239 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)",
27240 .pme_code = 1921,
27241 .pme_flags = 0x0,
27242 .pme_numasks = 0,
27243 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27244 .pme_ctr = 27,
27245 .pme_event = 0,
27246 .pme_chipno = 1,
27247 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27248 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27249 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27250 },
27251 {
27252 .pme_name = "W_SWORD_NGETS@2",
27253 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)",
27254 .pme_code = 1922,
27255 .pme_flags = 0x0,
27256 .pme_numasks = 0,
27257 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27258 .pme_ctr = 27,
27259 .pme_event = 0,
27260 .pme_chipno = 2,
27261 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27262 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27263 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27264 },
27265 {
27266 .pme_name = "W_SWORD_NGETS@3",
27267 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)",
27268 .pme_code = 1923,
27269 .pme_flags = 0x0,
27270 .pme_numasks = 0,
27271 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27272 .pme_ctr = 27,
27273 .pme_event = 0,
27274 .pme_chipno = 3,
27275 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27276 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27277 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27278 },
27279 {
27280 .pme_name = "W_SWORD_NGETS@4",
27281 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)",
27282 .pme_code = 1924,
27283 .pme_flags = 0x0,
27284 .pme_numasks = 0,
27285 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27286 .pme_ctr = 27,
27287 .pme_event = 0,
27288 .pme_chipno = 4,
27289 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27290 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27291 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27292 },
27293 {
27294 .pme_name = "W_SWORD_NGETS@5",
27295 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)",
27296 .pme_code = 1925,
27297 .pme_flags = 0x0,
27298 .pme_numasks = 0,
27299 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27300 .pme_ctr = 27,
27301 .pme_event = 0,
27302 .pme_chipno = 5,
27303 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27304 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27305 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27306 },
27307 {
27308 .pme_name = "W_SWORD_NGETS@6",
27309 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)",
27310 .pme_code = 1926,
27311 .pme_flags = 0x0,
27312 .pme_numasks = 0,
27313 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27314 .pme_ctr = 27,
27315 .pme_event = 0,
27316 .pme_chipno = 6,
27317 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27318 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27319 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27320 },
27321 {
27322 .pme_name = "W_SWORD_NGETS@7",
27323 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)",
27324 .pme_code = 1927,
27325 .pme_flags = 0x0,
27326 .pme_numasks = 0,
27327 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27328 .pme_ctr = 27,
27329 .pme_event = 0,
27330 .pme_chipno = 7,
27331 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27332 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27333 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27334 },
27335 {
27336 .pme_name = "W_SWORD_NGETS@8",
27337 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)",
27338 .pme_code = 1928,
27339 .pme_flags = 0x0,
27340 .pme_numasks = 0,
27341 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27342 .pme_ctr = 27,
27343 .pme_event = 0,
27344 .pme_chipno = 8,
27345 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27346 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27347 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27348 },
27349 {
27350 .pme_name = "W_SWORD_NGETS@9",
27351 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)",
27352 .pme_code = 1929,
27353 .pme_flags = 0x0,
27354 .pme_numasks = 0,
27355 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27356 .pme_ctr = 27,
27357 .pme_event = 0,
27358 .pme_chipno = 9,
27359 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27360 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27361 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27362 },
27363 {
27364 .pme_name = "W_SWORD_NGETS@10",
27365 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)",
27366 .pme_code = 1930,
27367 .pme_flags = 0x0,
27368 .pme_numasks = 0,
27369 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27370 .pme_ctr = 27,
27371 .pme_event = 0,
27372 .pme_chipno = 10,
27373 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27374 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27375 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27376 },
27377 {
27378 .pme_name = "W_SWORD_NGETS@11",
27379 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)",
27380 .pme_code = 1931,
27381 .pme_flags = 0x0,
27382 .pme_numasks = 0,
27383 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27384 .pme_ctr = 27,
27385 .pme_event = 0,
27386 .pme_chipno = 11,
27387 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27388 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27389 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27390 },
27391 {
27392 .pme_name = "W_SWORD_NGETS@12",
27393 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)",
27394 .pme_code = 1932,
27395 .pme_flags = 0x0,
27396 .pme_numasks = 0,
27397 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27398 .pme_ctr = 27,
27399 .pme_event = 0,
27400 .pme_chipno = 12,
27401 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27402 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27403 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27404 },
27405 {
27406 .pme_name = "W_SWORD_NGETS@13",
27407 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)",
27408 .pme_code = 1933,
27409 .pme_flags = 0x0,
27410 .pme_numasks = 0,
27411 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27412 .pme_ctr = 27,
27413 .pme_event = 0,
27414 .pme_chipno = 13,
27415 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27416 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27417 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27418 },
27419 {
27420 .pme_name = "W_SWORD_NGETS@14",
27421 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)",
27422 .pme_code = 1934,
27423 .pme_flags = 0x0,
27424 .pme_numasks = 0,
27425 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27426 .pme_ctr = 27,
27427 .pme_event = 0,
27428 .pme_chipno = 14,
27429 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27430 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27431 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27432 },
27433 {
27434 .pme_name = "W_SWORD_NGETS@15",
27435 .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)",
27436 .pme_code = 1935,
27437 .pme_flags = 0x0,
27438 .pme_numasks = 0,
27439 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27440 .pme_ctr = 27,
27441 .pme_event = 0,
27442 .pme_chipno = 15,
27443 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27444 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27445 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27446 },
27447 /* M Counter 27 Event 1 */
27448 {
27449 .pme_name = "<M:27:1>@0",
27450 .pme_desc = "<NA>",
27451 .pme_code = 1936,
27452 .pme_flags = 0x0,
27453 .pme_numasks = 0,
27454 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27455 .pme_ctr = 27,
27456 .pme_event = 1,
27457 .pme_chipno = 0,
27458 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27459 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27460 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27461 },
27462 {
27463 .pme_name = "<M:27:1>@1",
27464 .pme_desc = "<NA>",
27465 .pme_code = 1937,
27466 .pme_flags = 0x0,
27467 .pme_numasks = 0,
27468 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27469 .pme_ctr = 27,
27470 .pme_event = 1,
27471 .pme_chipno = 1,
27472 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27473 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27474 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27475 },
27476 {
27477 .pme_name = "<M:27:1>@2",
27478 .pme_desc = "<NA>",
27479 .pme_code = 1938,
27480 .pme_flags = 0x0,
27481 .pme_numasks = 0,
27482 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27483 .pme_ctr = 27,
27484 .pme_event = 1,
27485 .pme_chipno = 2,
27486 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27487 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27488 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27489 },
27490 {
27491 .pme_name = "<M:27:1>@3",
27492 .pme_desc = "<NA>",
27493 .pme_code = 1939,
27494 .pme_flags = 0x0,
27495 .pme_numasks = 0,
27496 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27497 .pme_ctr = 27,
27498 .pme_event = 1,
27499 .pme_chipno = 3,
27500 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27501 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27502 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27503 },
27504 {
27505 .pme_name = "<M:27:1>@4",
27506 .pme_desc = "<NA>",
27507 .pme_code = 1940,
27508 .pme_flags = 0x0,
27509 .pme_numasks = 0,
27510 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27511 .pme_ctr = 27,
27512 .pme_event = 1,
27513 .pme_chipno = 4,
27514 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27515 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27516 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27517 },
27518 {
27519 .pme_name = "<M:27:1>@5",
27520 .pme_desc = "<NA>",
27521 .pme_code = 1941,
27522 .pme_flags = 0x0,
27523 .pme_numasks = 0,
27524 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27525 .pme_ctr = 27,
27526 .pme_event = 1,
27527 .pme_chipno = 5,
27528 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27529 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27530 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27531 },
27532 {
27533 .pme_name = "<M:27:1>@6",
27534 .pme_desc = "<NA>",
27535 .pme_code = 1942,
27536 .pme_flags = 0x0,
27537 .pme_numasks = 0,
27538 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27539 .pme_ctr = 27,
27540 .pme_event = 1,
27541 .pme_chipno = 6,
27542 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27543 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27544 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27545 },
27546 {
27547 .pme_name = "<M:27:1>@7",
27548 .pme_desc = "<NA>",
27549 .pme_code = 1943,
27550 .pme_flags = 0x0,
27551 .pme_numasks = 0,
27552 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27553 .pme_ctr = 27,
27554 .pme_event = 1,
27555 .pme_chipno = 7,
27556 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27557 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27558 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27559 },
27560 {
27561 .pme_name = "<M:27:1>@8",
27562 .pme_desc = "<NA>",
27563 .pme_code = 1944,
27564 .pme_flags = 0x0,
27565 .pme_numasks = 0,
27566 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27567 .pme_ctr = 27,
27568 .pme_event = 1,
27569 .pme_chipno = 8,
27570 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27571 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27572 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27573 },
27574 {
27575 .pme_name = "<M:27:1>@9",
27576 .pme_desc = "<NA>",
27577 .pme_code = 1945,
27578 .pme_flags = 0x0,
27579 .pme_numasks = 0,
27580 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27581 .pme_ctr = 27,
27582 .pme_event = 1,
27583 .pme_chipno = 9,
27584 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27585 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27586 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27587 },
27588 {
27589 .pme_name = "<M:27:1>@10",
27590 .pme_desc = "<NA>",
27591 .pme_code = 1946,
27592 .pme_flags = 0x0,
27593 .pme_numasks = 0,
27594 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27595 .pme_ctr = 27,
27596 .pme_event = 1,
27597 .pme_chipno = 10,
27598 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27599 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27600 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27601 },
27602 {
27603 .pme_name = "<M:27:1>@11",
27604 .pme_desc = "<NA>",
27605 .pme_code = 1947,
27606 .pme_flags = 0x0,
27607 .pme_numasks = 0,
27608 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27609 .pme_ctr = 27,
27610 .pme_event = 1,
27611 .pme_chipno = 11,
27612 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27613 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27614 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27615 },
27616 {
27617 .pme_name = "<M:27:1>@12",
27618 .pme_desc = "<NA>",
27619 .pme_code = 1948,
27620 .pme_flags = 0x0,
27621 .pme_numasks = 0,
27622 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27623 .pme_ctr = 27,
27624 .pme_event = 1,
27625 .pme_chipno = 12,
27626 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27627 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27628 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27629 },
27630 {
27631 .pme_name = "<M:27:1>@13",
27632 .pme_desc = "<NA>",
27633 .pme_code = 1949,
27634 .pme_flags = 0x0,
27635 .pme_numasks = 0,
27636 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27637 .pme_ctr = 27,
27638 .pme_event = 1,
27639 .pme_chipno = 13,
27640 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27641 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27642 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27643 },
27644 {
27645 .pme_name = "<M:27:1>@14",
27646 .pme_desc = "<NA>",
27647 .pme_code = 1950,
27648 .pme_flags = 0x0,
27649 .pme_numasks = 0,
27650 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27651 .pme_ctr = 27,
27652 .pme_event = 1,
27653 .pme_chipno = 14,
27654 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27655 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27656 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27657 },
27658 {
27659 .pme_name = "<M:27:1>@15",
27660 .pme_desc = "<NA>",
27661 .pme_code = 1951,
27662 .pme_flags = 0x0,
27663 .pme_numasks = 0,
27664 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27665 .pme_ctr = 27,
27666 .pme_event = 1,
27667 .pme_chipno = 15,
27668 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27669 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27670 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27671 },
27672 /* M Counter 27 Event 2 */
27673 {
27674 .pme_name = "<M:27:2>@0",
27675 .pme_desc = "<NA>",
27676 .pme_code = 1952,
27677 .pme_flags = 0x0,
27678 .pme_numasks = 0,
27679 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27680 .pme_ctr = 27,
27681 .pme_event = 2,
27682 .pme_chipno = 0,
27683 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27684 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27685 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27686 },
27687 {
27688 .pme_name = "<M:27:2>@1",
27689 .pme_desc = "<NA>",
27690 .pme_code = 1953,
27691 .pme_flags = 0x0,
27692 .pme_numasks = 0,
27693 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27694 .pme_ctr = 27,
27695 .pme_event = 2,
27696 .pme_chipno = 1,
27697 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27698 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27699 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27700 },
27701 {
27702 .pme_name = "<M:27:2>@2",
27703 .pme_desc = "<NA>",
27704 .pme_code = 1954,
27705 .pme_flags = 0x0,
27706 .pme_numasks = 0,
27707 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27708 .pme_ctr = 27,
27709 .pme_event = 2,
27710 .pme_chipno = 2,
27711 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27712 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27713 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27714 },
27715 {
27716 .pme_name = "<M:27:2>@3",
27717 .pme_desc = "<NA>",
27718 .pme_code = 1955,
27719 .pme_flags = 0x0,
27720 .pme_numasks = 0,
27721 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27722 .pme_ctr = 27,
27723 .pme_event = 2,
27724 .pme_chipno = 3,
27725 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27726 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27727 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27728 },
27729 {
27730 .pme_name = "<M:27:2>@4",
27731 .pme_desc = "<NA>",
27732 .pme_code = 1956,
27733 .pme_flags = 0x0,
27734 .pme_numasks = 0,
27735 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27736 .pme_ctr = 27,
27737 .pme_event = 2,
27738 .pme_chipno = 4,
27739 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27740 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27741 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27742 },
27743 {
27744 .pme_name = "<M:27:2>@5",
27745 .pme_desc = "<NA>",
27746 .pme_code = 1957,
27747 .pme_flags = 0x0,
27748 .pme_numasks = 0,
27749 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27750 .pme_ctr = 27,
27751 .pme_event = 2,
27752 .pme_chipno = 5,
27753 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27754 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27755 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27756 },
27757 {
27758 .pme_name = "<M:27:2>@6",
27759 .pme_desc = "<NA>",
27760 .pme_code = 1958,
27761 .pme_flags = 0x0,
27762 .pme_numasks = 0,
27763 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27764 .pme_ctr = 27,
27765 .pme_event = 2,
27766 .pme_chipno = 6,
27767 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27768 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27769 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27770 },
27771 {
27772 .pme_name = "<M:27:2>@7",
27773 .pme_desc = "<NA>",
27774 .pme_code = 1959,
27775 .pme_flags = 0x0,
27776 .pme_numasks = 0,
27777 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27778 .pme_ctr = 27,
27779 .pme_event = 2,
27780 .pme_chipno = 7,
27781 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27782 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27783 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27784 },
27785 {
27786 .pme_name = "<M:27:2>@8",
27787 .pme_desc = "<NA>",
27788 .pme_code = 1960,
27789 .pme_flags = 0x0,
27790 .pme_numasks = 0,
27791 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27792 .pme_ctr = 27,
27793 .pme_event = 2,
27794 .pme_chipno = 8,
27795 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27796 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27797 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27798 },
27799 {
27800 .pme_name = "<M:27:2>@9",
27801 .pme_desc = "<NA>",
27802 .pme_code = 1961,
27803 .pme_flags = 0x0,
27804 .pme_numasks = 0,
27805 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27806 .pme_ctr = 27,
27807 .pme_event = 2,
27808 .pme_chipno = 9,
27809 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27810 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27811 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27812 },
27813 {
27814 .pme_name = "<M:27:2>@10",
27815 .pme_desc = "<NA>",
27816 .pme_code = 1962,
27817 .pme_flags = 0x0,
27818 .pme_numasks = 0,
27819 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27820 .pme_ctr = 27,
27821 .pme_event = 2,
27822 .pme_chipno = 10,
27823 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27824 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27825 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27826 },
27827 {
27828 .pme_name = "<M:27:2>@11",
27829 .pme_desc = "<NA>",
27830 .pme_code = 1963,
27831 .pme_flags = 0x0,
27832 .pme_numasks = 0,
27833 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27834 .pme_ctr = 27,
27835 .pme_event = 2,
27836 .pme_chipno = 11,
27837 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27838 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27839 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27840 },
27841 {
27842 .pme_name = "<M:27:2>@12",
27843 .pme_desc = "<NA>",
27844 .pme_code = 1964,
27845 .pme_flags = 0x0,
27846 .pme_numasks = 0,
27847 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27848 .pme_ctr = 27,
27849 .pme_event = 2,
27850 .pme_chipno = 12,
27851 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27852 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27853 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27854 },
27855 {
27856 .pme_name = "<M:27:2>@13",
27857 .pme_desc = "<NA>",
27858 .pme_code = 1965,
27859 .pme_flags = 0x0,
27860 .pme_numasks = 0,
27861 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27862 .pme_ctr = 27,
27863 .pme_event = 2,
27864 .pme_chipno = 13,
27865 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27866 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27867 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27868 },
27869 {
27870 .pme_name = "<M:27:2>@14",
27871 .pme_desc = "<NA>",
27872 .pme_code = 1966,
27873 .pme_flags = 0x0,
27874 .pme_numasks = 0,
27875 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27876 .pme_ctr = 27,
27877 .pme_event = 2,
27878 .pme_chipno = 14,
27879 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27880 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27881 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27882 },
27883 {
27884 .pme_name = "<M:27:2>@15",
27885 .pme_desc = "<NA>",
27886 .pme_code = 1967,
27887 .pme_flags = 0x0,
27888 .pme_numasks = 0,
27889 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27890 .pme_ctr = 27,
27891 .pme_event = 2,
27892 .pme_chipno = 15,
27893 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27894 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27895 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27896 },
27897 /* M Counter 27 Event 3 */
27898 {
27899 .pme_name = "<M:27:3>@0",
27900 .pme_desc = "<NA>",
27901 .pme_code = 1968,
27902 .pme_flags = 0x0,
27903 .pme_numasks = 0,
27904 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27905 .pme_ctr = 27,
27906 .pme_event = 3,
27907 .pme_chipno = 0,
27908 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27909 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27910 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27911 },
27912 {
27913 .pme_name = "<M:27:3>@1",
27914 .pme_desc = "<NA>",
27915 .pme_code = 1969,
27916 .pme_flags = 0x0,
27917 .pme_numasks = 0,
27918 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27919 .pme_ctr = 27,
27920 .pme_event = 3,
27921 .pme_chipno = 1,
27922 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27923 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27924 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27925 },
27926 {
27927 .pme_name = "<M:27:3>@2",
27928 .pme_desc = "<NA>",
27929 .pme_code = 1970,
27930 .pme_flags = 0x0,
27931 .pme_numasks = 0,
27932 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27933 .pme_ctr = 27,
27934 .pme_event = 3,
27935 .pme_chipno = 2,
27936 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27937 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27938 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27939 },
27940 {
27941 .pme_name = "<M:27:3>@3",
27942 .pme_desc = "<NA>",
27943 .pme_code = 1971,
27944 .pme_flags = 0x0,
27945 .pme_numasks = 0,
27946 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27947 .pme_ctr = 27,
27948 .pme_event = 3,
27949 .pme_chipno = 3,
27950 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27951 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27952 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27953 },
27954 {
27955 .pme_name = "<M:27:3>@4",
27956 .pme_desc = "<NA>",
27957 .pme_code = 1972,
27958 .pme_flags = 0x0,
27959 .pme_numasks = 0,
27960 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27961 .pme_ctr = 27,
27962 .pme_event = 3,
27963 .pme_chipno = 4,
27964 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27965 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27966 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27967 },
27968 {
27969 .pme_name = "<M:27:3>@5",
27970 .pme_desc = "<NA>",
27971 .pme_code = 1973,
27972 .pme_flags = 0x0,
27973 .pme_numasks = 0,
27974 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27975 .pme_ctr = 27,
27976 .pme_event = 3,
27977 .pme_chipno = 5,
27978 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27979 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27980 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27981 },
27982 {
27983 .pme_name = "<M:27:3>@6",
27984 .pme_desc = "<NA>",
27985 .pme_code = 1974,
27986 .pme_flags = 0x0,
27987 .pme_numasks = 0,
27988 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
27989 .pme_ctr = 27,
27990 .pme_event = 3,
27991 .pme_chipno = 6,
27992 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
27993 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
27994 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
27995 },
27996 {
27997 .pme_name = "<M:27:3>@7",
27998 .pme_desc = "<NA>",
27999 .pme_code = 1975,
28000 .pme_flags = 0x0,
28001 .pme_numasks = 0,
28002 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28003 .pme_ctr = 27,
28004 .pme_event = 3,
28005 .pme_chipno = 7,
28006 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28007 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28008 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28009 },
28010 {
28011 .pme_name = "<M:27:3>@8",
28012 .pme_desc = "<NA>",
28013 .pme_code = 1976,
28014 .pme_flags = 0x0,
28015 .pme_numasks = 0,
28016 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28017 .pme_ctr = 27,
28018 .pme_event = 3,
28019 .pme_chipno = 8,
28020 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28021 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28022 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28023 },
28024 {
28025 .pme_name = "<M:27:3>@9",
28026 .pme_desc = "<NA>",
28027 .pme_code = 1977,
28028 .pme_flags = 0x0,
28029 .pme_numasks = 0,
28030 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28031 .pme_ctr = 27,
28032 .pme_event = 3,
28033 .pme_chipno = 9,
28034 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28035 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28036 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28037 },
28038 {
28039 .pme_name = "<M:27:3>@10",
28040 .pme_desc = "<NA>",
28041 .pme_code = 1978,
28042 .pme_flags = 0x0,
28043 .pme_numasks = 0,
28044 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28045 .pme_ctr = 27,
28046 .pme_event = 3,
28047 .pme_chipno = 10,
28048 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28049 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28050 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28051 },
28052 {
28053 .pme_name = "<M:27:3>@11",
28054 .pme_desc = "<NA>",
28055 .pme_code = 1979,
28056 .pme_flags = 0x0,
28057 .pme_numasks = 0,
28058 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28059 .pme_ctr = 27,
28060 .pme_event = 3,
28061 .pme_chipno = 11,
28062 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28063 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28064 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28065 },
28066 {
28067 .pme_name = "<M:27:3>@12",
28068 .pme_desc = "<NA>",
28069 .pme_code = 1980,
28070 .pme_flags = 0x0,
28071 .pme_numasks = 0,
28072 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28073 .pme_ctr = 27,
28074 .pme_event = 3,
28075 .pme_chipno = 12,
28076 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28077 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28078 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28079 },
28080 {
28081 .pme_name = "<M:27:3>@13",
28082 .pme_desc = "<NA>",
28083 .pme_code = 1981,
28084 .pme_flags = 0x0,
28085 .pme_numasks = 0,
28086 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28087 .pme_ctr = 27,
28088 .pme_event = 3,
28089 .pme_chipno = 13,
28090 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28091 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28092 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28093 },
28094 {
28095 .pme_name = "<M:27:3>@14",
28096 .pme_desc = "<NA>",
28097 .pme_code = 1982,
28098 .pme_flags = 0x0,
28099 .pme_numasks = 0,
28100 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28101 .pme_ctr = 27,
28102 .pme_event = 3,
28103 .pme_chipno = 14,
28104 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28105 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28106 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28107 },
28108 {
28109 .pme_name = "<M:27:3>@15",
28110 .pme_desc = "<NA>",
28111 .pme_code = 1983,
28112 .pme_flags = 0x0,
28113 .pme_numasks = 0,
28114 .pme_chip = PME_CRAYX2_CHIP_MEMORY,
28115 .pme_ctr = 27,
28116 .pme_event = 3,
28117 .pme_chipno = 15,
28118 .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE,
28119 .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP,
28120 .pme_nchips = PME_CRAYX2_MEMORY_CHIPS
28121 },
28122};
28123
28124#define PME_CRAYX2_CYCLES 0
28125#define PME_CRAYX2_INSTR_GRADUATED 4
28126#define PME_CRAYX2_EVENT_COUNT (sizeof(crayx2_pe)/sizeof(pme_crayx2_entry_t))
28127
28128#endif /* __CRAYX2_EVENTS_H__ */
crayx2_pe
static pme_crayx2_entry_t crayx2_pe[]
Definition: crayx2_events.h:40
PMU_CRAYX2_CPU_PMD_BASE
#define PMU_CRAYX2_CPU_PMD_BASE
Definition: pfmlib_crayx2.h:94
PMU_CRAYX2_MEMORY_PMD_BASE
#define PMU_CRAYX2_MEMORY_PMD_BASE
Definition: pfmlib_crayx2.h:96
PMU_CRAYX2_CACHE_PMD_BASE
#define PMU_CRAYX2_CACHE_PMD_BASE
Definition: pfmlib_crayx2.h:95
pfmlib_crayx2_priv.h
PME_CRAYX2_CPU_CTRS_PER_CHIP
#define PME_CRAYX2_CPU_CTRS_PER_CHIP
Definition: pfmlib_crayx2_priv.h:48
PME_CRAYX2_CHIP_MEMORY
#define PME_CRAYX2_CHIP_MEMORY
Definition: pfmlib_crayx2_priv.h:34
PME_CRAYX2_CACHE_CHIPS
#define PME_CRAYX2_CACHE_CHIPS
Definition: pfmlib_crayx2_priv.h:39
PME_CRAYX2_MEMORY_CTRS_PER_CHIP
#define PME_CRAYX2_MEMORY_CTRS_PER_CHIP
Definition: pfmlib_crayx2_priv.h:50
PME_CRAYX2_CPU_CHIPS
#define PME_CRAYX2_CPU_CHIPS
Definition: pfmlib_crayx2_priv.h:38
PME_CRAYX2_MEMORY_CHIPS
#define PME_CRAYX2_MEMORY_CHIPS
Definition: pfmlib_crayx2_priv.h:40
PME_CRAYX2_CHIP_CPU
#define PME_CRAYX2_CHIP_CPU
Definition: pfmlib_crayx2_priv.h:32
PME_CRAYX2_CHIP_CACHE
#define PME_CRAYX2_CHIP_CACHE
Definition: pfmlib_crayx2_priv.h:33
PME_CRAYX2_CACHE_CTRS_PER_CHIP
#define PME_CRAYX2_CACHE_CTRS_PER_CHIP
Definition: pfmlib_crayx2_priv.h:49
pme_crayx2_entry_t
Definition: pfmlib_crayx2_priv.h:74
pme_crayx2_entry_t::pme_name
const char * pme_name
Definition: pfmlib_crayx2_priv.h:75