Accurate Cache and TLB Characterization Using Hardware Counters

TitleAccurate Cache and TLB Characterization Using Hardware Counters
Publication TypeConference Paper
Year of Publication2004
AuthorsDongarra, J., S. Moore, P. Mucci, K. Seymour, and H. You
Conference NameInternational Conference on Computational Science (ICCS 2004)
Date Published2004-06
Conference LocationKrakow, Poland
Keywordsgco, lacsi, papi

We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions.

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