@conference {dongarra2004accurate,
	title = {Accurate Cache and {TLB} Characterization Using Hardware Counters},
	booktitle = {International Conference on Computational Science (ICCS 2004)},
	year = {2004},
	month = {2004-06},
	publisher = {Springer},
	organization = {Springer},
	address = {Krakow, Poland},
	abstract = {We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions.},
	keywords = {gco, lacsi, papi},
	doi = {https://doi.org/10.1007/978-3-540-24688-6_57},
	author = {Jack Dongarra and Shirley Moore and Phil Mucci and Keith Seymour and Haihang You}
}
