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Macros | |
| #define | PAPI_PRESET_MASK ((int)0x80000000) |
| #define | PAPI_NATIVE_MASK ((int)0x40000000) |
| #define | PAPI_UE_MASK ((int)0xC0000000) |
| #define | PAPI_PRESET_AND_MASK 0x7FFFFFFF |
| #define | PAPI_NATIVE_AND_MASK 0xBFFFFFFF /* this masks just the native bit */ |
| #define | PAPI_UE_AND_MASK 0x3FFFFFFF |
| #define | PAPI_MAX_PRESET_EVENTS 128 /*The maxmimum number of preset events */ |
| #define | PAPI_MAX_USER_EVENTS 50 /*The maxmimum number of user defined events */ |
| #define | USER_EVENT_OPERATION_LEN 512 /*The maximum length of the operation string for user defined events */ |
| #define | PAPI_L1_DCM (PAPI_L1_DCM_idx | PAPI_PRESET_MASK) /*Level 1 data cache misses */ |
| #define | PAPI_L1_ICM (PAPI_L1_ICM_idx | PAPI_PRESET_MASK) /*Level 1 instruction cache misses */ |
| #define | PAPI_L2_DCM (PAPI_L2_DCM_idx | PAPI_PRESET_MASK) /*Level 2 data cache misses */ |
| #define | PAPI_L2_ICM (PAPI_L2_ICM_idx | PAPI_PRESET_MASK) /*Level 2 instruction cache misses */ |
| #define | PAPI_L3_DCM (PAPI_L3_DCM_idx | PAPI_PRESET_MASK) /*Level 3 data cache misses */ |
| #define | PAPI_L3_ICM (PAPI_L3_ICM_idx | PAPI_PRESET_MASK) /*Level 3 instruction cache misses */ |
| #define | PAPI_L1_TCM (PAPI_L1_TCM_idx | PAPI_PRESET_MASK) /*Level 1 total cache misses */ |
| #define | PAPI_L2_TCM (PAPI_L2_TCM_idx | PAPI_PRESET_MASK) /*Level 2 total cache misses */ |
| #define | PAPI_L3_TCM (PAPI_L3_TCM_idx | PAPI_PRESET_MASK) /*Level 3 total cache misses */ |
| #define | PAPI_CA_SNP (PAPI_CA_SNP_idx | PAPI_PRESET_MASK) /*Snoops */ |
| #define | PAPI_CA_SHR (PAPI_CA_SHR_idx | PAPI_PRESET_MASK) /*Request for shared cache line (SMP) */ |
| #define | PAPI_CA_CLN (PAPI_CA_CLN_idx | PAPI_PRESET_MASK) /*Request for clean cache line (SMP) */ |
| #define | PAPI_CA_INV (PAPI_CA_INV_idx | PAPI_PRESET_MASK) /*Request for cache line Invalidation (SMP) */ |
| #define | PAPI_CA_ITV (PAPI_CA_ITV_idx | PAPI_PRESET_MASK) /*Request for cache line Intervention (SMP) */ |
| #define | PAPI_L3_LDM (PAPI_L3_LDM_idx | PAPI_PRESET_MASK) /*Level 3 load misses */ |
| #define | PAPI_L3_STM (PAPI_L3_STM_idx | PAPI_PRESET_MASK) /*Level 3 store misses */ |
| #define | PAPI_BRU_IDL (PAPI_BRU_IDL_idx | PAPI_PRESET_MASK) /*Cycles branch units are idle */ |
| #define | PAPI_FXU_IDL (PAPI_FXU_IDL_idx | PAPI_PRESET_MASK) /*Cycles integer units are idle */ |
| #define | PAPI_FPU_IDL (PAPI_FPU_IDL_idx | PAPI_PRESET_MASK) /*Cycles floating point units are idle */ |
| #define | PAPI_LSU_IDL (PAPI_LSU_IDL_idx | PAPI_PRESET_MASK) /*Cycles load/store units are idle */ |
| #define | PAPI_TLB_DM (PAPI_TLB_DM_idx | PAPI_PRESET_MASK) /*Data translation lookaside buffer misses */ |
| #define | PAPI_TLB_IM (PAPI_TLB_IM_idx | PAPI_PRESET_MASK) /*Instr translation lookaside buffer misses */ |
| #define | PAPI_TLB_TL (PAPI_TLB_TL_idx | PAPI_PRESET_MASK) /*Total translation lookaside buffer misses */ |
| #define | PAPI_L1_LDM (PAPI_L1_LDM_idx | PAPI_PRESET_MASK) /*Level 1 load misses */ |
| #define | PAPI_L1_STM (PAPI_L1_STM_idx | PAPI_PRESET_MASK) /*Level 1 store misses */ |
| #define | PAPI_L2_LDM (PAPI_L2_LDM_idx | PAPI_PRESET_MASK) /*Level 2 load misses */ |
| #define | PAPI_L2_STM (PAPI_L2_STM_idx | PAPI_PRESET_MASK) /*Level 2 store misses */ |
| #define | PAPI_BTAC_M (PAPI_BTAC_M_idx | PAPI_PRESET_MASK) /*BTAC miss */ |
| #define | PAPI_PRF_DM (PAPI_PRF_DM_idx | PAPI_PRESET_MASK) /*Prefetch data instruction caused a miss */ |
| #define | PAPI_L3_DCH (PAPI_L3_DCH_idx | PAPI_PRESET_MASK) /*Level 3 Data Cache Hit */ |
| #define | PAPI_TLB_SD (PAPI_TLB_SD_idx | PAPI_PRESET_MASK) /*Xlation lookaside buffer shootdowns (SMP) */ |
| #define | PAPI_CSR_FAL (PAPI_CSR_FAL_idx | PAPI_PRESET_MASK) /*Failed store conditional instructions */ |
| #define | PAPI_CSR_SUC (PAPI_CSR_SUC_idx | PAPI_PRESET_MASK) /*Successful store conditional instructions */ |
| #define | PAPI_CSR_TOT (PAPI_CSR_TOT_idx | PAPI_PRESET_MASK) /*Total store conditional instructions */ |
| #define | PAPI_MEM_SCY (PAPI_MEM_SCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Access */ |
| #define | PAPI_MEM_RCY (PAPI_MEM_RCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Read */ |
| #define | PAPI_MEM_WCY (PAPI_MEM_WCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Write */ |
| #define | PAPI_STL_ICY (PAPI_STL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Issue */ |
| #define | PAPI_FUL_ICY (PAPI_FUL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Issue */ |
| #define | PAPI_STL_CCY (PAPI_STL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Completion */ |
| #define | PAPI_FUL_CCY (PAPI_FUL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Completion */ |
| #define | PAPI_HW_INT (PAPI_HW_INT_idx | PAPI_PRESET_MASK) /*Hardware interrupts */ |
| #define | PAPI_BR_UCN (PAPI_BR_UCN_idx | PAPI_PRESET_MASK) /*Unconditional branch instructions executed */ |
| #define | PAPI_BR_CN (PAPI_BR_CN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions executed */ |
| #define | PAPI_BR_TKN (PAPI_BR_TKN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions taken */ |
| #define | PAPI_BR_NTK (PAPI_BR_NTK_idx | PAPI_PRESET_MASK) /*Conditional branch instructions not taken */ |
| #define | PAPI_BR_MSP (PAPI_BR_MSP_idx | PAPI_PRESET_MASK) /*Conditional branch instructions mispred */ |
| #define | PAPI_BR_PRC (PAPI_BR_PRC_idx | PAPI_PRESET_MASK) /*Conditional branch instructions corr. pred */ |
| #define | PAPI_FMA_INS (PAPI_FMA_INS_idx | PAPI_PRESET_MASK) /*FMA instructions completed */ |
| #define | PAPI_TOT_IIS (PAPI_TOT_IIS_idx | PAPI_PRESET_MASK) /*Total instructions issued */ |
| #define | PAPI_TOT_INS (PAPI_TOT_INS_idx | PAPI_PRESET_MASK) /*Total instructions executed */ |
| #define | PAPI_INT_INS (PAPI_INT_INS_idx | PAPI_PRESET_MASK) /*Integer instructions executed */ |
| #define | PAPI_FP_INS (PAPI_FP_INS_idx | PAPI_PRESET_MASK) /*Floating point instructions executed */ |
| #define | PAPI_LD_INS (PAPI_LD_INS_idx | PAPI_PRESET_MASK) /*Load instructions executed */ |
| #define | PAPI_SR_INS (PAPI_SR_INS_idx | PAPI_PRESET_MASK) /*Store instructions executed */ |
| #define | PAPI_BR_INS (PAPI_BR_INS_idx | PAPI_PRESET_MASK) /*Total branch instructions executed */ |
| #define | PAPI_VEC_INS (PAPI_VEC_INS_idx | PAPI_PRESET_MASK) /*Vector/SIMD instructions executed (could include integer) */ |
| #define | PAPI_RES_STL (PAPI_RES_STL_idx | PAPI_PRESET_MASK) /*Cycles processor is stalled on resource */ |
| #define | PAPI_FP_STAL (PAPI_FP_STAL_idx | PAPI_PRESET_MASK) /*Cycles any FP units are stalled */ |
| #define | PAPI_TOT_CYC (PAPI_TOT_CYC_idx | PAPI_PRESET_MASK) /*Total cycles executed */ |
| #define | PAPI_LST_INS (PAPI_LST_INS_idx | PAPI_PRESET_MASK) /*Total load/store inst. executed */ |
| #define | PAPI_SYC_INS (PAPI_SYC_INS_idx | PAPI_PRESET_MASK) /*Sync. inst. executed */ |
| #define | PAPI_L1_DCH (PAPI_L1_DCH_idx | PAPI_PRESET_MASK) /*L1 D Cache Hit */ |
| #define | PAPI_L2_DCH (PAPI_L2_DCH_idx | PAPI_PRESET_MASK) /*L2 D Cache Hit */ |
| #define | PAPI_L1_DCA (PAPI_L1_DCA_idx | PAPI_PRESET_MASK) /*L1 D Cache Access */ |
| #define | PAPI_L2_DCA (PAPI_L2_DCA_idx | PAPI_PRESET_MASK) /*L2 D Cache Access */ |
| #define | PAPI_L3_DCA (PAPI_L3_DCA_idx | PAPI_PRESET_MASK) /*L3 D Cache Access */ |
| #define | PAPI_L1_DCR (PAPI_L1_DCR_idx | PAPI_PRESET_MASK) /*L1 D Cache Read */ |
| #define | PAPI_L2_DCR (PAPI_L2_DCR_idx | PAPI_PRESET_MASK) /*L2 D Cache Read */ |
| #define | PAPI_L3_DCR (PAPI_L3_DCR_idx | PAPI_PRESET_MASK) /*L3 D Cache Read */ |
| #define | PAPI_L1_DCW (PAPI_L1_DCW_idx | PAPI_PRESET_MASK) /*L1 D Cache Write */ |
| #define | PAPI_L2_DCW (PAPI_L2_DCW_idx | PAPI_PRESET_MASK) /*L2 D Cache Write */ |
| #define | PAPI_L3_DCW (PAPI_L3_DCW_idx | PAPI_PRESET_MASK) /*L3 D Cache Write */ |
| #define | PAPI_L1_ICH (PAPI_L1_ICH_idx | PAPI_PRESET_MASK) /*L1 instruction cache hits */ |
| #define | PAPI_L2_ICH (PAPI_L2_ICH_idx | PAPI_PRESET_MASK) /*L2 instruction cache hits */ |
| #define | PAPI_L3_ICH (PAPI_L3_ICH_idx | PAPI_PRESET_MASK) /*L3 instruction cache hits */ |
| #define | PAPI_L1_ICA (PAPI_L1_ICA_idx | PAPI_PRESET_MASK) /*L1 instruction cache accesses */ |
| #define | PAPI_L2_ICA (PAPI_L2_ICA_idx | PAPI_PRESET_MASK) /*L2 instruction cache accesses */ |
| #define | PAPI_L3_ICA (PAPI_L3_ICA_idx | PAPI_PRESET_MASK) /*L3 instruction cache accesses */ |
| #define | PAPI_L1_ICR (PAPI_L1_ICR_idx | PAPI_PRESET_MASK) /*L1 instruction cache reads */ |
| #define | PAPI_L2_ICR (PAPI_L2_ICR_idx | PAPI_PRESET_MASK) /*L2 instruction cache reads */ |
| #define | PAPI_L3_ICR (PAPI_L3_ICR_idx | PAPI_PRESET_MASK) /*L3 instruction cache reads */ |
| #define | PAPI_L1_ICW (PAPI_L1_ICW_idx | PAPI_PRESET_MASK) /*L1 instruction cache writes */ |
| #define | PAPI_L2_ICW (PAPI_L2_ICW_idx | PAPI_PRESET_MASK) /*L2 instruction cache writes */ |
| #define | PAPI_L3_ICW (PAPI_L3_ICW_idx | PAPI_PRESET_MASK) /*L3 instruction cache writes */ |
| #define | PAPI_L1_TCH (PAPI_L1_TCH_idx | PAPI_PRESET_MASK) /*L1 total cache hits */ |
| #define | PAPI_L2_TCH (PAPI_L2_TCH_idx | PAPI_PRESET_MASK) /*L2 total cache hits */ |
| #define | PAPI_L3_TCH (PAPI_L3_TCH_idx | PAPI_PRESET_MASK) /*L3 total cache hits */ |
| #define | PAPI_L1_TCA (PAPI_L1_TCA_idx | PAPI_PRESET_MASK) /*L1 total cache accesses */ |
| #define | PAPI_L2_TCA (PAPI_L2_TCA_idx | PAPI_PRESET_MASK) /*L2 total cache accesses */ |
| #define | PAPI_L3_TCA (PAPI_L3_TCA_idx | PAPI_PRESET_MASK) /*L3 total cache accesses */ |
| #define | PAPI_L1_TCR (PAPI_L1_TCR_idx | PAPI_PRESET_MASK) /*L1 total cache reads */ |
| #define | PAPI_L2_TCR (PAPI_L2_TCR_idx | PAPI_PRESET_MASK) /*L2 total cache reads */ |
| #define | PAPI_L3_TCR (PAPI_L3_TCR_idx | PAPI_PRESET_MASK) /*L3 total cache reads */ |
| #define | PAPI_L1_TCW (PAPI_L1_TCW_idx | PAPI_PRESET_MASK) /*L1 total cache writes */ |
| #define | PAPI_L2_TCW (PAPI_L2_TCW_idx | PAPI_PRESET_MASK) /*L2 total cache writes */ |
| #define | PAPI_L3_TCW (PAPI_L3_TCW_idx | PAPI_PRESET_MASK) /*L3 total cache writes */ |
| #define | PAPI_FML_INS (PAPI_FML_INS_idx | PAPI_PRESET_MASK) /*FM ins */ |
| #define | PAPI_FAD_INS (PAPI_FAD_INS_idx | PAPI_PRESET_MASK) /*FA ins */ |
| #define | PAPI_FDV_INS (PAPI_FDV_INS_idx | PAPI_PRESET_MASK) /*FD ins */ |
| #define | PAPI_FSQ_INS (PAPI_FSQ_INS_idx | PAPI_PRESET_MASK) /*FSq ins */ |
| #define | PAPI_FNV_INS (PAPI_FNV_INS_idx | PAPI_PRESET_MASK) /*Finv ins */ |
| #define | PAPI_FP_OPS (PAPI_FP_OPS_idx | PAPI_PRESET_MASK) /*Floating point operations executed */ |
| #define | PAPI_SP_OPS (PAPI_SP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled single precision vector operations */ |
| #define | PAPI_DP_OPS (PAPI_DP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled double precision vector operations */ |
| #define | PAPI_VEC_SP (PAPI_VEC_SP_idx | PAPI_PRESET_MASK) /* Single precision vector/SIMD instructions */ |
| #define | PAPI_VEC_DP (PAPI_VEC_DP_idx | PAPI_PRESET_MASK) /* Double precision vector/SIMD instructions */ |
| #define | PAPI_REF_CYC (PAPI_REF_CYC_idx | PAPI_PRESET_MASK) /* Reference clock cycles */ |
| #define | PAPI_END (PAPI_END_idx | PAPI_PRESET_MASK) /*This should always be last! */ |
Macro Definition Documentation
◆ PAPI_BR_CN
| #define PAPI_BR_CN (PAPI_BR_CN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions executed */ |
Definition at line 213 of file papiStdEventDefs.h.
◆ PAPI_BR_INS
| #define PAPI_BR_INS (PAPI_BR_INS_idx | PAPI_PRESET_MASK) /*Total branch instructions executed */ |
Definition at line 225 of file papiStdEventDefs.h.
◆ PAPI_BR_MSP
| #define PAPI_BR_MSP (PAPI_BR_MSP_idx | PAPI_PRESET_MASK) /*Conditional branch instructions mispred */ |
Definition at line 216 of file papiStdEventDefs.h.
◆ PAPI_BR_NTK
| #define PAPI_BR_NTK (PAPI_BR_NTK_idx | PAPI_PRESET_MASK) /*Conditional branch instructions not taken */ |
Definition at line 215 of file papiStdEventDefs.h.
◆ PAPI_BR_PRC
| #define PAPI_BR_PRC (PAPI_BR_PRC_idx | PAPI_PRESET_MASK) /*Conditional branch instructions corr. pred */ |
Definition at line 217 of file papiStdEventDefs.h.
◆ PAPI_BR_TKN
| #define PAPI_BR_TKN (PAPI_BR_TKN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions taken */ |
Definition at line 214 of file papiStdEventDefs.h.
◆ PAPI_BR_UCN
| #define PAPI_BR_UCN (PAPI_BR_UCN_idx | PAPI_PRESET_MASK) /*Unconditional branch instructions executed */ |
Definition at line 212 of file papiStdEventDefs.h.
◆ PAPI_BRU_IDL
| #define PAPI_BRU_IDL (PAPI_BRU_IDL_idx | PAPI_PRESET_MASK) /*Cycles branch units are idle */ |
Definition at line 186 of file papiStdEventDefs.h.
◆ PAPI_BTAC_M
| #define PAPI_BTAC_M (PAPI_BTAC_M_idx | PAPI_PRESET_MASK) /*BTAC miss */ |
Definition at line 197 of file papiStdEventDefs.h.
◆ PAPI_CA_CLN
| #define PAPI_CA_CLN (PAPI_CA_CLN_idx | PAPI_PRESET_MASK) /*Request for clean cache line (SMP) */ |
Definition at line 181 of file papiStdEventDefs.h.
◆ PAPI_CA_INV
| #define PAPI_CA_INV (PAPI_CA_INV_idx | PAPI_PRESET_MASK) /*Request for cache line Invalidation (SMP) */ |
Definition at line 182 of file papiStdEventDefs.h.
◆ PAPI_CA_ITV
| #define PAPI_CA_ITV (PAPI_CA_ITV_idx | PAPI_PRESET_MASK) /*Request for cache line Intervention (SMP) */ |
Definition at line 183 of file papiStdEventDefs.h.
◆ PAPI_CA_SHR
| #define PAPI_CA_SHR (PAPI_CA_SHR_idx | PAPI_PRESET_MASK) /*Request for shared cache line (SMP) */ |
Definition at line 180 of file papiStdEventDefs.h.
◆ PAPI_CA_SNP
| #define PAPI_CA_SNP (PAPI_CA_SNP_idx | PAPI_PRESET_MASK) /*Snoops */ |
Definition at line 179 of file papiStdEventDefs.h.
◆ PAPI_CSR_FAL
| #define PAPI_CSR_FAL (PAPI_CSR_FAL_idx | PAPI_PRESET_MASK) /*Failed store conditional instructions */ |
Definition at line 201 of file papiStdEventDefs.h.
◆ PAPI_CSR_SUC
| #define PAPI_CSR_SUC (PAPI_CSR_SUC_idx | PAPI_PRESET_MASK) /*Successful store conditional instructions */ |
Definition at line 202 of file papiStdEventDefs.h.
◆ PAPI_CSR_TOT
| #define PAPI_CSR_TOT (PAPI_CSR_TOT_idx | PAPI_PRESET_MASK) /*Total store conditional instructions */ |
Definition at line 203 of file papiStdEventDefs.h.
◆ PAPI_DP_OPS
| #define PAPI_DP_OPS (PAPI_DP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled double precision vector operations */ |
Definition at line 274 of file papiStdEventDefs.h.
◆ PAPI_END
| #define PAPI_END (PAPI_END_idx | PAPI_PRESET_MASK) /*This should always be last! */ |
Definition at line 279 of file papiStdEventDefs.h.
◆ PAPI_FAD_INS
| #define PAPI_FAD_INS (PAPI_FAD_INS_idx | PAPI_PRESET_MASK) /*FA ins */ |
Definition at line 268 of file papiStdEventDefs.h.
◆ PAPI_FDV_INS
| #define PAPI_FDV_INS (PAPI_FDV_INS_idx | PAPI_PRESET_MASK) /*FD ins */ |
Definition at line 269 of file papiStdEventDefs.h.
◆ PAPI_FMA_INS
| #define PAPI_FMA_INS (PAPI_FMA_INS_idx | PAPI_PRESET_MASK) /*FMA instructions completed */ |
Definition at line 218 of file papiStdEventDefs.h.
◆ PAPI_FML_INS
| #define PAPI_FML_INS (PAPI_FML_INS_idx | PAPI_PRESET_MASK) /*FM ins */ |
Definition at line 267 of file papiStdEventDefs.h.
◆ PAPI_FNV_INS
| #define PAPI_FNV_INS (PAPI_FNV_INS_idx | PAPI_PRESET_MASK) /*Finv ins */ |
Definition at line 271 of file papiStdEventDefs.h.
◆ PAPI_FP_INS
| #define PAPI_FP_INS (PAPI_FP_INS_idx | PAPI_PRESET_MASK) /*Floating point instructions executed */ |
Definition at line 222 of file papiStdEventDefs.h.
◆ PAPI_FP_OPS
| #define PAPI_FP_OPS (PAPI_FP_OPS_idx | PAPI_PRESET_MASK) /*Floating point operations executed */ |
Definition at line 272 of file papiStdEventDefs.h.
◆ PAPI_FP_STAL
| #define PAPI_FP_STAL (PAPI_FP_STAL_idx | PAPI_PRESET_MASK) /*Cycles any FP units are stalled */ |
Definition at line 228 of file papiStdEventDefs.h.
◆ PAPI_FPU_IDL
| #define PAPI_FPU_IDL (PAPI_FPU_IDL_idx | PAPI_PRESET_MASK) /*Cycles floating point units are idle */ |
Definition at line 188 of file papiStdEventDefs.h.
◆ PAPI_FSQ_INS
| #define PAPI_FSQ_INS (PAPI_FSQ_INS_idx | PAPI_PRESET_MASK) /*FSq ins */ |
Definition at line 270 of file papiStdEventDefs.h.
◆ PAPI_FUL_CCY
| #define PAPI_FUL_CCY (PAPI_FUL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Completion */ |
Definition at line 210 of file papiStdEventDefs.h.
◆ PAPI_FUL_ICY
| #define PAPI_FUL_ICY (PAPI_FUL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Issue */ |
Definition at line 208 of file papiStdEventDefs.h.
◆ PAPI_FXU_IDL
| #define PAPI_FXU_IDL (PAPI_FXU_IDL_idx | PAPI_PRESET_MASK) /*Cycles integer units are idle */ |
Definition at line 187 of file papiStdEventDefs.h.
◆ PAPI_HW_INT
| #define PAPI_HW_INT (PAPI_HW_INT_idx | PAPI_PRESET_MASK) /*Hardware interrupts */ |
Definition at line 211 of file papiStdEventDefs.h.
◆ PAPI_INT_INS
| #define PAPI_INT_INS (PAPI_INT_INS_idx | PAPI_PRESET_MASK) /*Integer instructions executed */ |
Definition at line 221 of file papiStdEventDefs.h.
◆ PAPI_L1_DCA
| #define PAPI_L1_DCA (PAPI_L1_DCA_idx | PAPI_PRESET_MASK) /*L1 D Cache Access */ |
Definition at line 234 of file papiStdEventDefs.h.
◆ PAPI_L1_DCH
| #define PAPI_L1_DCH (PAPI_L1_DCH_idx | PAPI_PRESET_MASK) /*L1 D Cache Hit */ |
Definition at line 232 of file papiStdEventDefs.h.
◆ PAPI_L1_DCM
| #define PAPI_L1_DCM (PAPI_L1_DCM_idx | PAPI_PRESET_MASK) /*Level 1 data cache misses */ |
Definition at line 170 of file papiStdEventDefs.h.
◆ PAPI_L1_DCR
| #define PAPI_L1_DCR (PAPI_L1_DCR_idx | PAPI_PRESET_MASK) /*L1 D Cache Read */ |
Definition at line 237 of file papiStdEventDefs.h.
◆ PAPI_L1_DCW
| #define PAPI_L1_DCW (PAPI_L1_DCW_idx | PAPI_PRESET_MASK) /*L1 D Cache Write */ |
Definition at line 240 of file papiStdEventDefs.h.
◆ PAPI_L1_ICA
| #define PAPI_L1_ICA (PAPI_L1_ICA_idx | PAPI_PRESET_MASK) /*L1 instruction cache accesses */ |
Definition at line 246 of file papiStdEventDefs.h.
◆ PAPI_L1_ICH
| #define PAPI_L1_ICH (PAPI_L1_ICH_idx | PAPI_PRESET_MASK) /*L1 instruction cache hits */ |
Definition at line 243 of file papiStdEventDefs.h.
◆ PAPI_L1_ICM
| #define PAPI_L1_ICM (PAPI_L1_ICM_idx | PAPI_PRESET_MASK) /*Level 1 instruction cache misses */ |
Definition at line 171 of file papiStdEventDefs.h.
◆ PAPI_L1_ICR
| #define PAPI_L1_ICR (PAPI_L1_ICR_idx | PAPI_PRESET_MASK) /*L1 instruction cache reads */ |
Definition at line 249 of file papiStdEventDefs.h.
◆ PAPI_L1_ICW
| #define PAPI_L1_ICW (PAPI_L1_ICW_idx | PAPI_PRESET_MASK) /*L1 instruction cache writes */ |
Definition at line 252 of file papiStdEventDefs.h.
◆ PAPI_L1_LDM
| #define PAPI_L1_LDM (PAPI_L1_LDM_idx | PAPI_PRESET_MASK) /*Level 1 load misses */ |
Definition at line 193 of file papiStdEventDefs.h.
◆ PAPI_L1_STM
| #define PAPI_L1_STM (PAPI_L1_STM_idx | PAPI_PRESET_MASK) /*Level 1 store misses */ |
Definition at line 194 of file papiStdEventDefs.h.
◆ PAPI_L1_TCA
| #define PAPI_L1_TCA (PAPI_L1_TCA_idx | PAPI_PRESET_MASK) /*L1 total cache accesses */ |
Definition at line 258 of file papiStdEventDefs.h.
◆ PAPI_L1_TCH
| #define PAPI_L1_TCH (PAPI_L1_TCH_idx | PAPI_PRESET_MASK) /*L1 total cache hits */ |
Definition at line 255 of file papiStdEventDefs.h.
◆ PAPI_L1_TCM
| #define PAPI_L1_TCM (PAPI_L1_TCM_idx | PAPI_PRESET_MASK) /*Level 1 total cache misses */ |
Definition at line 176 of file papiStdEventDefs.h.
◆ PAPI_L1_TCR
| #define PAPI_L1_TCR (PAPI_L1_TCR_idx | PAPI_PRESET_MASK) /*L1 total cache reads */ |
Definition at line 261 of file papiStdEventDefs.h.
◆ PAPI_L1_TCW
| #define PAPI_L1_TCW (PAPI_L1_TCW_idx | PAPI_PRESET_MASK) /*L1 total cache writes */ |
Definition at line 264 of file papiStdEventDefs.h.
◆ PAPI_L2_DCA
| #define PAPI_L2_DCA (PAPI_L2_DCA_idx | PAPI_PRESET_MASK) /*L2 D Cache Access */ |
Definition at line 235 of file papiStdEventDefs.h.
◆ PAPI_L2_DCH
| #define PAPI_L2_DCH (PAPI_L2_DCH_idx | PAPI_PRESET_MASK) /*L2 D Cache Hit */ |
Definition at line 233 of file papiStdEventDefs.h.
◆ PAPI_L2_DCM
| #define PAPI_L2_DCM (PAPI_L2_DCM_idx | PAPI_PRESET_MASK) /*Level 2 data cache misses */ |
Definition at line 172 of file papiStdEventDefs.h.
◆ PAPI_L2_DCR
| #define PAPI_L2_DCR (PAPI_L2_DCR_idx | PAPI_PRESET_MASK) /*L2 D Cache Read */ |
Definition at line 238 of file papiStdEventDefs.h.
◆ PAPI_L2_DCW
| #define PAPI_L2_DCW (PAPI_L2_DCW_idx | PAPI_PRESET_MASK) /*L2 D Cache Write */ |
Definition at line 241 of file papiStdEventDefs.h.
◆ PAPI_L2_ICA
| #define PAPI_L2_ICA (PAPI_L2_ICA_idx | PAPI_PRESET_MASK) /*L2 instruction cache accesses */ |
Definition at line 247 of file papiStdEventDefs.h.
◆ PAPI_L2_ICH
| #define PAPI_L2_ICH (PAPI_L2_ICH_idx | PAPI_PRESET_MASK) /*L2 instruction cache hits */ |
Definition at line 244 of file papiStdEventDefs.h.
◆ PAPI_L2_ICM
| #define PAPI_L2_ICM (PAPI_L2_ICM_idx | PAPI_PRESET_MASK) /*Level 2 instruction cache misses */ |
Definition at line 173 of file papiStdEventDefs.h.
◆ PAPI_L2_ICR
| #define PAPI_L2_ICR (PAPI_L2_ICR_idx | PAPI_PRESET_MASK) /*L2 instruction cache reads */ |
Definition at line 250 of file papiStdEventDefs.h.
◆ PAPI_L2_ICW
| #define PAPI_L2_ICW (PAPI_L2_ICW_idx | PAPI_PRESET_MASK) /*L2 instruction cache writes */ |
Definition at line 253 of file papiStdEventDefs.h.
◆ PAPI_L2_LDM
| #define PAPI_L2_LDM (PAPI_L2_LDM_idx | PAPI_PRESET_MASK) /*Level 2 load misses */ |
Definition at line 195 of file papiStdEventDefs.h.
◆ PAPI_L2_STM
| #define PAPI_L2_STM (PAPI_L2_STM_idx | PAPI_PRESET_MASK) /*Level 2 store misses */ |
Definition at line 196 of file papiStdEventDefs.h.
◆ PAPI_L2_TCA
| #define PAPI_L2_TCA (PAPI_L2_TCA_idx | PAPI_PRESET_MASK) /*L2 total cache accesses */ |
Definition at line 259 of file papiStdEventDefs.h.
◆ PAPI_L2_TCH
| #define PAPI_L2_TCH (PAPI_L2_TCH_idx | PAPI_PRESET_MASK) /*L2 total cache hits */ |
Definition at line 256 of file papiStdEventDefs.h.
◆ PAPI_L2_TCM
| #define PAPI_L2_TCM (PAPI_L2_TCM_idx | PAPI_PRESET_MASK) /*Level 2 total cache misses */ |
Definition at line 177 of file papiStdEventDefs.h.
◆ PAPI_L2_TCR
| #define PAPI_L2_TCR (PAPI_L2_TCR_idx | PAPI_PRESET_MASK) /*L2 total cache reads */ |
Definition at line 262 of file papiStdEventDefs.h.
◆ PAPI_L2_TCW
| #define PAPI_L2_TCW (PAPI_L2_TCW_idx | PAPI_PRESET_MASK) /*L2 total cache writes */ |
Definition at line 265 of file papiStdEventDefs.h.
◆ PAPI_L3_DCA
| #define PAPI_L3_DCA (PAPI_L3_DCA_idx | PAPI_PRESET_MASK) /*L3 D Cache Access */ |
Definition at line 236 of file papiStdEventDefs.h.
◆ PAPI_L3_DCH
| #define PAPI_L3_DCH (PAPI_L3_DCH_idx | PAPI_PRESET_MASK) /*Level 3 Data Cache Hit */ |
Definition at line 199 of file papiStdEventDefs.h.
◆ PAPI_L3_DCM
| #define PAPI_L3_DCM (PAPI_L3_DCM_idx | PAPI_PRESET_MASK) /*Level 3 data cache misses */ |
Definition at line 174 of file papiStdEventDefs.h.
◆ PAPI_L3_DCR
| #define PAPI_L3_DCR (PAPI_L3_DCR_idx | PAPI_PRESET_MASK) /*L3 D Cache Read */ |
Definition at line 239 of file papiStdEventDefs.h.
◆ PAPI_L3_DCW
| #define PAPI_L3_DCW (PAPI_L3_DCW_idx | PAPI_PRESET_MASK) /*L3 D Cache Write */ |
Definition at line 242 of file papiStdEventDefs.h.
◆ PAPI_L3_ICA
| #define PAPI_L3_ICA (PAPI_L3_ICA_idx | PAPI_PRESET_MASK) /*L3 instruction cache accesses */ |
Definition at line 248 of file papiStdEventDefs.h.
◆ PAPI_L3_ICH
| #define PAPI_L3_ICH (PAPI_L3_ICH_idx | PAPI_PRESET_MASK) /*L3 instruction cache hits */ |
Definition at line 245 of file papiStdEventDefs.h.
◆ PAPI_L3_ICM
| #define PAPI_L3_ICM (PAPI_L3_ICM_idx | PAPI_PRESET_MASK) /*Level 3 instruction cache misses */ |
Definition at line 175 of file papiStdEventDefs.h.
◆ PAPI_L3_ICR
| #define PAPI_L3_ICR (PAPI_L3_ICR_idx | PAPI_PRESET_MASK) /*L3 instruction cache reads */ |
Definition at line 251 of file papiStdEventDefs.h.
◆ PAPI_L3_ICW
| #define PAPI_L3_ICW (PAPI_L3_ICW_idx | PAPI_PRESET_MASK) /*L3 instruction cache writes */ |
Definition at line 254 of file papiStdEventDefs.h.
◆ PAPI_L3_LDM
| #define PAPI_L3_LDM (PAPI_L3_LDM_idx | PAPI_PRESET_MASK) /*Level 3 load misses */ |
Definition at line 184 of file papiStdEventDefs.h.
◆ PAPI_L3_STM
| #define PAPI_L3_STM (PAPI_L3_STM_idx | PAPI_PRESET_MASK) /*Level 3 store misses */ |
Definition at line 185 of file papiStdEventDefs.h.
◆ PAPI_L3_TCA
| #define PAPI_L3_TCA (PAPI_L3_TCA_idx | PAPI_PRESET_MASK) /*L3 total cache accesses */ |
Definition at line 260 of file papiStdEventDefs.h.
◆ PAPI_L3_TCH
| #define PAPI_L3_TCH (PAPI_L3_TCH_idx | PAPI_PRESET_MASK) /*L3 total cache hits */ |
Definition at line 257 of file papiStdEventDefs.h.
◆ PAPI_L3_TCM
| #define PAPI_L3_TCM (PAPI_L3_TCM_idx | PAPI_PRESET_MASK) /*Level 3 total cache misses */ |
Definition at line 178 of file papiStdEventDefs.h.
◆ PAPI_L3_TCR
| #define PAPI_L3_TCR (PAPI_L3_TCR_idx | PAPI_PRESET_MASK) /*L3 total cache reads */ |
Definition at line 263 of file papiStdEventDefs.h.
◆ PAPI_L3_TCW
| #define PAPI_L3_TCW (PAPI_L3_TCW_idx | PAPI_PRESET_MASK) /*L3 total cache writes */ |
Definition at line 266 of file papiStdEventDefs.h.
◆ PAPI_LD_INS
| #define PAPI_LD_INS (PAPI_LD_INS_idx | PAPI_PRESET_MASK) /*Load instructions executed */ |
Definition at line 223 of file papiStdEventDefs.h.
◆ PAPI_LST_INS
| #define PAPI_LST_INS (PAPI_LST_INS_idx | PAPI_PRESET_MASK) /*Total load/store inst. executed */ |
Definition at line 230 of file papiStdEventDefs.h.
◆ PAPI_LSU_IDL
| #define PAPI_LSU_IDL (PAPI_LSU_IDL_idx | PAPI_PRESET_MASK) /*Cycles load/store units are idle */ |
Definition at line 189 of file papiStdEventDefs.h.
◆ PAPI_MAX_PRESET_EVENTS
Definition at line 36 of file papiStdEventDefs.h.
◆ PAPI_MAX_USER_EVENTS
| #define PAPI_MAX_USER_EVENTS 50 /*The maxmimum number of user defined events */ |
Definition at line 37 of file papiStdEventDefs.h.
◆ PAPI_MEM_RCY
| #define PAPI_MEM_RCY (PAPI_MEM_RCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Read */ |
Definition at line 205 of file papiStdEventDefs.h.
◆ PAPI_MEM_SCY
| #define PAPI_MEM_SCY (PAPI_MEM_SCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Access */ |
Definition at line 204 of file papiStdEventDefs.h.
◆ PAPI_MEM_WCY
| #define PAPI_MEM_WCY (PAPI_MEM_WCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Write */ |
Definition at line 206 of file papiStdEventDefs.h.
◆ PAPI_NATIVE_AND_MASK
| #define PAPI_NATIVE_AND_MASK 0xBFFFFFFF /* this masks just the native bit */ |
Definition at line 33 of file papiStdEventDefs.h.
◆ PAPI_NATIVE_MASK
| #define PAPI_NATIVE_MASK ((int)0x40000000) |
Definition at line 30 of file papiStdEventDefs.h.
◆ PAPI_PRESET_AND_MASK
| #define PAPI_PRESET_AND_MASK 0x7FFFFFFF |
Definition at line 32 of file papiStdEventDefs.h.
◆ PAPI_PRESET_MASK
| #define PAPI_PRESET_MASK ((int)0x80000000) |
Definition at line 29 of file papiStdEventDefs.h.
◆ PAPI_PRF_DM
| #define PAPI_PRF_DM (PAPI_PRF_DM_idx | PAPI_PRESET_MASK) /*Prefetch data instruction caused a miss */ |
Definition at line 198 of file papiStdEventDefs.h.
◆ PAPI_REF_CYC
| #define PAPI_REF_CYC (PAPI_REF_CYC_idx | PAPI_PRESET_MASK) /* Reference clock cycles */ |
Definition at line 277 of file papiStdEventDefs.h.
◆ PAPI_RES_STL
| #define PAPI_RES_STL (PAPI_RES_STL_idx | PAPI_PRESET_MASK) /*Cycles processor is stalled on resource */ |
Definition at line 227 of file papiStdEventDefs.h.
◆ PAPI_SP_OPS
| #define PAPI_SP_OPS (PAPI_SP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled single precision vector operations */ |
Definition at line 273 of file papiStdEventDefs.h.
◆ PAPI_SR_INS
| #define PAPI_SR_INS (PAPI_SR_INS_idx | PAPI_PRESET_MASK) /*Store instructions executed */ |
Definition at line 224 of file papiStdEventDefs.h.
◆ PAPI_STL_CCY
| #define PAPI_STL_CCY (PAPI_STL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Completion */ |
Definition at line 209 of file papiStdEventDefs.h.
◆ PAPI_STL_ICY
| #define PAPI_STL_ICY (PAPI_STL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Issue */ |
Definition at line 207 of file papiStdEventDefs.h.
◆ PAPI_SYC_INS
| #define PAPI_SYC_INS (PAPI_SYC_INS_idx | PAPI_PRESET_MASK) /*Sync. inst. executed */ |
Definition at line 231 of file papiStdEventDefs.h.
◆ PAPI_TLB_DM
| #define PAPI_TLB_DM (PAPI_TLB_DM_idx | PAPI_PRESET_MASK) /*Data translation lookaside buffer misses */ |
Definition at line 190 of file papiStdEventDefs.h.
◆ PAPI_TLB_IM
| #define PAPI_TLB_IM (PAPI_TLB_IM_idx | PAPI_PRESET_MASK) /*Instr translation lookaside buffer misses */ |
Definition at line 191 of file papiStdEventDefs.h.
◆ PAPI_TLB_SD
| #define PAPI_TLB_SD (PAPI_TLB_SD_idx | PAPI_PRESET_MASK) /*Xlation lookaside buffer shootdowns (SMP) */ |
Definition at line 200 of file papiStdEventDefs.h.
◆ PAPI_TLB_TL
| #define PAPI_TLB_TL (PAPI_TLB_TL_idx | PAPI_PRESET_MASK) /*Total translation lookaside buffer misses */ |
Definition at line 192 of file papiStdEventDefs.h.
◆ PAPI_TOT_CYC
| #define PAPI_TOT_CYC (PAPI_TOT_CYC_idx | PAPI_PRESET_MASK) /*Total cycles executed */ |
Definition at line 229 of file papiStdEventDefs.h.
◆ PAPI_TOT_IIS
| #define PAPI_TOT_IIS (PAPI_TOT_IIS_idx | PAPI_PRESET_MASK) /*Total instructions issued */ |
Definition at line 219 of file papiStdEventDefs.h.
◆ PAPI_TOT_INS
| #define PAPI_TOT_INS (PAPI_TOT_INS_idx | PAPI_PRESET_MASK) /*Total instructions executed */ |
Definition at line 220 of file papiStdEventDefs.h.
◆ PAPI_UE_AND_MASK
| #define PAPI_UE_AND_MASK 0x3FFFFFFF |
Definition at line 34 of file papiStdEventDefs.h.
◆ PAPI_UE_MASK
| #define PAPI_UE_MASK ((int)0xC0000000) |
Definition at line 31 of file papiStdEventDefs.h.
◆ PAPI_VEC_DP
| #define PAPI_VEC_DP (PAPI_VEC_DP_idx | PAPI_PRESET_MASK) /* Double precision vector/SIMD instructions */ |
Definition at line 276 of file papiStdEventDefs.h.
◆ PAPI_VEC_INS
| #define PAPI_VEC_INS (PAPI_VEC_INS_idx | PAPI_PRESET_MASK) /*Vector/SIMD instructions executed (could include integer) */ |
Definition at line 226 of file papiStdEventDefs.h.
◆ PAPI_VEC_SP
| #define PAPI_VEC_SP (PAPI_VEC_SP_idx | PAPI_PRESET_MASK) /* Single precision vector/SIMD instructions */ |
Definition at line 275 of file papiStdEventDefs.h.
◆ USER_EVENT_OPERATION_LEN
| #define USER_EVENT_OPERATION_LEN 512 /*The maximum length of the operation string for user defined events */ |
Definition at line 38 of file papiStdEventDefs.h.
Enumeration Type Documentation
◆ anonymous enum
| anonymous enum |
Definition at line 51 of file papiStdEventDefs.h.
