PAPI 7.1.0.0
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itanium_events.h
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1/*
2 * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P.
3 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
16 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
17 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
18 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
19 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * This file is part of libpfm, a performance monitoring support library for
23 * applications on Linux/ia64.
24 */
25
26/*
27 * This file is generated automatically
28 * !! DO NOT CHANGE !!
29 */
30
31/*
32 * Events table for the Itanium PMU family
33 */
34static pme_ita_entry_t itanium_pe []={
35#define PME_ITA_ALAT_INST_CHKA_LDC_ALL 0
36{ "ALAT_INST_CHKA_LDC_ALL", {0x30036} , 0xf0, 2, {0xffff0003}, NULL},
37#define PME_ITA_ALAT_INST_CHKA_LDC_FP 1
38{ "ALAT_INST_CHKA_LDC_FP", {0x10036} , 0xf0, 2, {0xffff0003}, NULL},
39#define PME_ITA_ALAT_INST_CHKA_LDC_INT 2
40{ "ALAT_INST_CHKA_LDC_INT", {0x20036} , 0xf0, 2, {0xffff0003}, NULL},
41#define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_ALL 3
42{ "ALAT_INST_FAILED_CHKA_LDC_ALL", {0x30037} , 0xf0, 2, {0xffff0003}, NULL},
43#define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_FP 4
44{ "ALAT_INST_FAILED_CHKA_LDC_FP", {0x10037} , 0xf0, 2, {0xffff0003}, NULL},
45#define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_INT 5
46{ "ALAT_INST_FAILED_CHKA_LDC_INT", {0x20037} , 0xf0, 2, {0xffff0003}, NULL},
47#define PME_ITA_ALAT_REPLACEMENT_ALL 6
48{ "ALAT_REPLACEMENT_ALL", {0x30038} , 0xf0, 2, {0xffff0007}, NULL},
49#define PME_ITA_ALAT_REPLACEMENT_FP 7
50{ "ALAT_REPLACEMENT_FP", {0x10038} , 0xf0, 2, {0xffff0007}, NULL},
51#define PME_ITA_ALAT_REPLACEMENT_INT 8
52{ "ALAT_REPLACEMENT_INT", {0x20038} , 0xf0, 2, {0xffff0007}, NULL},
53#define PME_ITA_ALL_STOPS_DISPERSED 9
54{ "ALL_STOPS_DISPERSED", {0x2f} , 0xf0, 1, {0xffff0001}, NULL},
55#define PME_ITA_BRANCH_EVENT 10
56{ "BRANCH_EVENT", {0x811} , 0xf0, 1, {0xffff0003}, NULL},
57#define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_ALL_PREDICTIONS 11
58{ "BRANCH_MULTIWAY_ALL_PATHS_ALL_PREDICTIONS", {0xe} , 0xf0, 1, {0xffff0003}, NULL},
59#define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_CORRECT_PREDICTIONS 12
60{ "BRANCH_MULTIWAY_ALL_PATHS_CORRECT_PREDICTIONS", {0x1000e} , 0xf0, 1, {0xffff0003}, NULL},
61#define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_WRONG_PATH 13
62{ "BRANCH_MULTIWAY_ALL_PATHS_WRONG_PATH", {0x2000e} , 0xf0, 1, {0xffff0003}, NULL},
63#define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_WRONG_TARGET 14
64{ "BRANCH_MULTIWAY_ALL_PATHS_WRONG_TARGET", {0x3000e} , 0xf0, 1, {0xffff0003}, NULL},
65#define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_ALL_PREDICTIONS 15
66{ "BRANCH_MULTIWAY_NOT_TAKEN_ALL_PREDICTIONS", {0x8000e} , 0xf0, 1, {0xffff0003}, NULL},
67#define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_CORRECT_PREDICTIONS 16
68{ "BRANCH_MULTIWAY_NOT_TAKEN_CORRECT_PREDICTIONS", {0x9000e} , 0xf0, 1, {0xffff0003}, NULL},
69#define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_WRONG_PATH 17
70{ "BRANCH_MULTIWAY_NOT_TAKEN_WRONG_PATH", {0xa000e} , 0xf0, 1, {0xffff0003}, NULL},
71#define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_WRONG_TARGET 18
72{ "BRANCH_MULTIWAY_NOT_TAKEN_WRONG_TARGET", {0xb000e} , 0xf0, 1, {0xffff0003}, NULL},
73#define PME_ITA_BRANCH_MULTIWAY_TAKEN_ALL_PREDICTIONS 19
74{ "BRANCH_MULTIWAY_TAKEN_ALL_PREDICTIONS", {0xc000e} , 0xf0, 1, {0xffff0003}, NULL},
75#define PME_ITA_BRANCH_MULTIWAY_TAKEN_CORRECT_PREDICTIONS 20
76{ "BRANCH_MULTIWAY_TAKEN_CORRECT_PREDICTIONS", {0xd000e} , 0xf0, 1, {0xffff0003}, NULL},
77#define PME_ITA_BRANCH_MULTIWAY_TAKEN_WRONG_PATH 21
78{ "BRANCH_MULTIWAY_TAKEN_WRONG_PATH", {0xe000e} , 0xf0, 1, {0xffff0003}, NULL},
79#define PME_ITA_BRANCH_MULTIWAY_TAKEN_WRONG_TARGET 22
80{ "BRANCH_MULTIWAY_TAKEN_WRONG_TARGET", {0xf000e} , 0xf0, 1, {0xffff0003}, NULL},
81#define PME_ITA_BRANCH_NOT_TAKEN 23
82{ "BRANCH_NOT_TAKEN", {0x8000d} , 0xf0, 1, {0xffff0003}, NULL},
83#define PME_ITA_BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 24
84{ "BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0x6000f} , 0xf0, 1, {0xffff0003}, NULL},
85#define PME_ITA_BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 25
86{ "BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0x4000f} , 0xf0, 1, {0xffff0003}, NULL},
87#define PME_ITA_BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 26
88{ "BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0x7000f} , 0xf0, 1, {0xffff0003}, NULL},
89#define PME_ITA_BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 27
90{ "BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x5000f} , 0xf0, 1, {0xffff0003}, NULL},
91#define PME_ITA_BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 28
92{ "BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0xa000f} , 0xf0, 1, {0xffff0003}, NULL},
93#define PME_ITA_BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 29
94{ "BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0x8000f} , 0xf0, 1, {0xffff0003}, NULL},
95#define PME_ITA_BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 30
96{ "BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0xb000f} , 0xf0, 1, {0xffff0003}, NULL},
97#define PME_ITA_BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 31
98{ "BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x9000f} , 0xf0, 1, {0xffff0003}, NULL},
99#define PME_ITA_BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 32
100{ "BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0xe000f} , 0xf0, 1, {0xffff0003}, NULL},
101#define PME_ITA_BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 33
102{ "BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0xc000f} , 0xf0, 1, {0xffff0003}, NULL},
103#define PME_ITA_BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 34
104{ "BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0xf000f} , 0xf0, 1, {0xffff0003}, NULL},
105#define PME_ITA_BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 35
106{ "BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0xd000f} , 0xf0, 1, {0xffff0003}, NULL},
107#define PME_ITA_BRANCH_PATH_ALL_NT_OUTCOMES_CORRECTLY_PREDICTED 36
108{ "BRANCH_PATH_ALL_NT_OUTCOMES_CORRECTLY_PREDICTED", {0x2000f} , 0xf0, 1, {0xffff0003}, NULL},
109#define PME_ITA_BRANCH_PATH_ALL_NT_OUTCOMES_INCORRECTLY_PREDICTED 37
110{ "BRANCH_PATH_ALL_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0xf} , 0xf0, 1, {0xffff0003}, NULL},
111#define PME_ITA_BRANCH_PATH_ALL_TK_OUTCOMES_CORRECTLY_PREDICTED 38
112{ "BRANCH_PATH_ALL_TK_OUTCOMES_CORRECTLY_PREDICTED", {0x3000f} , 0xf0, 1, {0xffff0003}, NULL},
113#define PME_ITA_BRANCH_PATH_ALL_TK_OUTCOMES_INCORRECTLY_PREDICTED 39
114{ "BRANCH_PATH_ALL_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x1000f} , 0xf0, 1, {0xffff0003}, NULL},
115#define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_ALL_PREDICTIONS 40
116{ "BRANCH_PREDICTOR_1ST_STAGE_ALL_PREDICTIONS", {0x40010} , 0xf0, 1, {0xffff0003}, NULL},
117#define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_CORRECT_PREDICTIONS 41
118{ "BRANCH_PREDICTOR_1ST_STAGE_CORRECT_PREDICTIONS", {0x50010} , 0xf0, 1, {0xffff0003}, NULL},
119#define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_WRONG_PATH 42
120{ "BRANCH_PREDICTOR_1ST_STAGE_WRONG_PATH", {0x60010} , 0xf0, 1, {0xffff0003}, NULL},
121#define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_WRONG_TARGET 43
122{ "BRANCH_PREDICTOR_1ST_STAGE_WRONG_TARGET", {0x70010} , 0xf0, 1, {0xffff0003}, NULL},
123#define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_ALL_PREDICTIONS 44
124{ "BRANCH_PREDICTOR_2ND_STAGE_ALL_PREDICTIONS", {0x80010} , 0xf0, 1, {0xffff0003}, NULL},
125#define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_CORRECT_PREDICTIONS 45
126{ "BRANCH_PREDICTOR_2ND_STAGE_CORRECT_PREDICTIONS", {0x90010} , 0xf0, 1, {0xffff0003}, NULL},
127#define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_WRONG_PATH 46
128{ "BRANCH_PREDICTOR_2ND_STAGE_WRONG_PATH", {0xa0010} , 0xf0, 1, {0xffff0003}, NULL},
129#define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_WRONG_TARGET 47
130{ "BRANCH_PREDICTOR_2ND_STAGE_WRONG_TARGET", {0xb0010} , 0xf0, 1, {0xffff0003}, NULL},
131#define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_ALL_PREDICTIONS 48
132{ "BRANCH_PREDICTOR_3RD_STAGE_ALL_PREDICTIONS", {0xc0010} , 0xf0, 1, {0xffff0003}, NULL},
133#define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_CORRECT_PREDICTIONS 49
134{ "BRANCH_PREDICTOR_3RD_STAGE_CORRECT_PREDICTIONS", {0xd0010} , 0xf0, 1, {0xffff0003}, NULL},
135#define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_WRONG_PATH 50
136{ "BRANCH_PREDICTOR_3RD_STAGE_WRONG_PATH", {0xe0010} , 0xf0, 1, {0xffff0003}, NULL},
137#define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_WRONG_TARGET 51
138{ "BRANCH_PREDICTOR_3RD_STAGE_WRONG_TARGET", {0xf0010} , 0xf0, 1, {0xffff0003}, NULL},
139#define PME_ITA_BRANCH_PREDICTOR_ALL_ALL_PREDICTIONS 52
140{ "BRANCH_PREDICTOR_ALL_ALL_PREDICTIONS", {0x10} , 0xf0, 1, {0xffff0003}, NULL},
141#define PME_ITA_BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS 53
142{ "BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS", {0x10010} , 0xf0, 1, {0xffff0003}, NULL},
143#define PME_ITA_BRANCH_PREDICTOR_ALL_WRONG_PATH 54
144{ "BRANCH_PREDICTOR_ALL_WRONG_PATH", {0x20010} , 0xf0, 1, {0xffff0003}, NULL},
145#define PME_ITA_BRANCH_PREDICTOR_ALL_WRONG_TARGET 55
146{ "BRANCH_PREDICTOR_ALL_WRONG_TARGET", {0x30010} , 0xf0, 1, {0xffff0003}, NULL},
147#define PME_ITA_BRANCH_TAKEN_SLOT_0 56
148{ "BRANCH_TAKEN_SLOT_0", {0x1000d} , 0xf0, 1, {0xffff0003}, NULL},
149#define PME_ITA_BRANCH_TAKEN_SLOT_1 57
150{ "BRANCH_TAKEN_SLOT_1", {0x2000d} , 0xf0, 1, {0xffff0003}, NULL},
151#define PME_ITA_BRANCH_TAKEN_SLOT_2 58
152{ "BRANCH_TAKEN_SLOT_2", {0x4000d} , 0xf0, 1, {0xffff0003}, NULL},
153#define PME_ITA_BUS_ALL_ANY 59
154{ "BUS_ALL_ANY", {0x10047} , 0xf0, 1, {0xffff0000}, NULL},
155#define PME_ITA_BUS_ALL_IO 60
156{ "BUS_ALL_IO", {0x40047} , 0xf0, 1, {0xffff0000}, NULL},
157#define PME_ITA_BUS_ALL_SELF 61
158{ "BUS_ALL_SELF", {0x20047} , 0xf0, 1, {0xffff0000}, NULL},
159#define PME_ITA_BUS_BRQ_LIVE_REQ_HI 62
160{ "BUS_BRQ_LIVE_REQ_HI", {0x5c} , 0xf0, 2, {0xffff0000}, NULL},
161#define PME_ITA_BUS_BRQ_LIVE_REQ_LO 63
162{ "BUS_BRQ_LIVE_REQ_LO", {0x5b} , 0xf0, 2, {0xffff0000}, NULL},
163#define PME_ITA_BUS_BRQ_REQ_INSERTED 64
164{ "BUS_BRQ_REQ_INSERTED", {0x5d} , 0xf0, 1, {0xffff0000}, NULL},
165#define PME_ITA_BUS_BURST_ANY 65
166{ "BUS_BURST_ANY", {0x10049} , 0xf0, 1, {0xffff0000}, NULL},
167#define PME_ITA_BUS_BURST_IO 66
168{ "BUS_BURST_IO", {0x40049} , 0xf0, 1, {0xffff0000}, NULL},
169#define PME_ITA_BUS_BURST_SELF 67
170{ "BUS_BURST_SELF", {0x20049} , 0xf0, 1, {0xffff0000}, NULL},
171#define PME_ITA_BUS_HITM 68
172{ "BUS_HITM", {0x44} , 0xf0, 1, {0xffff0000}, NULL},
173#define PME_ITA_BUS_IO_ANY 69
174{ "BUS_IO_ANY", {0x10050} , 0xf0, 1, {0xffff0000}, NULL},
175#define PME_ITA_BUS_IOQ_LIVE_REQ_HI 70
176{ "BUS_IOQ_LIVE_REQ_HI", {0x58} , 0xf0, 3, {0xffff0000}, NULL},
177#define PME_ITA_BUS_IOQ_LIVE_REQ_LO 71
178{ "BUS_IOQ_LIVE_REQ_LO", {0x57} , 0xf0, 3, {0xffff0000}, NULL},
179#define PME_ITA_BUS_IO_SELF 72
180{ "BUS_IO_SELF", {0x20050} , 0xf0, 1, {0xffff0000}, NULL},
181#define PME_ITA_BUS_LOCK_ANY 73
182{ "BUS_LOCK_ANY", {0x10053} , 0xf0, 1, {0xffff0000}, NULL},
183#define PME_ITA_BUS_LOCK_CYCLES_ANY 74
184{ "BUS_LOCK_CYCLES_ANY", {0x10054} , 0xf0, 1, {0xffff0000}, NULL},
185#define PME_ITA_BUS_LOCK_CYCLES_SELF 75
186{ "BUS_LOCK_CYCLES_SELF", {0x20054} , 0xf0, 1, {0xffff0000}, NULL},
187#define PME_ITA_BUS_LOCK_SELF 76
188{ "BUS_LOCK_SELF", {0x20053} , 0xf0, 1, {0xffff0000}, NULL},
189#define PME_ITA_BUS_MEMORY_ANY 77
190{ "BUS_MEMORY_ANY", {0x1004a} , 0xf0, 1, {0xffff0000}, NULL},
191#define PME_ITA_BUS_MEMORY_IO 78
192{ "BUS_MEMORY_IO", {0x4004a} , 0xf0, 1, {0xffff0000}, NULL},
193#define PME_ITA_BUS_MEMORY_SELF 79
194{ "BUS_MEMORY_SELF", {0x2004a} , 0xf0, 1, {0xffff0000}, NULL},
195#define PME_ITA_BUS_PARTIAL_ANY 80
196{ "BUS_PARTIAL_ANY", {0x10048} , 0xf0, 1, {0xffff0000}, NULL},
197#define PME_ITA_BUS_PARTIAL_IO 81
198{ "BUS_PARTIAL_IO", {0x40048} , 0xf0, 1, {0xffff0000}, NULL},
199#define PME_ITA_BUS_PARTIAL_SELF 82
200{ "BUS_PARTIAL_SELF", {0x20048} , 0xf0, 1, {0xffff0000}, NULL},
201#define PME_ITA_BUS_RD_ALL_ANY 83
202{ "BUS_RD_ALL_ANY", {0x1004b} , 0xf0, 1, {0xffff0000}, NULL},
203#define PME_ITA_BUS_RD_ALL_IO 84
204{ "BUS_RD_ALL_IO", {0x4004b} , 0xf0, 1, {0xffff0000}, NULL},
205#define PME_ITA_BUS_RD_ALL_SELF 85
206{ "BUS_RD_ALL_SELF", {0x2004b} , 0xf0, 1, {0xffff0000}, NULL},
207#define PME_ITA_BUS_RD_DATA_ANY 86
208{ "BUS_RD_DATA_ANY", {0x1004c} , 0xf0, 1, {0xffff0000}, NULL},
209#define PME_ITA_BUS_RD_DATA_IO 87
210{ "BUS_RD_DATA_IO", {0x4004c} , 0xf0, 1, {0xffff0000}, NULL},
211#define PME_ITA_BUS_RD_DATA_SELF 88
212{ "BUS_RD_DATA_SELF", {0x2004c} , 0xf0, 1, {0xffff0000}, NULL},
213#define PME_ITA_BUS_RD_HIT 89
214{ "BUS_RD_HIT", {0x40} , 0xf0, 1, {0xffff0000}, NULL},
215#define PME_ITA_BUS_RD_HITM 90
216{ "BUS_RD_HITM", {0x41} , 0xf0, 1, {0xffff0000}, NULL},
217#define PME_ITA_BUS_RD_INVAL_ANY 91
218{ "BUS_RD_INVAL_ANY", {0x1004e} , 0xf0, 1, {0xffff0000}, NULL},
219#define PME_ITA_BUS_RD_INVAL_BST_ANY 92
220{ "BUS_RD_INVAL_BST_ANY", {0x1004f} , 0xf0, 1, {0xffff0000}, NULL},
221#define PME_ITA_BUS_RD_INVAL_BST_HITM 93
222{ "BUS_RD_INVAL_BST_HITM", {0x43} , 0xf0, 1, {0xffff0000}, NULL},
223#define PME_ITA_BUS_RD_INVAL_BST_IO 94
224{ "BUS_RD_INVAL_BST_IO", {0x4004f} , 0xf0, 1, {0xffff0000}, NULL},
225#define PME_ITA_BUS_RD_INVAL_BST_SELF 95
226{ "BUS_RD_INVAL_BST_SELF", {0x2004f} , 0xf0, 1, {0xffff0000}, NULL},
227#define PME_ITA_BUS_RD_INVAL_HITM 96
228{ "BUS_RD_INVAL_HITM", {0x42} , 0xf0, 1, {0xffff0000}, NULL},
229#define PME_ITA_BUS_RD_INVAL_IO 97
230{ "BUS_RD_INVAL_IO", {0x4004e} , 0xf0, 1, {0xffff0000}, NULL},
231#define PME_ITA_BUS_RD_INVAL_SELF 98
232{ "BUS_RD_INVAL_SELF", {0x2004e} , 0xf0, 1, {0xffff0000}, NULL},
233#define PME_ITA_BUS_RD_IO_ANY 99
234{ "BUS_RD_IO_ANY", {0x10051} , 0xf0, 1, {0xffff0000}, NULL},
235#define PME_ITA_BUS_RD_IO_SELF 100
236{ "BUS_RD_IO_SELF", {0x20051} , 0xf0, 1, {0xffff0000}, NULL},
237#define PME_ITA_BUS_RD_PRTL_ANY 101
238{ "BUS_RD_PRTL_ANY", {0x1004d} , 0xf0, 1, {0xffff0000}, NULL},
239#define PME_ITA_BUS_RD_PRTL_IO 102
240{ "BUS_RD_PRTL_IO", {0x4004d} , 0xf0, 1, {0xffff0000}, NULL},
241#define PME_ITA_BUS_RD_PRTL_SELF 103
242{ "BUS_RD_PRTL_SELF", {0x2004d} , 0xf0, 1, {0xffff0000}, NULL},
243#define PME_ITA_BUS_SNOOPQ_REQ 104
244{ "BUS_SNOOPQ_REQ", {0x56} , 0x30, 3, {0xffff0000}, NULL},
245#define PME_ITA_BUS_SNOOPS_ANY 105
246{ "BUS_SNOOPS_ANY", {0x10046} , 0xf0, 1, {0xffff0000}, NULL},
247#define PME_ITA_BUS_SNOOPS_HITM_ANY 106
248{ "BUS_SNOOPS_HITM_ANY", {0x10045} , 0xf0, 1, {0xffff0000}, NULL},
249#define PME_ITA_BUS_SNOOP_STALL_CYCLES_ANY 107
250{ "BUS_SNOOP_STALL_CYCLES_ANY", {0x10055} , 0xf0, 1, {0xffff0000}, NULL},
251#define PME_ITA_BUS_SNOOP_STALL_CYCLES_SELF 108
252{ "BUS_SNOOP_STALL_CYCLES_SELF", {0x20055} , 0xf0, 1, {0xffff0000}, NULL},
253#define PME_ITA_BUS_WR_WB_ANY 109
254{ "BUS_WR_WB_ANY", {0x10052} , 0xf0, 1, {0xffff0000}, NULL},
255#define PME_ITA_BUS_WR_WB_IO 110
256{ "BUS_WR_WB_IO", {0x40052} , 0xf0, 1, {0xffff0000}, NULL},
257#define PME_ITA_BUS_WR_WB_SELF 111
258{ "BUS_WR_WB_SELF", {0x20052} , 0xf0, 1, {0xffff0000}, NULL},
259#define PME_ITA_CPU_CPL_CHANGES 112
260{ "CPU_CPL_CHANGES", {0x34} , 0xf0, 1, {0xffff0000}, NULL},
261#define PME_ITA_CPU_CYCLES 113
262{ "CPU_CYCLES", {0x12} , 0xf0, 1, {0xffff0000}, NULL},
263#define PME_ITA_DATA_ACCESS_CYCLE 114
264{ "DATA_ACCESS_CYCLE", {0x3} , 0xf0, 1, {0xffff0000}, NULL},
265#define PME_ITA_DATA_EAR_CACHE_LAT1024 115
266{ "DATA_EAR_CACHE_LAT1024", {0x90367} , 0xf0, 1, {0xffff0003}, NULL},
267#define PME_ITA_DATA_EAR_CACHE_LAT128 116
268{ "DATA_EAR_CACHE_LAT128", {0x50367} , 0xf0, 1, {0xffff0003}, NULL},
269#define PME_ITA_DATA_EAR_CACHE_LAT16 117
270{ "DATA_EAR_CACHE_LAT16", {0x20367} , 0xf0, 1, {0xffff0003}, NULL},
271#define PME_ITA_DATA_EAR_CACHE_LAT2048 118
272{ "DATA_EAR_CACHE_LAT2048", {0xa0367} , 0xf0, 1, {0xffff0003}, NULL},
273#define PME_ITA_DATA_EAR_CACHE_LAT256 119
274{ "DATA_EAR_CACHE_LAT256", {0x60367} , 0xf0, 1, {0xffff0003}, NULL},
275#define PME_ITA_DATA_EAR_CACHE_LAT32 120
276{ "DATA_EAR_CACHE_LAT32", {0x30367} , 0xf0, 1, {0xffff0003}, NULL},
277#define PME_ITA_DATA_EAR_CACHE_LAT4 121
278{ "DATA_EAR_CACHE_LAT4", {0x367} , 0xf0, 1, {0xffff0003}, NULL},
279#define PME_ITA_DATA_EAR_CACHE_LAT512 122
280{ "DATA_EAR_CACHE_LAT512", {0x80367} , 0xf0, 1, {0xffff0003}, NULL},
281#define PME_ITA_DATA_EAR_CACHE_LAT64 123
282{ "DATA_EAR_CACHE_LAT64", {0x40367} , 0xf0, 1, {0xffff0003}, NULL},
283#define PME_ITA_DATA_EAR_CACHE_LAT8 124
284{ "DATA_EAR_CACHE_LAT8", {0x10367} , 0xf0, 1, {0xffff0003}, NULL},
285#define PME_ITA_DATA_EAR_CACHE_LAT_NONE 125
286{ "DATA_EAR_CACHE_LAT_NONE", {0xf0367} , 0xf0, 1, {0xffff0003}, NULL},
287#define PME_ITA_DATA_EAR_EVENTS 126
288{ "DATA_EAR_EVENTS", {0x67} , 0xf0, 1, {0xffff0007}, NULL},
289#define PME_ITA_DATA_EAR_TLB_L2 127
290{ "DATA_EAR_TLB_L2", {0x20767} , 0xf0, 1, {0xffff0003}, NULL},
291#define PME_ITA_DATA_EAR_TLB_SW 128
292{ "DATA_EAR_TLB_SW", {0x80767} , 0xf0, 1, {0xffff0003}, NULL},
293#define PME_ITA_DATA_EAR_TLB_VHPT 129
294{ "DATA_EAR_TLB_VHPT", {0x40767} , 0xf0, 1, {0xffff0003}, NULL},
295#define PME_ITA_DATA_REFERENCES_RETIRED 130
296{ "DATA_REFERENCES_RETIRED", {0x63} , 0xf0, 2, {0xffff0007}, NULL},
297#define PME_ITA_DEPENDENCY_ALL_CYCLE 131
298{ "DEPENDENCY_ALL_CYCLE", {0x6} , 0xf0, 1, {0xffff0000}, NULL},
299#define PME_ITA_DEPENDENCY_SCOREBOARD_CYCLE 132
300{ "DEPENDENCY_SCOREBOARD_CYCLE", {0x2} , 0xf0, 1, {0xffff0000}, NULL},
301#define PME_ITA_DTC_MISSES 133
302{ "DTC_MISSES", {0x60} , 0xf0, 1, {0xffff0007}, NULL},
303#define PME_ITA_DTLB_INSERTS_HPW 134
304{ "DTLB_INSERTS_HPW", {0x62} , 0xf0, 1, {0xffff0007}, NULL},
305#define PME_ITA_DTLB_MISSES 135
306{ "DTLB_MISSES", {0x61} , 0xf0, 1, {0xffff0007}, NULL},
307#define PME_ITA_EXPL_STOPBITS 136
308{ "EXPL_STOPBITS", {0x2e} , 0xf0, 1, {0xffff0001}, NULL},
309#define PME_ITA_FP_FLUSH_TO_ZERO 137
310{ "FP_FLUSH_TO_ZERO", {0xb} , 0xf0, 2, {0xffff0003}, NULL},
311#define PME_ITA_FP_OPS_RETIRED_HI 138
312{ "FP_OPS_RETIRED_HI", {0xa} , 0xf0, 3, {0xffff0003}, NULL},
313#define PME_ITA_FP_OPS_RETIRED_LO 139
314{ "FP_OPS_RETIRED_LO", {0x9} , 0xf0, 3, {0xffff0003}, NULL},
315#define PME_ITA_FP_SIR_FLUSH 140
316{ "FP_SIR_FLUSH", {0xc} , 0xf0, 2, {0xffff0003}, NULL},
317#define PME_ITA_IA32_INST_RETIRED 141
318{ "IA32_INST_RETIRED", {0x15} , 0xf0, 2, {0xffff0000}, NULL},
319#define PME_ITA_IA64_INST_RETIRED 142
320{ "IA64_INST_RETIRED", {0x8} , 0x30, 6, {0xffff0003}, NULL},
321#define PME_ITA_IA64_TAGGED_INST_RETIRED_PMC8 143
322{ "IA64_TAGGED_INST_RETIRED_PMC8", {0x30008} , 0x30, 6, {0xffff0003}, NULL},
323#define PME_ITA_IA64_TAGGED_INST_RETIRED_PMC9 144
324{ "IA64_TAGGED_INST_RETIRED_PMC9", {0x20008} , 0x30, 6, {0xffff0003}, NULL},
325#define PME_ITA_INST_ACCESS_CYCLE 145
326{ "INST_ACCESS_CYCLE", {0x1} , 0xf0, 1, {0xffff0000}, NULL},
327#define PME_ITA_INST_DISPERSED 146
328{ "INST_DISPERSED", {0x2d} , 0x30, 6, {0xffff0001}, NULL},
329#define PME_ITA_INST_FAILED_CHKS_RETIRED_ALL 147
330{ "INST_FAILED_CHKS_RETIRED_ALL", {0x30035} , 0xf0, 1, {0xffff0003}, NULL},
331#define PME_ITA_INST_FAILED_CHKS_RETIRED_FP 148
332{ "INST_FAILED_CHKS_RETIRED_FP", {0x20035} , 0xf0, 1, {0xffff0003}, NULL},
333#define PME_ITA_INST_FAILED_CHKS_RETIRED_INT 149
334{ "INST_FAILED_CHKS_RETIRED_INT", {0x10035} , 0xf0, 1, {0xffff0003}, NULL},
335#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT1024 150
336{ "INSTRUCTION_EAR_CACHE_LAT1024", {0x80123} , 0xf0, 1, {0xffff0001}, NULL},
337#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT128 151
338{ "INSTRUCTION_EAR_CACHE_LAT128", {0x50123} , 0xf0, 1, {0xffff0001}, NULL},
339#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT16 152
340{ "INSTRUCTION_EAR_CACHE_LAT16", {0x20123} , 0xf0, 1, {0xffff0001}, NULL},
341#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT2048 153
342{ "INSTRUCTION_EAR_CACHE_LAT2048", {0x90123} , 0xf0, 1, {0xffff0001}, NULL},
343#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT256 154
344{ "INSTRUCTION_EAR_CACHE_LAT256", {0x60123} , 0xf0, 1, {0xffff0001}, NULL},
345#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT32 155
346{ "INSTRUCTION_EAR_CACHE_LAT32", {0x30123} , 0xf0, 1, {0xffff0001}, NULL},
347#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT4096 156
348{ "INSTRUCTION_EAR_CACHE_LAT4096", {0xa0123} , 0xf0, 1, {0xffff0001}, NULL},
349#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT4 157
350{ "INSTRUCTION_EAR_CACHE_LAT4", {0x123} , 0xf0, 1, {0xffff0001}, NULL},
351#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT512 158
352{ "INSTRUCTION_EAR_CACHE_LAT512", {0x70123} , 0xf0, 1, {0xffff0001}, NULL},
353#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT64 159
354{ "INSTRUCTION_EAR_CACHE_LAT64", {0x40123} , 0xf0, 1, {0xffff0001}, NULL},
355#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT8 160
356{ "INSTRUCTION_EAR_CACHE_LAT8", {0x10123} , 0xf0, 1, {0xffff0001}, NULL},
357#define PME_ITA_INSTRUCTION_EAR_CACHE_LAT_NONE 161
358{ "INSTRUCTION_EAR_CACHE_LAT_NONE", {0xf0123} , 0xf0, 1, {0xffff0001}, NULL},
359#define PME_ITA_INSTRUCTION_EAR_EVENTS 162
360{ "INSTRUCTION_EAR_EVENTS", {0x23} , 0xf0, 1, {0xffff0001}, NULL},
361#define PME_ITA_INSTRUCTION_EAR_TLB_SW 163
362{ "INSTRUCTION_EAR_TLB_SW", {0x80523} , 0xf0, 1, {0xffff0001}, NULL},
363#define PME_ITA_INSTRUCTION_EAR_TLB_VHPT 164
364{ "INSTRUCTION_EAR_TLB_VHPT", {0x40523} , 0xf0, 1, {0xffff0001}, NULL},
365#define PME_ITA_ISA_TRANSITIONS 165
366{ "ISA_TRANSITIONS", {0x14} , 0xf0, 1, {0xffff0000}, NULL},
367#define PME_ITA_ISB_LINES_IN 166
368{ "ISB_LINES_IN", {0x26} , 0xf0, 1, {0xffff0000}, NULL},
369#define PME_ITA_ITLB_INSERTS_HPW 167
370{ "ITLB_INSERTS_HPW", {0x28} , 0xf0, 1, {0xffff0001}, NULL},
371#define PME_ITA_ITLB_MISSES_FETCH 168
372{ "ITLB_MISSES_FETCH", {0x27} , 0xf0, 1, {0xffff0001}, NULL},
373#define PME_ITA_L1D_READ_FORCED_MISSES_RETIRED 169
374{ "L1D_READ_FORCED_MISSES_RETIRED", {0x6b} , 0xf0, 2, {0xffff0007}, NULL},
375#define PME_ITA_L1D_READ_MISSES_RETIRED 170
376{ "L1D_READ_MISSES_RETIRED", {0x66} , 0xf0, 2, {0xffff0007}, NULL},
377#define PME_ITA_L1D_READS_RETIRED 171
378{ "L1D_READS_RETIRED", {0x64} , 0xf0, 2, {0xffff0007}, NULL},
379#define PME_ITA_L1I_DEMAND_READS 172
380{ "L1I_DEMAND_READS", {0x20} , 0xf0, 1, {0xffff0001}, NULL},
381#define PME_ITA_L1I_FILLS 173
382{ "L1I_FILLS", {0x21} , 0xf0, 1, {0xffff0000}, NULL},
383#define PME_ITA_L1I_PREFETCH_READS 174
384{ "L1I_PREFETCH_READS", {0x24} , 0xf0, 1, {0xffff0001}, NULL},
385#define PME_ITA_L1_OUTSTANDING_REQ_HI 175
386{ "L1_OUTSTANDING_REQ_HI", {0x79} , 0xf0, 1, {0xffff0000}, NULL},
387#define PME_ITA_L1_OUTSTANDING_REQ_LO 176
388{ "L1_OUTSTANDING_REQ_LO", {0x78} , 0xf0, 1, {0xffff0000}, NULL},
389#define PME_ITA_L2_DATA_REFERENCES_ALL 177
390{ "L2_DATA_REFERENCES_ALL", {0x30069} , 0xf0, 2, {0xffff0007}, NULL},
391#define PME_ITA_L2_DATA_REFERENCES_READS 178
392{ "L2_DATA_REFERENCES_READS", {0x10069} , 0xf0, 2, {0xffff0007}, NULL},
393#define PME_ITA_L2_DATA_REFERENCES_WRITES 179
394{ "L2_DATA_REFERENCES_WRITES", {0x20069} , 0xf0, 2, {0xffff0007}, NULL},
395#define PME_ITA_L2_FLUSH_DETAILS_ADDR_CONFLICT 180
396{ "L2_FLUSH_DETAILS_ADDR_CONFLICT", {0x20077} , 0xf0, 1, {0xffff0000}, NULL},
397#define PME_ITA_L2_FLUSH_DETAILS_ALL 181
398{ "L2_FLUSH_DETAILS_ALL", {0xf0077} , 0xf0, 1, {0xffff0000}, NULL},
399#define PME_ITA_L2_FLUSH_DETAILS_BUS_REJECT 182
400{ "L2_FLUSH_DETAILS_BUS_REJECT", {0x40077} , 0xf0, 1, {0xffff0000}, NULL},
401#define PME_ITA_L2_FLUSH_DETAILS_FULL_FLUSH 183
402{ "L2_FLUSH_DETAILS_FULL_FLUSH", {0x80077} , 0xf0, 1, {0xffff0000}, NULL},
403#define PME_ITA_L2_FLUSH_DETAILS_ST_BUFFER 184
404{ "L2_FLUSH_DETAILS_ST_BUFFER", {0x10077} , 0xf0, 1, {0xffff0000}, NULL},
405#define PME_ITA_L2_FLUSHES 185
406{ "L2_FLUSHES", {0x76} , 0xf0, 1, {0xffff0000}, NULL},
407#define PME_ITA_L2_INST_DEMAND_READS 186
408{ "L2_INST_DEMAND_READS", {0x22} , 0xf0, 1, {0xffff0001}, NULL},
409#define PME_ITA_L2_INST_PREFETCH_READS 187
410{ "L2_INST_PREFETCH_READS", {0x25} , 0xf0, 1, {0xffff0001}, NULL},
411#define PME_ITA_L2_MISSES 188
412{ "L2_MISSES", {0x6a} , 0xf0, 2, {0xffff0007}, NULL},
413#define PME_ITA_L2_REFERENCES 189
414{ "L2_REFERENCES", {0x68} , 0xf0, 3, {0xffff0007}, NULL},
415#define PME_ITA_L3_LINES_REPLACED 190
416{ "L3_LINES_REPLACED", {0x7f} , 0xf0, 1, {0xffff0000}, NULL},
417#define PME_ITA_L3_MISSES 191
418{ "L3_MISSES", {0x7c} , 0xf0, 1, {0xffff0000}, NULL},
419#define PME_ITA_L3_READS_ALL_READS_ALL 192
420{ "L3_READS_ALL_READS_ALL", {0xf007d} , 0xf0, 1, {0xffff0000}, NULL},
421#define PME_ITA_L3_READS_ALL_READS_HIT 193
422{ "L3_READS_ALL_READS_HIT", {0xd007d} , 0xf0, 1, {0xffff0000}, NULL},
423#define PME_ITA_L3_READS_ALL_READS_MISS 194
424{ "L3_READS_ALL_READS_MISS", {0xe007d} , 0xf0, 1, {0xffff0000}, NULL},
425#define PME_ITA_L3_READS_DATA_READS_ALL 195
426{ "L3_READS_DATA_READS_ALL", {0xb007d} , 0xf0, 1, {0xffff0000}, NULL},
427#define PME_ITA_L3_READS_DATA_READS_HIT 196
428{ "L3_READS_DATA_READS_HIT", {0x9007d} , 0xf0, 1, {0xffff0000}, NULL},
429#define PME_ITA_L3_READS_DATA_READS_MISS 197
430{ "L3_READS_DATA_READS_MISS", {0xa007d} , 0xf0, 1, {0xffff0000}, NULL},
431#define PME_ITA_L3_READS_INST_READS_ALL 198
432{ "L3_READS_INST_READS_ALL", {0x7007d} , 0xf0, 1, {0xffff0000}, NULL},
433#define PME_ITA_L3_READS_INST_READS_HIT 199
434{ "L3_READS_INST_READS_HIT", {0x5007d} , 0xf0, 1, {0xffff0000}, NULL},
435#define PME_ITA_L3_READS_INST_READS_MISS 200
436{ "L3_READS_INST_READS_MISS", {0x6007d} , 0xf0, 1, {0xffff0000}, NULL},
437#define PME_ITA_L3_REFERENCES 201
438{ "L3_REFERENCES", {0x7b} , 0xf0, 1, {0xffff0007}, NULL},
439#define PME_ITA_L3_WRITES_ALL_WRITES_ALL 202
440{ "L3_WRITES_ALL_WRITES_ALL", {0xf007e} , 0xf0, 1, {0xffff0000}, NULL},
441#define PME_ITA_L3_WRITES_ALL_WRITES_HIT 203
442{ "L3_WRITES_ALL_WRITES_HIT", {0xd007e} , 0xf0, 1, {0xffff0000}, NULL},
443#define PME_ITA_L3_WRITES_ALL_WRITES_MISS 204
444{ "L3_WRITES_ALL_WRITES_MISS", {0xe007e} , 0xf0, 1, {0xffff0000}, NULL},
445#define PME_ITA_L3_WRITES_DATA_WRITES_ALL 205
446{ "L3_WRITES_DATA_WRITES_ALL", {0x7007e} , 0xf0, 1, {0xffff0000}, NULL},
447#define PME_ITA_L3_WRITES_DATA_WRITES_HIT 206
448{ "L3_WRITES_DATA_WRITES_HIT", {0x5007e} , 0xf0, 1, {0xffff0000}, NULL},
449#define PME_ITA_L3_WRITES_DATA_WRITES_MISS 207
450{ "L3_WRITES_DATA_WRITES_MISS", {0x6007e} , 0xf0, 1, {0xffff0000}, NULL},
451#define PME_ITA_L3_WRITES_L2_WRITEBACK_ALL 208
452{ "L3_WRITES_L2_WRITEBACK_ALL", {0xb007e} , 0xf0, 1, {0xffff0000}, NULL},
453#define PME_ITA_L3_WRITES_L2_WRITEBACK_HIT 209
454{ "L3_WRITES_L2_WRITEBACK_HIT", {0x9007e} , 0xf0, 1, {0xffff0000}, NULL},
455#define PME_ITA_L3_WRITES_L2_WRITEBACK_MISS 210
456{ "L3_WRITES_L2_WRITEBACK_MISS", {0xa007e} , 0xf0, 1, {0xffff0000}, NULL},
457#define PME_ITA_LOADS_RETIRED 211
458{ "LOADS_RETIRED", {0x6c} , 0xf0, 2, {0xffff0007}, NULL},
459#define PME_ITA_MEMORY_CYCLE 212
460{ "MEMORY_CYCLE", {0x7} , 0xf0, 1, {0xffff0000}, NULL},
461#define PME_ITA_MISALIGNED_LOADS_RETIRED 213
462{ "MISALIGNED_LOADS_RETIRED", {0x70} , 0xf0, 2, {0xffff0007}, NULL},
463#define PME_ITA_MISALIGNED_STORES_RETIRED 214
464{ "MISALIGNED_STORES_RETIRED", {0x71} , 0xf0, 2, {0xffff0007}, NULL},
465#define PME_ITA_NOPS_RETIRED 215
466{ "NOPS_RETIRED", {0x30} , 0x30, 6, {0xffff0003}, NULL},
467#define PME_ITA_PIPELINE_ALL_FLUSH_CYCLE 216
468{ "PIPELINE_ALL_FLUSH_CYCLE", {0x4} , 0xf0, 1, {0xffff0000}, NULL},
469#define PME_ITA_PIPELINE_BACKEND_FLUSH_CYCLE 217
470{ "PIPELINE_BACKEND_FLUSH_CYCLE", {0x0} , 0xf0, 1, {0xffff0000}, NULL},
471#define PME_ITA_PIPELINE_FLUSH_ALL 218
472{ "PIPELINE_FLUSH_ALL", {0xf0033} , 0xf0, 1, {0xffff0000}, NULL},
473#define PME_ITA_PIPELINE_FLUSH_DTC_FLUSH 219
474{ "PIPELINE_FLUSH_DTC_FLUSH", {0x40033} , 0xf0, 1, {0xffff0000}, NULL},
475#define PME_ITA_PIPELINE_FLUSH_IEU_FLUSH 220
476{ "PIPELINE_FLUSH_IEU_FLUSH", {0x80033} , 0xf0, 1, {0xffff0000}, NULL},
477#define PME_ITA_PIPELINE_FLUSH_L1D_WAYMP_FLUSH 221
478{ "PIPELINE_FLUSH_L1D_WAYMP_FLUSH", {0x20033} , 0xf0, 1, {0xffff0000}, NULL},
479#define PME_ITA_PIPELINE_FLUSH_OTHER_FLUSH 222
480{ "PIPELINE_FLUSH_OTHER_FLUSH", {0x10033} , 0xf0, 1, {0xffff0000}, NULL},
481#define PME_ITA_PREDICATE_SQUASHED_RETIRED 223
482{ "PREDICATE_SQUASHED_RETIRED", {0x31} , 0x30, 6, {0xffff0003}, NULL},
483#define PME_ITA_RSE_LOADS_RETIRED 224
484{ "RSE_LOADS_RETIRED", {0x72} , 0xf0, 2, {0xffff0007}, NULL},
485#define PME_ITA_RSE_REFERENCES_RETIRED 225
486{ "RSE_REFERENCES_RETIRED", {0x65} , 0xf0, 2, {0xffff0007}, NULL},
487#define PME_ITA_STORES_RETIRED 226
488{ "STORES_RETIRED", {0x6d} , 0xf0, 2, {0xffff0007}, NULL},
489#define PME_ITA_UC_LOADS_RETIRED 227
490{ "UC_LOADS_RETIRED", {0x6e} , 0xf0, 2, {0xffff0007}, NULL},
491#define PME_ITA_UC_STORES_RETIRED 228
492{ "UC_STORES_RETIRED", {0x6f} , 0xf0, 2, {0xffff0007}, NULL},
493#define PME_ITA_UNSTALLED_BACKEND_CYCLE 229
494{ "UNSTALLED_BACKEND_CYCLE", {0x5} , 0xf0, 1, {0xffff0000}, NULL}};
495#define PME_ITA_EVENT_COUNT 230
itanium_pe
static pme_ita_entry_t itanium_pe[]
Definition: itanium_events.h:34
pme_ita_entry_t
Definition: pfmlib_itanium_priv.h:60