32#define PME_ITA2_ALAT_CAPACITY_MISS_ALL 0
33{
"ALAT_CAPACITY_MISS_ALL", {0x30058}, 0xf0, 2, {0xf00007},
"ALAT Entry Replaced -- both integer and floating point instructions"},
34#define PME_ITA2_ALAT_CAPACITY_MISS_FP 1
35{
"ALAT_CAPACITY_MISS_FP", {0x20058}, 0xf0, 2, {0xf00007},
"ALAT Entry Replaced -- only floating point instructions"},
36#define PME_ITA2_ALAT_CAPACITY_MISS_INT 2
37{
"ALAT_CAPACITY_MISS_INT", {0x10058}, 0xf0, 2, {0xf00007},
"ALAT Entry Replaced -- only integer instructions"},
38#define PME_ITA2_BACK_END_BUBBLE_ALL 3
39{
"BACK_END_BUBBLE_ALL", {0x0}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe -- Front-end, RSE, EXE, FPU/L1D stall or a pipeline flush due to an exception/branch misprediction"},
40#define PME_ITA2_BACK_END_BUBBLE_FE 4
41{
"BACK_END_BUBBLE_FE", {0x10000}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe -- front-end"},
42#define PME_ITA2_BACK_END_BUBBLE_L1D_FPU_RSE 5
43{
"BACK_END_BUBBLE_L1D_FPU_RSE", {0x20000}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe -- L1D_FPU or RSE."},
44#define PME_ITA2_BE_BR_MISPRED_DETAIL_ANY 6
45{
"BE_BR_MISPRED_DETAIL_ANY", {0x61}, 0xf0, 1, {0xf00003},
"BE Branch Misprediction Detail -- any back-end (be) mispredictions"},
46#define PME_ITA2_BE_BR_MISPRED_DETAIL_PFS 7
47{
"BE_BR_MISPRED_DETAIL_PFS", {0x30061}, 0xf0, 1, {0xf00003},
"BE Branch Misprediction Detail -- only back-end pfs mispredictions for taken branches"},
48#define PME_ITA2_BE_BR_MISPRED_DETAIL_ROT 8
49{
"BE_BR_MISPRED_DETAIL_ROT", {0x20061}, 0xf0, 1, {0xf00003},
"BE Branch Misprediction Detail -- only back-end rotate mispredictions"},
50#define PME_ITA2_BE_BR_MISPRED_DETAIL_STG 9
51{
"BE_BR_MISPRED_DETAIL_STG", {0x10061}, 0xf0, 1, {0xf00003},
"BE Branch Misprediction Detail -- only back-end stage mispredictions"},
52#define PME_ITA2_BE_EXE_BUBBLE_ALL 10
53{
"BE_EXE_BUBBLE_ALL", {0x2}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe"},
54#define PME_ITA2_BE_EXE_BUBBLE_ARCR 11
55{
"BE_EXE_BUBBLE_ARCR", {0x40002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to AR or CR dependency"},
56#define PME_ITA2_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 12
57{
"BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK", {0x80002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- ARCR, PR, CANCEL or BANK_SWITCH"},
58#define PME_ITA2_BE_EXE_BUBBLE_BANK_SWITCH 13
59{
"BE_EXE_BUBBLE_BANK_SWITCH", {0x70002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to bank switching."},
60#define PME_ITA2_BE_EXE_BUBBLE_CANCEL 14
61{
"BE_EXE_BUBBLE_CANCEL", {0x60002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to a canceled load"},
62#define PME_ITA2_BE_EXE_BUBBLE_FRALL 15
63{
"BE_EXE_BUBBLE_FRALL", {0x20002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to FR/FR or FR/load dependency"},
64#define PME_ITA2_BE_EXE_BUBBLE_GRALL 16
65{
"BE_EXE_BUBBLE_GRALL", {0x10002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR or GR/load dependency"},
66#define PME_ITA2_BE_EXE_BUBBLE_GRGR 17
67{
"BE_EXE_BUBBLE_GRGR", {0x50002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR dependency"},
68#define PME_ITA2_BE_EXE_BUBBLE_PR 18
69{
"BE_EXE_BUBBLE_PR", {0x30002}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to PR dependency"},
70#define PME_ITA2_BE_FLUSH_BUBBLE_ALL 19
71{
"BE_FLUSH_BUBBLE_ALL", {0x4}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to either an exception/interruption or branch misprediction flush"},
72#define PME_ITA2_BE_FLUSH_BUBBLE_BRU 20
73{
"BE_FLUSH_BUBBLE_BRU", {0x10004}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to a branch misprediction flush"},
74#define PME_ITA2_BE_FLUSH_BUBBLE_XPN 21
75{
"BE_FLUSH_BUBBLE_XPN", {0x20004}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to an exception/interruption flush"},
76#define PME_ITA2_BE_L1D_FPU_BUBBLE_ALL 22
77{
"BE_L1D_FPU_BUBBLE_ALL", {0xca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D or FPU"},
78#define PME_ITA2_BE_L1D_FPU_BUBBLE_FPU 23
79{
"BE_L1D_FPU_BUBBLE_FPU", {0x100ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by FPU."},
80#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D 24
81{
"BE_L1D_FPU_BUBBLE_L1D", {0x200ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D. This includes all stalls caused by the L1 pipeline (created in the L1D stage of the L1 pipeline which corresponds to the DET stage of the main pipe)."},
82#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCS 25
83{
"BE_L1D_FPU_BUBBLE_L1D_DCS", {0x800ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCS requiring a stall"},
84#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCURECIR 26
85{
"BE_L1D_FPU_BUBBLE_L1D_DCURECIR", {0x400ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCU recirculating"},
86#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 27
87{
"BE_L1D_FPU_BUBBLE_L1D_FILLCONF", {0x700ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due a store in conflict with a returning fill."},
88#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 28
89{
"BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF", {0x300ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer being full"},
90#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_HPW 29
91{
"BE_L1D_FPU_BUBBLE_L1D_HPW", {0x500ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to Hardware Page Walker"},
92#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 30
93{
"BE_L1D_FPU_BUBBLE_L1D_L2BPRESS", {0x900ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2 Back Pressure"},
94#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCHK 31
95{
"BE_L1D_FPU_BUBBLE_L1D_LDCHK", {0xc00ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"},
96#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCONF 32
97{
"BE_L1D_FPU_BUBBLE_L1D_LDCONF", {0xb00ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"},
98#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NAT 33
99{
"BE_L1D_FPU_BUBBLE_L1D_NAT", {0xd00ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L1D data return needing recirculated NaT generation."},
100#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NATCONF 34
101{
"BE_L1D_FPU_BUBBLE_L1D_NATCONF", {0xf00ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ld8.fill conflict with st8.spill not written to unat."},
102#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 35
103{
"BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR", {0xe00ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer cancel needing recirculate."},
104#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_TLB 36
105{
"BE_L1D_FPU_BUBBLE_L1D_TLB", {0xa00ca}, 0xf0, 1, {0x5210000},
"Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2DTLB to L1DTLB transfer"},
106#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_ALL 37
107{
"BE_LOST_BW_DUE_TO_FE_ALL", {0x72}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- count regardless of cause"},
108#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BI 38
109{
"BE_LOST_BW_DUE_TO_FE_BI", {0x90072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch initialization stall"},
110#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BRQ 39
111{
"BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch retirement queue stall"},
112#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 40
113{
"BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch interlock stall"},
114#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BUBBLE 41
115{
"BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch resteer bubble stall"},
116#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FEFLUSH 42
117{
"BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a front-end flush"},
118#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 43
119{
"BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a recirculate for a cache line fill operation"},
120#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IBFULL 44
121{
"BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- (* meaningless for this event *)"},
122#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IMISS 45
123{
"BE_LOST_BW_DUE_TO_FE_IMISS", {0x60072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by instruction cache miss stall"},
124#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_PLP 46
125{
"BE_LOST_BW_DUE_TO_FE_PLP", {0xb0072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by perfect loop prediction stall"},
126#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_TLBMISS 47
127{
"BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by TLB stall"},
128#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_UNREACHED 48
129{
"BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40072}, 0xf0, 2, {0xf00000},
"Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by unreachable bundle"},
130#define PME_ITA2_BE_RSE_BUBBLE_ALL 49
131{
"BE_RSE_BUBBLE_ALL", {0x1}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE"},
132#define PME_ITA2_BE_RSE_BUBBLE_AR_DEP 50
133{
"BE_RSE_BUBBLE_AR_DEP", {0x20001}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to AR dependencies"},
134#define PME_ITA2_BE_RSE_BUBBLE_BANK_SWITCH 51
135{
"BE_RSE_BUBBLE_BANK_SWITCH", {0x10001}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to bank switching"},
136#define PME_ITA2_BE_RSE_BUBBLE_LOADRS 52
137{
"BE_RSE_BUBBLE_LOADRS", {0x50001}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to loadrs calculations"},
138#define PME_ITA2_BE_RSE_BUBBLE_OVERFLOW 53
139{
"BE_RSE_BUBBLE_OVERFLOW", {0x30001}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to spill"},
140#define PME_ITA2_BE_RSE_BUBBLE_UNDERFLOW 54
141{
"BE_RSE_BUBBLE_UNDERFLOW", {0x40001}, 0xf0, 1, {0xf00000},
"Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to fill"},
142#define PME_ITA2_BRANCH_EVENT 55
143{
"BRANCH_EVENT", {0x111}, 0xf0, 1, {0xf00003},
"Branch Event Captured"},
144#define PME_ITA2_BR_MISPRED_DETAIL_ALL_ALL_PRED 56
145{
"BR_MISPRED_DETAIL_ALL_ALL_PRED", {0x5b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- All branch types regardless of prediction result"},
146#define PME_ITA2_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 57
147{
"BR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x1005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- All branch types, correctly predicted branches (outcome and target)"},
148#define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_PATH 58
149{
"BR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x2005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong branch direction"},
150#define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 59
151{
"BR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x3005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong target for taken branches"},
152#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_ALL_PRED 60
153{
"BR_MISPRED_DETAIL_IPREL_ALL_PRED", {0x4005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only IP relative branches, regardless of prediction result"},
154#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 61
155{
"BR_MISPRED_DETAIL_IPREL_CORRECT_PRED", {0x5005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only IP relative branches, correctly predicted branches (outcome and target)"},
156#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 62
157{
"BR_MISPRED_DETAIL_IPREL_WRONG_PATH", {0x6005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong branch direction"},
158#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 63
159{
"BR_MISPRED_DETAIL_IPREL_WRONG_TARGET", {0x7005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong target for taken branches"},
160#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_ALL_PRED 64
161{
"BR_MISPRED_DETAIL_NTRETIND_ALL_PRED", {0xc005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only non-return indirect branches, regardless of prediction result"},
162#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED 65
163{
"BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED", {0xd005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only non-return indirect branches, correctly predicted branches (outcome and target)"},
164#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH 66
165{
"BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH", {0xe005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"},
166#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET 67
167{
"BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET", {0xf005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"},
168#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_ALL_PRED 68
169{
"BR_MISPRED_DETAIL_RETURN_ALL_PRED", {0x8005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only return type branches, regardless of prediction result"},
170#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 69
171{
"BR_MISPRED_DETAIL_RETURN_CORRECT_PRED", {0x9005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only return type branches, correctly predicted branches (outcome and target)"},
172#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 70
173{
"BR_MISPRED_DETAIL_RETURN_WRONG_PATH", {0xa005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong branch direction"},
174#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 71
175{
"BR_MISPRED_DETAIL_RETURN_WRONG_TARGET", {0xb005b}, 0xf0, 3, {0xf00003},
"FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong target for taken branches"},
176#define PME_ITA2_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 72
177{
"BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED", {0x68}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction"},
178#define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 73
179{
"BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED", {0x10068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and correctly predicted branch (outcome & target)"},
180#define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 74
181{
"BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH", {0x20068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and wrong branch direction"},
182#define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 75
183{
"BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED", {0x40068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction"},
184#define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 76
185{
"BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED", {0x50068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and correct predicted branch (outcome & target)"},
186#define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 77
187{
"BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH", {0x60068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and wrong branch direction"},
188#define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 78
189{
"BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED", {0xc0068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction"},
190#define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 79
191{
"BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED", {0xd0068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and correct predicted branch (outcome & target)"},
192#define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 80
193{
"BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH", {0xe0068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and wrong branch direction"},
194#define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 81
195{
"BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED", {0x80068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction"},
196#define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 82
197{
"BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED", {0x90068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and correct predicted branch (outcome & target)"},
198#define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 83
199{
"BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH", {0xa0068}, 0xf0, 2, {0xf00003},
"FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and wrong branch direction"},
200#define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 84
201{
"BR_PATH_PRED_ALL_MISPRED_NOTTAKEN", {0x54}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and not taken branch"},
202#define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_TAKEN 85
203{
"BR_PATH_PRED_ALL_MISPRED_TAKEN", {0x10054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and taken branch"},
204#define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 86
205{
"BR_PATH_PRED_ALL_OKPRED_NOTTAKEN", {0x20054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- All branch types, correctly predicted path and not taken branch"},
206#define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_TAKEN 87
207{
"BR_PATH_PRED_ALL_OKPRED_TAKEN", {0x30054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- All branch types, correctly predicted path and taken branch"},
208#define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 88
209{
"BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN", {0x40054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and not taken branch"},
210#define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_TAKEN 89
211{
"BR_PATH_PRED_IPREL_MISPRED_TAKEN", {0x50054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and taken branch"},
212#define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 90
213{
"BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN", {0x60054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and not taken branch"},
214#define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_TAKEN 91
215{
"BR_PATH_PRED_IPREL_OKPRED_TAKEN", {0x70054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and taken branch"},
216#define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 92
217{
"BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN", {0xc0054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and not taken branch"},
218#define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 93
219{
"BR_PATH_PRED_NRETIND_MISPRED_TAKEN", {0xd0054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and taken branch"},
220#define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 94
221{
"BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN", {0xe0054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and not taken branch"},
222#define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 95
223{
"BR_PATH_PRED_NRETIND_OKPRED_TAKEN", {0xf0054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and taken branch"},
224#define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 96
225{
"BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN", {0x80054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and not taken branch"},
226#define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_TAKEN 97
227{
"BR_PATH_PRED_RETURN_MISPRED_TAKEN", {0x90054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and taken branch"},
228#define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 98
229{
"BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN", {0xa0054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and not taken branch"},
230#define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_TAKEN 99
231{
"BR_PATH_PRED_RETURN_OKPRED_TAKEN", {0xb0054}, 0xf0, 3, {0xf00003},
"FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and taken branch"},
232#define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 100
233{
"BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN", {0x6a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"},
234#define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 101
235{
"BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN", {0x1006a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"},
236#define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 102
237{
"BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN", {0x4006a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"},
238#define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 103
239{
"BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN", {0x5006a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"},
240#define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 104
241{
"BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN", {0xc006a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"},
242#define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 105
243{
"BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN", {0xd006a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"},
244#define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 106
245{
"BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN", {0x8006a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"},
246#define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 107
247{
"BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN", {0x9006a}, 0xf0, 2, {0xf00003},
"FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"},
248#define PME_ITA2_BUS_ALL_ANY 108
249{
"BUS_ALL_ANY", {0x30087}, 0xf0, 1, {0xf00000},
"Bus Transactions -- CPU or non-CPU (all transactions)."},
250#define PME_ITA2_BUS_ALL_IO 109
251{
"BUS_ALL_IO", {0x10087}, 0xf0, 1, {0xf00000},
"Bus Transactions -- non-CPU priority agents"},
252#define PME_ITA2_BUS_ALL_SELF 110
253{
"BUS_ALL_SELF", {0x20087}, 0xf0, 1, {0xf00000},
"Bus Transactions -- local processor"},
254#define PME_ITA2_BUS_BACKSNP_REQ_THIS 111
255{
"BUS_BACKSNP_REQ_THIS", {0x1008e}, 0xf0, 1, {0xf00000},
"Bus Back Snoop Requests -- Counts the number of bus back snoop me requests"},
256#define PME_ITA2_BUS_BRQ_LIVE_REQ_HI 112
257{
"BUS_BRQ_LIVE_REQ_HI", {0x9c}, 0xf0, 2, {0xf00000},
"BRQ Live Requests (upper 2 bits)"},
258#define PME_ITA2_BUS_BRQ_LIVE_REQ_LO 113
259{
"BUS_BRQ_LIVE_REQ_LO", {0x9b}, 0xf0, 7, {0xf00000},
"BRQ Live Requests (lower 3 bits)"},
260#define PME_ITA2_BUS_BRQ_REQ_INSERTED 114
261{
"BUS_BRQ_REQ_INSERTED", {0x9d}, 0xf0, 1, {0xf00000},
"BRQ Requests Inserted"},
262#define PME_ITA2_BUS_DATA_CYCLE 115
263{
"BUS_DATA_CYCLE", {0x88}, 0xf0, 1, {0xf00000},
"Valid Data Cycle on the Bus"},
264#define PME_ITA2_BUS_HITM 116
265{
"BUS_HITM", {0x84}, 0xf0, 1, {0xf00000},
"Bus Hit Modified Line Transactions"},
266#define PME_ITA2_BUS_IO_ANY 117
267{
"BUS_IO_ANY", {0x30090}, 0xf0, 1, {0xf00000},
"IA-32 Compatible IO Bus Transactions -- CPU or non-CPU (all transactions)."},
268#define PME_ITA2_BUS_IO_IO 118
269{
"BUS_IO_IO", {0x10090}, 0xf0, 1, {0xf00000},
"IA-32 Compatible IO Bus Transactions -- non-CPU priority agents"},
270#define PME_ITA2_BUS_IO_SELF 119
271{
"BUS_IO_SELF", {0x20090}, 0xf0, 1, {0xf00000},
"IA-32 Compatible IO Bus Transactions -- local processor"},
272#define PME_ITA2_BUS_IOQ_LIVE_REQ_HI 120
273{
"BUS_IOQ_LIVE_REQ_HI", {0x98}, 0xf0, 2, {0xf00000},
"Inorder Bus Queue Requests (upper 2 bits)"},
274#define PME_ITA2_BUS_IOQ_LIVE_REQ_LO 121
275{
"BUS_IOQ_LIVE_REQ_LO", {0x97}, 0xf0, 3, {0xf00000},
"Inorder Bus Queue Requests (lower2 bitst)"},
276#define PME_ITA2_BUS_LOCK_ANY 122
277{
"BUS_LOCK_ANY", {0x30093}, 0xf0, 1, {0xf00000},
"IA-32 Compatible Bus Lock Transactions -- CPU or non-CPU (all transactions)."},
278#define PME_ITA2_BUS_LOCK_SELF 123
279{
"BUS_LOCK_SELF", {0x20093}, 0xf0, 1, {0xf00000},
"IA-32 Compatible Bus Lock Transactions -- local processor"},
280#define PME_ITA2_BUS_MEMORY_ALL_ANY 124
281{
"BUS_MEMORY_ALL_ANY", {0xf008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions)."},
282#define PME_ITA2_BUS_MEMORY_ALL_IO 125
283{
"BUS_MEMORY_ALL_IO", {0xd008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- All bus transactions from non-CPU priority agents"},
284#define PME_ITA2_BUS_MEMORY_ALL_SELF 126
285{
"BUS_MEMORY_ALL_SELF", {0xe008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- All bus transactions from local processor"},
286#define PME_ITA2_BUS_MEMORY_EQ_128BYTE_ANY 127
287{
"BUS_MEMORY_EQ_128BYTE_ANY", {0x7008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from CPU or non-CPU (all transactions)."},
288#define PME_ITA2_BUS_MEMORY_EQ_128BYTE_IO 128
289{
"BUS_MEMORY_EQ_128BYTE_IO", {0x5008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from non-CPU priority agents"},
290#define PME_ITA2_BUS_MEMORY_EQ_128BYTE_SELF 129
291{
"BUS_MEMORY_EQ_128BYTE_SELF", {0x6008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from local processor"},
292#define PME_ITA2_BUS_MEMORY_LT_128BYTE_ANY 130
293{
"BUS_MEMORY_LT_128BYTE_ANY", {0xb008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) CPU or non-CPU (all transactions)."},
294#define PME_ITA2_BUS_MEMORY_LT_128BYTE_IO 131
295{
"BUS_MEMORY_LT_128BYTE_IO", {0x9008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) from non-CPU priority agents"},
296#define PME_ITA2_BUS_MEMORY_LT_128BYTE_SELF 132
297{
"BUS_MEMORY_LT_128BYTE_SELF", {0xa008a}, 0xf0, 1, {0xf00000},
"Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) local processor"},
298#define PME_ITA2_BUS_MEM_READ_ALL_ANY 133
299{
"BUS_MEM_READ_ALL_ANY", {0xf008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from CPU or non-CPU (all transactions)."},
300#define PME_ITA2_BUS_MEM_READ_ALL_IO 134
301{
"BUS_MEM_READ_ALL_IO", {0xd008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from non-CPU priority agents"},
302#define PME_ITA2_BUS_MEM_READ_ALL_SELF 135
303{
"BUS_MEM_READ_ALL_SELF", {0xe008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from local processor"},
304#define PME_ITA2_BUS_MEM_READ_BIL_ANY 136
305{
"BUS_MEM_READ_BIL_ANY", {0x3008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from CPU or non-CPU (all transactions)."},
306#define PME_ITA2_BUS_MEM_READ_BIL_IO 137
307{
"BUS_MEM_READ_BIL_IO", {0x1008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from non-CPU priority agents"},
308#define PME_ITA2_BUS_MEM_READ_BIL_SELF 138
309{
"BUS_MEM_READ_BIL_SELF", {0x2008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from local processor"},
310#define PME_ITA2_BUS_MEM_READ_BRIL_ANY 139
311{
"BUS_MEM_READ_BRIL_ANY", {0xb008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from CPU or non-CPU (all transactions)."},
312#define PME_ITA2_BUS_MEM_READ_BRIL_IO 140
313{
"BUS_MEM_READ_BRIL_IO", {0x9008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from non-CPU priority agents"},
314#define PME_ITA2_BUS_MEM_READ_BRIL_SELF 141
315{
"BUS_MEM_READ_BRIL_SELF", {0xa008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from local processor"},
316#define PME_ITA2_BUS_MEM_READ_BRL_ANY 142
317{
"BUS_MEM_READ_BRL_ANY", {0x7008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from CPU or non-CPU (all transactions)."},
318#define PME_ITA2_BUS_MEM_READ_BRL_IO 143
319{
"BUS_MEM_READ_BRL_IO", {0x5008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from non-CPU priority agents"},
320#define PME_ITA2_BUS_MEM_READ_BRL_SELF 144
321{
"BUS_MEM_READ_BRL_SELF", {0x6008b}, 0xf0, 1, {0xf00000},
"Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from local processor"},
322#define PME_ITA2_BUS_MEM_READ_OUT_HI 145
323{
"BUS_MEM_READ_OUT_HI", {0x94}, 0xf0, 2, {0xf00000},
"Outstanding Memory Read Transactions (upper 2 bits)"},
324#define PME_ITA2_BUS_MEM_READ_OUT_LO 146
325{
"BUS_MEM_READ_OUT_LO", {0x95}, 0xf0, 7, {0xf00000},
"Outstanding Memory Read Transactions (lower 3 bits)"},
326#define PME_ITA2_BUS_OOQ_LIVE_REQ_HI 147
327{
"BUS_OOQ_LIVE_REQ_HI", {0x9a}, 0xf0, 2, {0xf00000},
"Out-of-order Bus Queue Requests (upper 2 bits)"},
328#define PME_ITA2_BUS_OOQ_LIVE_REQ_LO 148
329{
"BUS_OOQ_LIVE_REQ_LO", {0x99}, 0xf0, 7, {0xf00000},
"Out-of-order Bus Queue Requests (lower 3 bits)"},
330#define PME_ITA2_BUS_RD_DATA_ANY 149
331{
"BUS_RD_DATA_ANY", {0x3008c}, 0xf0, 1, {0xf00000},
"Bus Read Data Transactions -- CPU or non-CPU (all transactions)."},
332#define PME_ITA2_BUS_RD_DATA_IO 150
333{
"BUS_RD_DATA_IO", {0x1008c}, 0xf0, 1, {0xf00000},
"Bus Read Data Transactions -- non-CPU priority agents"},
334#define PME_ITA2_BUS_RD_DATA_SELF 151
335{
"BUS_RD_DATA_SELF", {0x2008c}, 0xf0, 1, {0xf00000},
"Bus Read Data Transactions -- local processor"},
336#define PME_ITA2_BUS_RD_HIT 152
337{
"BUS_RD_HIT", {0x80}, 0xf0, 1, {0xf00000},
"Bus Read Hit Clean Non-local Cache Transactions"},
338#define PME_ITA2_BUS_RD_HITM 153
339{
"BUS_RD_HITM", {0x81}, 0xf0, 1, {0xf00000},
"Bus Read Hit Modified Non-local Cache Transactions"},
340#define PME_ITA2_BUS_RD_INVAL_ALL_HITM 154
341{
"BUS_RD_INVAL_ALL_HITM", {0x83}, 0xf0, 1, {0xf00000},
"Bus BRIL Burst Transaction Results in HITM"},
342#define PME_ITA2_BUS_RD_INVAL_HITM 155
343{
"BUS_RD_INVAL_HITM", {0x82}, 0xf0, 1, {0xf00000},
"Bus BIL Transaction Results in HITM"},
344#define PME_ITA2_BUS_RD_IO_ANY 156
345{
"BUS_RD_IO_ANY", {0x30091}, 0xf0, 1, {0xf00000},
"IA-32 Compatible IO Read Transactions -- CPU or non-CPU (all transactions)."},
346#define PME_ITA2_BUS_RD_IO_IO 157
347{
"BUS_RD_IO_IO", {0x10091}, 0xf0, 1, {0xf00000},
"IA-32 Compatible IO Read Transactions -- non-CPU priority agents"},
348#define PME_ITA2_BUS_RD_IO_SELF 158
349{
"BUS_RD_IO_SELF", {0x20091}, 0xf0, 1, {0xf00000},
"IA-32 Compatible IO Read Transactions -- local processor"},
350#define PME_ITA2_BUS_RD_PRTL_ANY 159
351{
"BUS_RD_PRTL_ANY", {0x3008d}, 0xf0, 1, {0xf00000},
"Bus Read Partial Transactions -- CPU or non-CPU (all transactions)."},
352#define PME_ITA2_BUS_RD_PRTL_IO 160
353{
"BUS_RD_PRTL_IO", {0x1008d}, 0xf0, 1, {0xf00000},
"Bus Read Partial Transactions -- non-CPU priority agents"},
354#define PME_ITA2_BUS_RD_PRTL_SELF 161
355{
"BUS_RD_PRTL_SELF", {0x2008d}, 0xf0, 1, {0xf00000},
"Bus Read Partial Transactions -- local processor"},
356#define PME_ITA2_BUS_SNOOPQ_REQ 162
357{
"BUS_SNOOPQ_REQ", {0x96}, 0xf0, 7, {0xf00000},
"Bus Snoop Queue Requests"},
358#define PME_ITA2_BUS_SNOOPS_ANY 163
359{
"BUS_SNOOPS_ANY", {0x30086}, 0xf0, 1, {0xf00000},
"Bus Snoops Total -- CPU or non-CPU (all transactions)."},
360#define PME_ITA2_BUS_SNOOPS_IO 164
361{
"BUS_SNOOPS_IO", {0x10086}, 0xf0, 1, {0xf00000},
"Bus Snoops Total -- non-CPU priority agents"},
362#define PME_ITA2_BUS_SNOOPS_SELF 165
363{
"BUS_SNOOPS_SELF", {0x20086}, 0xf0, 1, {0xf00000},
"Bus Snoops Total -- local processor"},
364#define PME_ITA2_BUS_SNOOPS_HITM_ANY 166
365{
"BUS_SNOOPS_HITM_ANY", {0x30085}, 0xf0, 1, {0xf00000},
"Bus Snoops HIT Modified Cache Line -- CPU or non-CPU (all transactions)."},
366#define PME_ITA2_BUS_SNOOPS_HITM_SELF 167
367{
"BUS_SNOOPS_HITM_SELF", {0x20085}, 0xf0, 1, {0xf00000},
"Bus Snoops HIT Modified Cache Line -- local processor"},
368#define PME_ITA2_BUS_SNOOP_STALL_CYCLES_ANY 168
369{
"BUS_SNOOP_STALL_CYCLES_ANY", {0x3008f}, 0xf0, 1, {0xf00000},
"Bus Snoop Stall Cycles (from any agent) -- CPU or non-CPU (all transactions)."},
370#define PME_ITA2_BUS_SNOOP_STALL_CYCLES_SELF 169
371{
"BUS_SNOOP_STALL_CYCLES_SELF", {0x2008f}, 0xf0, 1, {0xf00000},
"Bus Snoop Stall Cycles (from any agent) -- local processor"},
372#define PME_ITA2_BUS_WR_WB_ALL_ANY 170
373{
"BUS_WR_WB_ALL_ANY", {0xf0092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- CPU or non-CPU (all transactions)."},
374#define PME_ITA2_BUS_WR_WB_ALL_IO 171
375{
"BUS_WR_WB_ALL_IO", {0xd0092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- non-CPU priority agents"},
376#define PME_ITA2_BUS_WR_WB_ALL_SELF 172
377{
"BUS_WR_WB_ALL_SELF", {0xe0092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- local processor"},
378#define PME_ITA2_BUS_WR_WB_CCASTOUT_ANY 173
379{
"BUS_WR_WB_CCASTOUT_ANY", {0xb0092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- CPU or non-CPU (all transactions)/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"},
380#define PME_ITA2_BUS_WR_WB_CCASTOUT_SELF 174
381{
"BUS_WR_WB_CCASTOUT_SELF", {0xa0092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- local processor/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"},
382#define PME_ITA2_BUS_WR_WB_EQ_128BYTE_ANY 175
383{
"BUS_WR_WB_EQ_128BYTE_ANY", {0x70092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- CPU or non-CPU (all transactions)./Only cache line transactions with write back or write coalesce attributes will be counted."},
384#define PME_ITA2_BUS_WR_WB_EQ_128BYTE_IO 176
385{
"BUS_WR_WB_EQ_128BYTE_IO", {0x50092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- non-CPU priority agents/Only cache line transactions with write back or write coalesce attributes will be counted."},
386#define PME_ITA2_BUS_WR_WB_EQ_128BYTE_SELF 177
387{
"BUS_WR_WB_EQ_128BYTE_SELF", {0x60092}, 0xf0, 1, {0xf00000},
"Bus Write Back Transactions -- local processor/Only cache line transactions with write back or write coalesce attributes will be counted."},
388#define PME_ITA2_CPU_CPL_CHANGES 178
389{
"CPU_CPL_CHANGES", {0x13}, 0xf0, 1, {0xf00000},
"Privilege Level Changes"},
390#define PME_ITA2_CPU_CYCLES 179
391{
"CPU_CYCLES", {0x12}, 0xf0, 1, {0xf00000},
"CPU Cycles"},
392#define PME_ITA2_DATA_DEBUG_REGISTER_FAULT 180
393{
"DATA_DEBUG_REGISTER_FAULT", {0x52}, 0xf0, 1, {0xf00000},
"Fault Due to Data Debug Reg. Match to Load/Store Instruction"},
394#define PME_ITA2_DATA_DEBUG_REGISTER_MATCHES 181
395{
"DATA_DEBUG_REGISTER_MATCHES", {0xc6}, 0xf0, 1, {0xf00007},
"Data Debug Register Matches Data Address of Memory Reference."},
396#define PME_ITA2_DATA_EAR_ALAT 182
397{
"DATA_EAR_ALAT", {0x6c8}, 0xf0, 1, {0xf00007},
"Data EAR ALAT"},
398#define PME_ITA2_DATA_EAR_CACHE_LAT1024 183
399{
"DATA_EAR_CACHE_LAT1024", {0x805c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 1024 Cycles"},
400#define PME_ITA2_DATA_EAR_CACHE_LAT128 184
401{
"DATA_EAR_CACHE_LAT128", {0x505c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 128 Cycles"},
402#define PME_ITA2_DATA_EAR_CACHE_LAT16 185
403{
"DATA_EAR_CACHE_LAT16", {0x205c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 16 Cycles"},
404#define PME_ITA2_DATA_EAR_CACHE_LAT2048 186
405{
"DATA_EAR_CACHE_LAT2048", {0x905c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 2048 Cycles"},
406#define PME_ITA2_DATA_EAR_CACHE_LAT256 187
407{
"DATA_EAR_CACHE_LAT256", {0x605c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 256 Cycles"},
408#define PME_ITA2_DATA_EAR_CACHE_LAT32 188
409{
"DATA_EAR_CACHE_LAT32", {0x305c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 32 Cycles"},
410#define PME_ITA2_DATA_EAR_CACHE_LAT4 189
411{
"DATA_EAR_CACHE_LAT4", {0x5c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 4 Cycles"},
412#define PME_ITA2_DATA_EAR_CACHE_LAT4096 190
413{
"DATA_EAR_CACHE_LAT4096", {0xa05c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 4096 Cycles"},
414#define PME_ITA2_DATA_EAR_CACHE_LAT512 191
415{
"DATA_EAR_CACHE_LAT512", {0x705c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 512 Cycles"},
416#define PME_ITA2_DATA_EAR_CACHE_LAT64 192
417{
"DATA_EAR_CACHE_LAT64", {0x405c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 64 Cycles"},
418#define PME_ITA2_DATA_EAR_CACHE_LAT8 193
419{
"DATA_EAR_CACHE_LAT8", {0x105c8}, 0xf0, 1, {0xf00007},
"Data EAR Cache -- >= 8 Cycles"},
420#define PME_ITA2_DATA_EAR_EVENTS 194
421{
"DATA_EAR_EVENTS", {0xc8}, 0xf0, 1, {0xf00007},
"L1 Data Cache EAR Events"},
422#define PME_ITA2_DATA_EAR_TLB_ALL 195
423{
"DATA_EAR_TLB_ALL", {0xe04c8}, 0xf0, 1, {0xf00007},
"Data EAR TLB -- All L1 DTLB Misses"},
424#define PME_ITA2_DATA_EAR_TLB_FAULT 196
425{
"DATA_EAR_TLB_FAULT", {0x804c8}, 0xf0, 1, {0xf00007},
"Data EAR TLB -- DTLB Misses which produce a software fault"},
426#define PME_ITA2_DATA_EAR_TLB_L2DTLB 197
427{
"DATA_EAR_TLB_L2DTLB", {0x204c8}, 0xf0, 1, {0xf00007},
"Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB"},
428#define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_FAULT 198
429{
"DATA_EAR_TLB_L2DTLB_OR_FAULT", {0xa04c8}, 0xf0, 1, {0xf00007},
"Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or produce a software fault"},
430#define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_VHPT 199
431{
"DATA_EAR_TLB_L2DTLB_OR_VHPT", {0x604c8}, 0xf0, 1, {0xf00007},
"Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or VHPT"},
432#define PME_ITA2_DATA_EAR_TLB_VHPT 200
433{
"DATA_EAR_TLB_VHPT", {0x404c8}, 0xf0, 1, {0xf00007},
"Data EAR TLB -- L1 DTLB Misses which hit VHPT"},
434#define PME_ITA2_DATA_EAR_TLB_VHPT_OR_FAULT 201
435{
"DATA_EAR_TLB_VHPT_OR_FAULT", {0xc04c8}, 0xf0, 1, {0xf00007},
"Data EAR TLB -- L1 DTLB Misses which hit VHPT or produce a software fault"},
436#define PME_ITA2_DATA_REFERENCES_SET0 202
437{
"DATA_REFERENCES_SET0", {0xc3}, 0xf0, 4, {0x5010007},
"Data Memory References Issued to Memory Pipeline"},
438#define PME_ITA2_DATA_REFERENCES_SET1 203
439{
"DATA_REFERENCES_SET1", {0xc5}, 0xf0, 4, {0x5110007},
"Data Memory References Issued to Memory Pipeline"},
440#define PME_ITA2_DISP_STALLED 204
441{
"DISP_STALLED", {0x49}, 0xf0, 1, {0xf00000},
"Number of Cycles Dispersal Stalled"},
442#define PME_ITA2_DTLB_INSERTS_HPW 205
443{
"DTLB_INSERTS_HPW", {0xc9}, 0xf0, 4, {0xf00007},
"Hardware Page Walker Installs to DTLB"},
444#define PME_ITA2_DTLB_INSERTS_HPW_RETIRED 206
445{
"DTLB_INSERTS_HPW_RETIRED", {0x2c}, 0xf0, 4, {0xf00007},
"VHPT Entries Inserted into DTLB by the Hardware Page Walker"},
446#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 207
447{
"ENCBR_MISPRED_DETAIL_ALL_ALL_PRED", {0x63}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- All encoded branches regardless of prediction result"},
448#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 208
449{
"ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x10063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- All encoded branches, correctly predicted branches (outcome and target)"},
450#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 209
451{
"ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x20063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong branch direction"},
452#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 210
453{
"ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x30063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong target for taken branches"},
454#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 211
455{
"ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED", {0xc0063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only non-return indirect branches, regardless of prediction result"},
456#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 212
457{
"ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED", {0xd0063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only non-return indirect branches, correctly predicted branches (outcome and target)"},
458#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 213
459{
"ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH", {0xe0063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"},
460#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 214
461{
"ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET", {0xf0063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"},
462#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 215
463{
"ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED", {0x80063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only return type branches, regardless of prediction result"},
464#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 216
465{
"ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED", {0x90063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only return type branches, correctly predicted branches (outcome and target)"},
466#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 217
467{
"ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH", {0xa0063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong branch direction"},
468#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 218
469{
"ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET", {0xb0063}, 0xf0, 3, {0xf00003},
"Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong target for taken branches"},
470#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_ALL 219
471{
"EXTERN_DP_PINS_0_TO_3_ALL", {0xf009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin3 assertion"},
472#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0 220
473{
"EXTERN_DP_PINS_0_TO_3_PIN0", {0x1009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin0 assertion"},
474#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1 221
475{
"EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1", {0x3009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin0 or pin1 assertion"},
476#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2 222
477{
"EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2", {0x7009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin0 or pin1 or pin2 assertion"},
478#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3 223
479{
"EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3", {0xb009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin0 or pin1 or pin3 assertion"},
480#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2 224
481{
"EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2", {0x5009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin0 or pin2 assertion"},
482#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3 225
483{
"EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3", {0xd009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin0 or pin2 or pin3 assertion"},
484#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3 226
485{
"EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3", {0x9009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin0 or pin3 assertion"},
486#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1 227
487{
"EXTERN_DP_PINS_0_TO_3_PIN1", {0x2009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin1 assertion"},
488#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2 228
489{
"EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2", {0x6009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin1 or pin2 assertion"},
490#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3 229
491{
"EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3", {0xe009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin1 or pin2 or pin3 assertion"},
492#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3 230
493{
"EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3", {0xa009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin1 or pin3 assertion"},
494#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2 231
495{
"EXTERN_DP_PINS_0_TO_3_PIN2", {0x4009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin2 assertion"},
496#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3 232
497{
"EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3", {0xc009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin2 or pin3 assertion"},
498#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN3 233
499{
"EXTERN_DP_PINS_0_TO_3_PIN3", {0x8009e}, 0xf0, 1, {0xf00000},
"DP Pins 0-3 Asserted -- include pin3 assertion"},
500#define PME_ITA2_EXTERN_DP_PINS_4_TO_5_ALL 234
501{
"EXTERN_DP_PINS_4_TO_5_ALL", {0x3009f}, 0xf0, 1, {0xf00000},
"DP Pins 4-5 Asserted -- include pin5 assertion"},
502#define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN4 235
503{
"EXTERN_DP_PINS_4_TO_5_PIN4", {0x1009f}, 0xf0, 1, {0xf00000},
"DP Pins 4-5 Asserted -- include pin4 assertion"},
504#define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN5 236
505{
"EXTERN_DP_PINS_4_TO_5_PIN5", {0x2009f}, 0xf0, 1, {0xf00000},
"DP Pins 4-5 Asserted -- include pin5 assertion"},
506#define PME_ITA2_FE_BUBBLE_ALL 237
507{
"FE_BUBBLE_ALL", {0x71}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- count regardless of cause"},
508#define PME_ITA2_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 238
509{
"FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE", {0xb0071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- ALL except FEFLUSH and BUBBLE"},
510#define PME_ITA2_FE_BUBBLE_ALLBUT_IBFULL 239
511{
"FE_BUBBLE_ALLBUT_IBFULL", {0xc0071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- ALL except IBFULl"},
512#define PME_ITA2_FE_BUBBLE_BRANCH 240
513{
"FE_BUBBLE_BRANCH", {0x90071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- only if caused by any of 4 branch recirculates"},
514#define PME_ITA2_FE_BUBBLE_BUBBLE 241
515{
"FE_BUBBLE_BUBBLE", {0xd0071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- only if caused by branch bubble stall"},
516#define PME_ITA2_FE_BUBBLE_FEFLUSH 242
517{
"FE_BUBBLE_FEFLUSH", {0x10071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- only if caused by a front-end flush"},
518#define PME_ITA2_FE_BUBBLE_FILL_RECIRC 243
519{
"FE_BUBBLE_FILL_RECIRC", {0x80071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- only if caused by a recirculate for a cache line fill operation"},
520#define PME_ITA2_FE_BUBBLE_GROUP1 244
521{
"FE_BUBBLE_GROUP1", {0x30071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- BUBBLE or BRANCH"},
522#define PME_ITA2_FE_BUBBLE_GROUP2 245
523{
"FE_BUBBLE_GROUP2", {0x40071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- IMISS or TLBMISS"},
524#define PME_ITA2_FE_BUBBLE_GROUP3 246
525{
"FE_BUBBLE_GROUP3", {0xa0071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- FILL_RECIRC or BRANCH"},
526#define PME_ITA2_FE_BUBBLE_IBFULL 247
527{
"FE_BUBBLE_IBFULL", {0x50071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- only if caused by instruction buffer full stall"},
528#define PME_ITA2_FE_BUBBLE_IMISS 248
529{
"FE_BUBBLE_IMISS", {0x60071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- only if caused by instruction cache miss stall"},
530#define PME_ITA2_FE_BUBBLE_TLBMISS 249
531{
"FE_BUBBLE_TLBMISS", {0x70071}, 0xf0, 1, {0xf00000},
"Bubbles Seen by FE -- only if caused by TLB stall"},
532#define PME_ITA2_FE_LOST_BW_ALL 250
533{
"FE_LOST_BW_ALL", {0x70}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- count regardless of cause"},
534#define PME_ITA2_FE_LOST_BW_BI 251
535{
"FE_LOST_BW_BI", {0x90070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by branch initialization stall"},
536#define PME_ITA2_FE_LOST_BW_BRQ 252
537{
"FE_LOST_BW_BRQ", {0xa0070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by branch retirement queue stall"},
538#define PME_ITA2_FE_LOST_BW_BR_ILOCK 253
539{
"FE_LOST_BW_BR_ILOCK", {0xc0070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by branch interlock stall"},
540#define PME_ITA2_FE_LOST_BW_BUBBLE 254
541{
"FE_LOST_BW_BUBBLE", {0xd0070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by branch resteer bubble stall"},
542#define PME_ITA2_FE_LOST_BW_FEFLUSH 255
543{
"FE_LOST_BW_FEFLUSH", {0x10070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by a front-end flush"},
544#define PME_ITA2_FE_LOST_BW_FILL_RECIRC 256
545{
"FE_LOST_BW_FILL_RECIRC", {0x80070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by a recirculate for a cache line fill operation"},
546#define PME_ITA2_FE_LOST_BW_IBFULL 257
547{
"FE_LOST_BW_IBFULL", {0x50070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by instruction buffer full stall"},
548#define PME_ITA2_FE_LOST_BW_IMISS 258
549{
"FE_LOST_BW_IMISS", {0x60070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by instruction cache miss stall"},
550#define PME_ITA2_FE_LOST_BW_PLP 259
551{
"FE_LOST_BW_PLP", {0xb0070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by perfect loop prediction stall"},
552#define PME_ITA2_FE_LOST_BW_TLBMISS 260
553{
"FE_LOST_BW_TLBMISS", {0x70070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by TLB stall"},
554#define PME_ITA2_FE_LOST_BW_UNREACHED 261
555{
"FE_LOST_BW_UNREACHED", {0x40070}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Entrance to IB -- only if caused by unreachable bundle"},
556#define PME_ITA2_FP_FAILED_FCHKF 262
557{
"FP_FAILED_FCHKF", {0x6}, 0xf0, 1, {0xf00001},
"Failed fchkf"},
558#define PME_ITA2_FP_FALSE_SIRSTALL 263
559{
"FP_FALSE_SIRSTALL", {0x5}, 0xf0, 1, {0xf00001},
"SIR Stall Without a Trap"},
560#define PME_ITA2_FP_FLUSH_TO_ZERO 264
561{
"FP_FLUSH_TO_ZERO", {0xb}, 0xf0, 2, {0xf00001},
"FP Result Flushed to Zero"},
562#define PME_ITA2_FP_OPS_RETIRED 265
563{
"FP_OPS_RETIRED", {0x9}, 0xf0, 4, {0xf00001},
"Retired FP Operations"},
564#define PME_ITA2_FP_TRUE_SIRSTALL 266
565{
"FP_TRUE_SIRSTALL", {0x3}, 0xf0, 1, {0xf00001},
"SIR stall asserted and leads to a trap"},
566#define PME_ITA2_HPW_DATA_REFERENCES 267
567{
"HPW_DATA_REFERENCES", {0x2d}, 0xf0, 4, {0xf00007},
"Data Memory References to VHPT"},
568#define PME_ITA2_IA32_INST_RETIRED 268
569{
"IA32_INST_RETIRED", {0x59}, 0xf0, 2, {0xf00000},
"IA-32 Instructions Retired"},
570#define PME_ITA2_IA32_ISA_TRANSITIONS 269
571{
"IA32_ISA_TRANSITIONS", {0x7}, 0xf0, 1, {0xf00000},
"IA-64 to/from IA-32 ISA Transitions"},
572#define PME_ITA2_IA64_INST_RETIRED 270
573{
"IA64_INST_RETIRED", {0x8}, 0xf0, 6, {0xf00003},
"Retired IA-64 Instructions, alias to IA64_INST_RETIRED_THIS"},
574#define PME_ITA2_IA64_INST_RETIRED_THIS 271
575{
"IA64_INST_RETIRED_THIS", {0x8}, 0xf0, 6, {0xf00003},
"Retired IA-64 Instructions -- Retired IA-64 Instructions"},
576#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8 272
577{
"IA64_TAGGED_INST_RETIRED_IBRP0_PMC8", {0x8}, 0xf0, 6, {0xf00003},
"Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 0 and opcode matcher PMC8. Code executed with PSR.is=1 is included."},
578#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9 273
579{
"IA64_TAGGED_INST_RETIRED_IBRP1_PMC9", {0x10008}, 0xf0, 6, {0xf00003},
"Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 1 and opcode matcher PMC9. Code executed with PSR.is=1 is included."},
580#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8 274
581{
"IA64_TAGGED_INST_RETIRED_IBRP2_PMC8", {0x20008}, 0xf0, 6, {0xf00003},
"Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 2 and opcode matcher PMC8. Code executed with PSR.is=1 is not included."},
582#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9 275
583{
"IA64_TAGGED_INST_RETIRED_IBRP3_PMC9", {0x30008}, 0xf0, 6, {0xf00003},
"Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 3 and opcode matcher PMC9. Code executed with PSR.is=1 is not included."},
584#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 276
585{
"IDEAL_BE_LOST_BW_DUE_TO_FE_ALL", {0x73}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- count regardless of cause"},
586#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 277
587{
"IDEAL_BE_LOST_BW_DUE_TO_FE_BI", {0x90073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by branch initialization stall"},
588#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 278
589{
"IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by branch retirement queue stall"},
590#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 279
591{
"IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by branch interlock stall"},
592#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 280
593{
"IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by branch resteer bubble stall"},
594#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 281
595{
"IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by a front-end flush"},
596#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 282
597{
"IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by a recirculate for a cache line fill operation"},
598#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 283
599{
"IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- (* meaningless for this event *)"},
600#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 284
601{
"IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS", {0x60073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by instruction cache miss stall"},
602#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 285
603{
"IDEAL_BE_LOST_BW_DUE_TO_FE_PLP", {0xb0073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by perfect loop prediction stall"},
604#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 286
605{
"IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by TLB stall"},
606#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 287
607{
"IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40073}, 0xf0, 2, {0xf00000},
"Invalid Bundles at the Exit from IB -- only if caused by unreachable bundle"},
608#define PME_ITA2_INST_CHKA_LDC_ALAT_ALL 288
609{
"INST_CHKA_LDC_ALAT_ALL", {0x30056}, 0xf0, 2, {0xf00007},
"Retired chk.a and ld.c Instructions -- both integer and floating point instructions"},
610#define PME_ITA2_INST_CHKA_LDC_ALAT_FP 289
611{
"INST_CHKA_LDC_ALAT_FP", {0x20056}, 0xf0, 2, {0xf00007},
"Retired chk.a and ld.c Instructions -- only floating point instructions"},
612#define PME_ITA2_INST_CHKA_LDC_ALAT_INT 290
613{
"INST_CHKA_LDC_ALAT_INT", {0x10056}, 0xf0, 2, {0xf00007},
"Retired chk.a and ld.c Instructions -- only integer instructions"},
614#define PME_ITA2_INST_DISPERSED 291
615{
"INST_DISPERSED", {0x4d}, 0xf0, 6, {0xf00001},
"Syllables Dispersed from REN to REG stage"},
616#define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_ALL 292
617{
"INST_FAILED_CHKA_LDC_ALAT_ALL", {0x30057}, 0xf0, 1, {0xf00007},
"Failed chk.a and ld.c Instructions -- both integer and floating point instructions"},
618#define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_FP 293
619{
"INST_FAILED_CHKA_LDC_ALAT_FP", {0x20057}, 0xf0, 1, {0xf00007},
"Failed chk.a and ld.c Instructions -- only floating point instructions"},
620#define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_INT 294
621{
"INST_FAILED_CHKA_LDC_ALAT_INT", {0x10057}, 0xf0, 1, {0xf00007},
"Failed chk.a and ld.c Instructions -- only integer instructions"},
622#define PME_ITA2_INST_FAILED_CHKS_RETIRED_ALL 295
623{
"INST_FAILED_CHKS_RETIRED_ALL", {0x30055}, 0xf0, 1, {0xf00000},
"Failed chk.s Instructions -- both integer and floating point instructions"},
624#define PME_ITA2_INST_FAILED_CHKS_RETIRED_FP 296
625{
"INST_FAILED_CHKS_RETIRED_FP", {0x20055}, 0xf0, 1, {0xf00000},
"Failed chk.s Instructions -- only floating point instructions"},
626#define PME_ITA2_INST_FAILED_CHKS_RETIRED_INT 297
627{
"INST_FAILED_CHKS_RETIRED_INT", {0x10055}, 0xf0, 1, {0xf00000},
"Failed chk.s Instructions -- only integer instructions"},
628#define PME_ITA2_ISB_BUNPAIRS_IN 298
629{
"ISB_BUNPAIRS_IN", {0x46}, 0xf0, 1, {0xf00001},
"Bundle Pairs Written from L2 into FE"},
630#define PME_ITA2_ITLB_MISSES_FETCH_ALL 299
631{
"ITLB_MISSES_FETCH_ALL", {0x30047}, 0xf0, 1, {0xf00001},
"ITLB Misses Demand Fetch -- All tlb misses will be counted. Note that this is not equal to sum of the L1ITLB and L2ITLB umasks because any access could be a miss in L1ITLB and L2ITLB."},
632#define PME_ITA2_ITLB_MISSES_FETCH_L1ITLB 300
633{
"ITLB_MISSES_FETCH_L1ITLB", {0x10047}, 0xf0, 1, {0xf00001},
"ITLB Misses Demand Fetch -- All misses in L1ITLB will be counted. even if L1ITLB is not updated for an access (Uncacheable/nat page/not present page/faulting/some flushed), it will be counted here."},
634#define PME_ITA2_ITLB_MISSES_FETCH_L2ITLB 301
635{
"ITLB_MISSES_FETCH_L2ITLB", {0x20047}, 0xf0, 1, {0xf00001},
"ITLB Misses Demand Fetch -- All misses in L1ITLB which also missed in L2ITLB will be counted."},
636#define PME_ITA2_L1DTLB_TRANSFER 302
637{
"L1DTLB_TRANSFER", {0xc0}, 0xf0, 1, {0x5010007},
"L1DTLB Misses That Hit in the L2DTLB for Accesses Counted in L1D_READS"},
638#define PME_ITA2_L1D_READS_SET0 303
639{
"L1D_READS_SET0", {0xc2}, 0xf0, 2, {0x5010007},
"L1 Data Cache Reads"},
640#define PME_ITA2_L1D_READS_SET1 304
641{
"L1D_READS_SET1", {0xc4}, 0xf0, 2, {0x5110007},
"L1 Data Cache Reads"},
642#define PME_ITA2_L1D_READ_MISSES_ALL 305
643{
"L1D_READ_MISSES_ALL", {0xc7}, 0xf0, 2, {0x5110007},
"L1 Data Cache Read Misses -- all L1D read misses will be counted."},
644#define PME_ITA2_L1D_READ_MISSES_RSE_FILL 306
645{
"L1D_READ_MISSES_RSE_FILL", {0x100c7}, 0xf0, 2, {0x5110007},
"L1 Data Cache Read Misses -- only L1D read misses caused by RSE fills will be counted"},
646#define PME_ITA2_L1ITLB_INSERTS_HPW 307
647{
"L1ITLB_INSERTS_HPW", {0x48}, 0xf0, 1, {0xf00001},
"L1ITLB Hardware Page Walker Inserts"},
648#define PME_ITA2_L1I_EAR_CACHE_LAT0 308
649{
"L1I_EAR_CACHE_LAT0", {0x400343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- > 0 Cycles (All L1 Misses)"},
650#define PME_ITA2_L1I_EAR_CACHE_LAT1024 309
651{
"L1I_EAR_CACHE_LAT1024", {0xc00343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 1024 Cycles"},
652#define PME_ITA2_L1I_EAR_CACHE_LAT128 310
653{
"L1I_EAR_CACHE_LAT128", {0xf00343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 128 Cycles"},
654#define PME_ITA2_L1I_EAR_CACHE_LAT16 311
655{
"L1I_EAR_CACHE_LAT16", {0xfc0343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 16 Cycles"},
656#define PME_ITA2_L1I_EAR_CACHE_LAT256 312
657{
"L1I_EAR_CACHE_LAT256", {0xe00343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 256 Cycles"},
658#define PME_ITA2_L1I_EAR_CACHE_LAT32 313
659{
"L1I_EAR_CACHE_LAT32", {0xf80343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 32 Cycles"},
660#define PME_ITA2_L1I_EAR_CACHE_LAT4 314
661{
"L1I_EAR_CACHE_LAT4", {0xff0343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 4 Cycles"},
662#define PME_ITA2_L1I_EAR_CACHE_LAT4096 315
663{
"L1I_EAR_CACHE_LAT4096", {0x800343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 4096 Cycles"},
664#define PME_ITA2_L1I_EAR_CACHE_LAT8 316
665{
"L1I_EAR_CACHE_LAT8", {0xfe0343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- >= 8 Cycles"},
666#define PME_ITA2_L1I_EAR_CACHE_RAB 317
667{
"L1I_EAR_CACHE_RAB", {0x343}, 0xf0, 1, {0xf00001},
"L1I EAR Cache -- RAB HIT"},
668#define PME_ITA2_L1I_EAR_EVENTS 318
669{
"L1I_EAR_EVENTS", {0x43}, 0xf0, 1, {0xf00001},
"Instruction EAR Events"},
670#define PME_ITA2_L1I_EAR_TLB_ALL 319
671{
"L1I_EAR_TLB_ALL", {0x70243}, 0xf0, 1, {0xf00001},
"L1I EAR TLB -- All L1 ITLB Misses"},
672#define PME_ITA2_L1I_EAR_TLB_FAULT 320
673{
"L1I_EAR_TLB_FAULT", {0x40243}, 0xf0, 1, {0xf00001},
"L1I EAR TLB -- ITLB Misses which produced a fault"},
674#define PME_ITA2_L1I_EAR_TLB_L2TLB 321
675{
"L1I_EAR_TLB_L2TLB", {0x10243}, 0xf0, 1, {0xf00001},
"L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB"},
676#define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_FAULT 322
677{
"L1I_EAR_TLB_L2TLB_OR_FAULT", {0x50243}, 0xf0, 1, {0xf00001},
"L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or produce a software fault"},
678#define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_VHPT 323
679{
"L1I_EAR_TLB_L2TLB_OR_VHPT", {0x30243}, 0xf0, 1, {0xf00001},
"L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or VHPT"},
680#define PME_ITA2_L1I_EAR_TLB_VHPT 324
681{
"L1I_EAR_TLB_VHPT", {0x20243}, 0xf0, 1, {0xf00001},
"L1I EAR TLB -- L1 ITLB Misses which hit VHPT"},
682#define PME_ITA2_L1I_EAR_TLB_VHPT_OR_FAULT 325
683{
"L1I_EAR_TLB_VHPT_OR_FAULT", {0x60243}, 0xf0, 1, {0xf00001},
"L1I EAR TLB -- L1 ITLB Misses which hit VHPT or produce a software fault"},
684#define PME_ITA2_L1I_FETCH_ISB_HIT 326
685{
"L1I_FETCH_ISB_HIT", {0x66}, 0xf0, 1, {0xf00001},
"\"Just-In-Time\" Instruction Fetch Hitting in and Being Bypassed from ISB"},
686#define PME_ITA2_L1I_FETCH_RAB_HIT 327
687{
"L1I_FETCH_RAB_HIT", {0x65}, 0xf0, 1, {0xf00001},
"Instruction Fetch Hitting in RAB"},
688#define PME_ITA2_L1I_FILLS 328
689{
"L1I_FILLS", {0x41}, 0xf0, 1, {0xf00001},
"L1 Instruction Cache Fills"},
690#define PME_ITA2_L1I_PREFETCHES 329
691{
"L1I_PREFETCHES", {0x44}, 0xf0, 1, {0xf00001},
"L1 Instruction Prefetch Requests"},
692#define PME_ITA2_L1I_PREFETCH_STALL_ALL 330
693{
"L1I_PREFETCH_STALL_ALL", {0x30067}, 0xf0, 1, {0xf00000},
"Prefetch Pipeline Stalls -- Number of clocks prefetch pipeline is stalled"},
694#define PME_ITA2_L1I_PREFETCH_STALL_FLOW 331
695{
"L1I_PREFETCH_STALL_FLOW", {0x20067}, 0xf0, 1, {0xf00000},
"Prefetch Pipeline Stalls -- Number of clocks flow is not asserted"},
696#define PME_ITA2_L1I_PURGE 332
697{
"L1I_PURGE", {0x4b}, 0xf0, 1, {0xf00001},
"L1ITLB Purges Handled by L1I"},
698#define PME_ITA2_L1I_PVAB_OVERFLOW 333
699{
"L1I_PVAB_OVERFLOW", {0x69}, 0xf0, 1, {0xf00000},
"PVAB Overflow"},
700#define PME_ITA2_L1I_RAB_ALMOST_FULL 334
701{
"L1I_RAB_ALMOST_FULL", {0x64}, 0xf0, 1, {0xf00000},
"Is RAB Almost Full?"},
702#define PME_ITA2_L1I_RAB_FULL 335
703{
"L1I_RAB_FULL", {0x60}, 0xf0, 1, {0xf00000},
"Is RAB Full?"},
704#define PME_ITA2_L1I_READS 336
705{
"L1I_READS", {0x40}, 0xf0, 1, {0xf00001},
"L1 Instruction Cache Reads"},
706#define PME_ITA2_L1I_SNOOP 337
707{
"L1I_SNOOP", {0x4a}, 0xf0, 1, {0xf00007},
"Snoop Requests Handled by L1I"},
708#define PME_ITA2_L1I_STRM_PREFETCHES 338
709{
"L1I_STRM_PREFETCHES", {0x5f}, 0xf0, 1, {0xf00001},
"L1 Instruction Cache Line Prefetch Requests"},
710#define PME_ITA2_L2DTLB_MISSES 339
711{
"L2DTLB_MISSES", {0xc1}, 0xf0, 4, {0x5010007},
"L2DTLB Misses"},
712#define PME_ITA2_L2_BAD_LINES_SELECTED_ANY 340
713{
"L2_BAD_LINES_SELECTED_ANY", {0xb9}, 0xf0, 4, {0x4320007},
"Valid Line Replaced When Invalid Line Is Available -- Valid line replaced when invalid line is available"},
714#define PME_ITA2_L2_BYPASS_L2_DATA1 341
715{
"L2_BYPASS_L2_DATA1", {0xb8}, 0xf0, 1, {0x4320007},
"Count L2 Bypasses -- Count only L2 data bypasses (L1D to L2A)"},
716#define PME_ITA2_L2_BYPASS_L2_DATA2 342
717{
"L2_BYPASS_L2_DATA2", {0x100b8}, 0xf0, 1, {0x4320007},
"Count L2 Bypasses -- Count only L2 data bypasses (L1W to L2I)"},
718#define PME_ITA2_L2_BYPASS_L2_INST1 343
719{
"L2_BYPASS_L2_INST1", {0x400b8}, 0xf0, 1, {0x4320007},
"Count L2 Bypasses -- Count only L2 instruction bypasses (L1D to L2A)"},
720#define PME_ITA2_L2_BYPASS_L2_INST2 344
721{
"L2_BYPASS_L2_INST2", {0x500b8}, 0xf0, 1, {0x4320007},
"Count L2 Bypasses -- Count only L2 instruction bypasses (L1W to L2I)"},
722#define PME_ITA2_L2_BYPASS_L3_DATA1 345
723{
"L2_BYPASS_L3_DATA1", {0x200b8}, 0xf0, 1, {0x4320007},
"Count L2 Bypasses -- Count only L3 data bypasses (L1D to L2A)"},
724#define PME_ITA2_L2_BYPASS_L3_INST1 346
725{
"L2_BYPASS_L3_INST1", {0x600b8}, 0xf0, 1, {0x4320007},
"Count L2 Bypasses -- Count only L3 instruction bypasses (L1D to L2A)"},
726#define PME_ITA2_L2_DATA_REFERENCES_L2_ALL 347
727{
"L2_DATA_REFERENCES_L2_ALL", {0x300b2}, 0xf0, 4, {0x4120007},
"Data Read/Write Access to L2 -- count both read and write operations (semaphores will count as 2)"},
728#define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_READS 348
729{
"L2_DATA_REFERENCES_L2_DATA_READS", {0x100b2}, 0xf0, 4, {0x4120007},
"Data Read/Write Access to L2 -- count only data read and semaphore operations."},
730#define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_WRITES 349
731{
"L2_DATA_REFERENCES_L2_DATA_WRITES", {0x200b2}, 0xf0, 4, {0x4120007},
"Data Read/Write Access to L2 -- count only data write and semaphore operations"},
732#define PME_ITA2_L2_FILLB_FULL_THIS 350
733{
"L2_FILLB_FULL_THIS", {0xbf}, 0xf0, 1, {0x4520000},
"L2D Fill Buffer Is Full -- L2 Fill buffer is full"},
734#define PME_ITA2_L2_FORCE_RECIRC_ANY 351
735{
"L2_FORCE_RECIRC_ANY", {0xb4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count forced recirculates regardless of cause. SMC_HIT, TRAN_PREF & SNP_OR_L3 will not be included here."},
736#define PME_ITA2_L2_FORCE_RECIRC_FILL_HIT 352
737{
"L2_FORCE_RECIRC_FILL_HIT", {0x900b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by an L2 miss which hit in the fill buffer."},
738#define PME_ITA2_L2_FORCE_RECIRC_FRC_RECIRC 353
739{
"L2_FORCE_RECIRC_FRC_RECIRC", {0xe00b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- caused by an L2 miss when a force recirculate already existed"},
740#define PME_ITA2_L2_FORCE_RECIRC_IPF_MISS 354
741{
"L2_FORCE_RECIRC_IPF_MISS", {0xa00b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- caused by L2 miss when instruction prefetch buffer miss already existed"},
742#define PME_ITA2_L2_FORCE_RECIRC_L1W 355
743{
"L2_FORCE_RECIRC_L1W", {0x200b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by forced limbo"},
744#define PME_ITA2_L2_FORCE_RECIRC_OZQ_MISS 356
745{
"L2_FORCE_RECIRC_OZQ_MISS", {0xc00b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- caused by an L2 miss when an OZQ miss already existed"},
746#define PME_ITA2_L2_FORCE_RECIRC_SAME_INDEX 357
747{
"L2_FORCE_RECIRC_SAME_INDEX", {0xd00b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- caused by an L2 miss when a miss to the same index already existed"},
748#define PME_ITA2_L2_FORCE_RECIRC_SMC_HIT 358
749{
"L2_FORCE_RECIRC_SMC_HIT", {0x100b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by SMC hits due to an ifetch and load to same cache line or a pending WT store"},
750#define PME_ITA2_L2_FORCE_RECIRC_SNP_OR_L3 359
751{
"L2_FORCE_RECIRC_SNP_OR_L3", {0x600b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by a snoop or L3 issue"},
752#define PME_ITA2_L2_FORCE_RECIRC_TAG_NOTOK 360
753{
"L2_FORCE_RECIRC_TAG_NOTOK", {0x400b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by L2 hits caused by in flight snoops, stores with a sibling miss to the same index, sibling probe to the same line or pending sync.ia instructions."},
754#define PME_ITA2_L2_FORCE_RECIRC_TRAN_PREF 361
755{
"L2_FORCE_RECIRC_TRAN_PREF", {0x500b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by transforms to prefetches"},
756#define PME_ITA2_L2_FORCE_RECIRC_VIC_BUF_FULL 362
757{
"L2_FORCE_RECIRC_VIC_BUF_FULL", {0xb00b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by an L2 miss with victim buffer full"},
758#define PME_ITA2_L2_FORCE_RECIRC_VIC_PEND 363
759{
"L2_FORCE_RECIRC_VIC_PEND", {0x800b4}, 0x10, 4, {0x4220007},
"Forced Recirculates -- count only those caused by an L2 miss with pending victim"},
760#define PME_ITA2_L2_GOT_RECIRC_IFETCH_ANY 364
761{
"L2_GOT_RECIRC_IFETCH_ANY", {0x800ba}, 0xf0, 1, {0x4420007},
"Instruction Fetch Recirculates Received by L2D -- Instruction fetch recirculates received by L2"},
762#define PME_ITA2_L2_GOT_RECIRC_OZQ_ACC 365
763{
"L2_GOT_RECIRC_OZQ_ACC", {0xb6}, 0xf0, 1, {0x4220007},
"Counts Number of OZQ Accesses Recirculated to L1D"},
764#define PME_ITA2_L2_IFET_CANCELS_ANY 366
765{
"L2_IFET_CANCELS_ANY", {0xa1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- total instruction fetch cancels by L2"},
766#define PME_ITA2_L2_IFET_CANCELS_BYPASS 367
767{
"L2_IFET_CANCELS_BYPASS", {0x200a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- ifetch cancels due to bypassing"},
768#define PME_ITA2_L2_IFET_CANCELS_CHG_PRIO 368
769{
"L2_IFET_CANCELS_CHG_PRIO", {0xc00a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- ifetch cancels due to change priority"},
770#define PME_ITA2_L2_IFET_CANCELS_DATA_RD 369
771{
"L2_IFET_CANCELS_DATA_RD", {0x700a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- ifetch/prefetch cancels due to a data read"},
772#define PME_ITA2_L2_IFET_CANCELS_DIDNT_RECIR 370
773{
"L2_IFET_CANCELS_DIDNT_RECIR", {0x400a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- ifetch cancels because it did not recirculate"},
774#define PME_ITA2_L2_IFET_CANCELS_IFETCH_BYP 371
775{
"L2_IFET_CANCELS_IFETCH_BYP", {0xd00a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- due to ifetch bypass during last clock"},
776#define PME_ITA2_L2_IFET_CANCELS_PREEMPT 372
777{
"L2_IFET_CANCELS_PREEMPT", {0x800a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- ifetch cancels due to preempts"},
778#define PME_ITA2_L2_IFET_CANCELS_RECIR_OVER_SUB 373
779{
"L2_IFET_CANCELS_RECIR_OVER_SUB", {0x500a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- ifetch cancels because of recirculate oversubscription"},
780#define PME_ITA2_L2_IFET_CANCELS_ST_FILL_WB 374
781{
"L2_IFET_CANCELS_ST_FILL_WB", {0x600a1}, 0xf0, 1, {0x4020007},
"Instruction Fetch Cancels by the L2 -- ifetch cancels due to a store or fill or write back"},
782#define PME_ITA2_L2_INST_DEMAND_READS 375
783{
"L2_INST_DEMAND_READS", {0x42}, 0xf0, 1, {0xf00001},
"L2 Instruction Demand Fetch Requests"},
784#define PME_ITA2_L2_INST_PREFETCHES 376
785{
"L2_INST_PREFETCHES", {0x45}, 0xf0, 1, {0xf00001},
"L2 Instruction Prefetch Requests"},
786#define PME_ITA2_L2_ISSUED_RECIRC_IFETCH_ANY 377
787{
"L2_ISSUED_RECIRC_IFETCH_ANY", {0x800b9}, 0xf0, 1, {0x4420007},
"Instruction Fetch Recirculates Issued by L2 -- Instruction fetch recirculates issued by L2"},
788#define PME_ITA2_L2_ISSUED_RECIRC_OZQ_ACC 378
789{
"L2_ISSUED_RECIRC_OZQ_ACC", {0xb5}, 0xf0, 1, {0x4220007},
"Count Number of Times a Recirculate Issue Was Attempted and Not Preempted"},
790#define PME_ITA2_L2_L3ACCESS_CANCEL_ANY 379
791{
"L2_L3ACCESS_CANCEL_ANY", {0x900b0}, 0x10, 1, {0x4120007},
"Canceled L3 Accesses -- count cancels due to any reason. This umask will count more than the sum of all the other umasks. It will count things that weren't committed accesses when they reached L1w, but the L2 attempted to bypass them to the L3 anyway (speculatively). This will include accesses made repeatedly while the main pipeline is stalled and the L1d is attempting to recirculate an access down the L1d pipeline. Thus, an access could get counted many times before it really does get bypassed to the L3. It is a measure of how many times we asserted a request to the L3 but didn't confirm it."},
792#define PME_ITA2_L2_L3ACCESS_CANCEL_DFETCH 380
793{
"L2_L3ACCESS_CANCEL_DFETCH", {0xa00b0}, 0x10, 1, {0x4120007},
"Canceled L3 Accesses -- data fetches"},
794#define PME_ITA2_L2_L3ACCESS_CANCEL_EBL_REJECT 381
795{
"L2_L3ACCESS_CANCEL_EBL_REJECT", {0x800b0}, 0x10, 1, {0x4120007},
"Canceled L3 Accesses -- ebl rejects"},
796#define PME_ITA2_L2_L3ACCESS_CANCEL_FILLD_FULL 382
797{
"L2_L3ACCESS_CANCEL_FILLD_FULL", {0x200b0}, 0x10, 1, {0x4120007},
"Canceled L3 Accesses -- filld being full"},
798#define PME_ITA2_L2_L3ACCESS_CANCEL_IFETCH 383
799{
"L2_L3ACCESS_CANCEL_IFETCH", {0xb00b0}, 0xf0, 1, {0x4120007},
"Canceled L3 Accesses -- instruction fetches"},
800#define PME_ITA2_L2_L3ACCESS_CANCEL_INV_L3_BYP 384
801{
"L2_L3ACCESS_CANCEL_INV_L3_BYP", {0x600b0}, 0x10, 1, {0x4120007},
"Canceled L3 Accesses -- invalid L3 bypasses"},
802#define PME_ITA2_L2_L3ACCESS_CANCEL_SPEC_L3_BYP 385
803{
"L2_L3ACCESS_CANCEL_SPEC_L3_BYP", {0x100b0}, 0x10, 1, {0x4120007},
"Canceled L3 Accesses -- speculative L3 bypasses"},
804#define PME_ITA2_L2_L3ACCESS_CANCEL_UC_BLOCKED 386
805{
"L2_L3ACCESS_CANCEL_UC_BLOCKED", {0x500b0}, 0x10, 1, {0x4120007},
"Canceled L3 Accesses -- Uncacheable blocked L3 Accesses"},
806#define PME_ITA2_L2_MISSES 387
807{
"L2_MISSES", {0xcb}, 0xf0, 1, {0xf00007},
"L2 Misses"},
808#define PME_ITA2_L2_OPS_ISSUED_FP_LOAD 388
809{
"L2_OPS_ISSUED_FP_LOAD", {0x900b8}, 0xf0, 4, {0x4420007},
"Different Operations Issued by L2D -- Count only valid floating point loads"},
810#define PME_ITA2_L2_OPS_ISSUED_INT_LOAD 389
811{
"L2_OPS_ISSUED_INT_LOAD", {0x800b8}, 0xf0, 4, {0x4420007},
"Different Operations Issued by L2D -- Count only valid integer loads"},
812#define PME_ITA2_L2_OPS_ISSUED_NST_NLD 390
813{
"L2_OPS_ISSUED_NST_NLD", {0xc00b8}, 0xf0, 4, {0x4420007},
"Different Operations Issued by L2D -- Count only valid non-load, no-store accesses"},
814#define PME_ITA2_L2_OPS_ISSUED_RMW 391
815{
"L2_OPS_ISSUED_RMW", {0xa00b8}, 0xf0, 4, {0x4420007},
"Different Operations Issued by L2D -- Count only valid read_modify_write stores"},
816#define PME_ITA2_L2_OPS_ISSUED_STORE 392
817{
"L2_OPS_ISSUED_STORE", {0xb00b8}, 0xf0, 4, {0x4420007},
"Different Operations Issued by L2D -- Count only valid non-read_modify_write stores"},
818#define PME_ITA2_L2_OZDB_FULL_THIS 393
819{
"L2_OZDB_FULL_THIS", {0xbd}, 0xf0, 1, {0x4520000},
"L2 OZ Data Buffer Is Full -- L2 OZ Data Buffer is full"},
820#define PME_ITA2_L2_OZQ_ACQUIRE 394
821{
"L2_OZQ_ACQUIRE", {0xa2}, 0xf0, 1, {0x4020000},
"Clocks With Acquire Ordering Attribute Existed in L2 OZQ"},
822#define PME_ITA2_L2_OZQ_CANCELS0_ANY 395
823{
"L2_OZQ_CANCELS0_ANY", {0xa0}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Late or Any) -- counts the total OZ Queue cancels"},
824#define PME_ITA2_L2_OZQ_CANCELS0_LATE_ACQUIRE 396
825{
"L2_OZQ_CANCELS0_LATE_ACQUIRE", {0x300a0}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by acquires"},
826#define PME_ITA2_L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE 397
827{
"L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE", {0x400a0}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by L1D to L2A bypass effective releases"},
828#define PME_ITA2_L2_OZQ_CANCELS0_LATE_RELEASE 398
829{
"L2_OZQ_CANCELS0_LATE_RELEASE", {0x200a0}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by releases"},
830#define PME_ITA2_L2_OZQ_CANCELS0_LATE_SPEC_BYP 399
831{
"L2_OZQ_CANCELS0_LATE_SPEC_BYP", {0x100a0}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by speculative bypasses"},
832#define PME_ITA2_L2_OZQ_CANCELS1_BANK_CONF 400
833{
"L2_OZQ_CANCELS1_BANK_CONF", {0x100ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- bank conflicts"},
834#define PME_ITA2_L2_OZQ_CANCELS1_CANC_L2M_ST 401
835{
"L2_OZQ_CANCELS1_CANC_L2M_ST", {0x600ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- caused by a canceled store in L2M"},
836#define PME_ITA2_L2_OZQ_CANCELS1_CCV 402
837{
"L2_OZQ_CANCELS1_CCV", {0x900ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a ccv"},
838#define PME_ITA2_L2_OZQ_CANCELS1_ECC 403
839{
"L2_OZQ_CANCELS1_ECC", {0xf00ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- ECC hardware detecting a problem"},
840#define PME_ITA2_L2_OZQ_CANCELS1_HPW_IFETCH_CONF 404
841{
"L2_OZQ_CANCELS1_HPW_IFETCH_CONF", {0x500ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a ifetch conflict (canceling HPW?)"},
842#define PME_ITA2_L2_OZQ_CANCELS1_L1DF_L2M 405
843{
"L2_OZQ_CANCELS1_L1DF_L2M", {0xe00ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- L1D fill in L2M"},
844#define PME_ITA2_L2_OZQ_CANCELS1_L1_FILL_CONF 406
845{
"L2_OZQ_CANCELS1_L1_FILL_CONF", {0x700ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- an L1 fill conflict"},
846#define PME_ITA2_L2_OZQ_CANCELS1_L2A_ST_MAT 407
847{
"L2_OZQ_CANCELS1_L2A_ST_MAT", {0xd00ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2A"},
848#define PME_ITA2_L2_OZQ_CANCELS1_L2D_ST_MAT 408
849{
"L2_OZQ_CANCELS1_L2D_ST_MAT", {0x200ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2D"},
850#define PME_ITA2_L2_OZQ_CANCELS1_L2M_ST_MAT 409
851{
"L2_OZQ_CANCELS1_L2M_ST_MAT", {0xb00ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2M"},
852#define PME_ITA2_L2_OZQ_CANCELS1_MFA 410
853{
"L2_OZQ_CANCELS1_MFA", {0xc00ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a memory fence instruction"},
854#define PME_ITA2_L2_OZQ_CANCELS1_REL 411
855{
"L2_OZQ_CANCELS1_REL", {0xac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- caused by release"},
856#define PME_ITA2_L2_OZQ_CANCELS1_SEM 412
857{
"L2_OZQ_CANCELS1_SEM", {0xa00ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a semaphore"},
858#define PME_ITA2_L2_OZQ_CANCELS1_ST_FILL_CONF 413
859{
"L2_OZQ_CANCELS1_ST_FILL_CONF", {0x800ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- a store fill conflict"},
860#define PME_ITA2_L2_OZQ_CANCELS1_SYNC 414
861{
"L2_OZQ_CANCELS1_SYNC", {0x400ac}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 1) -- caused by sync.i"},
862#define PME_ITA2_L2_OZQ_CANCELS2_ACQ 415
863{
"L2_OZQ_CANCELS2_ACQ", {0x400a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- caused by an acquire"},
864#define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2C_ST 416
865{
"L2_OZQ_CANCELS2_CANC_L2C_ST", {0x100a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2C"},
866#define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2D_ST 417
867{
"L2_OZQ_CANCELS2_CANC_L2D_ST", {0xd00a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2D"},
868#define PME_ITA2_L2_OZQ_CANCELS2_DIDNT_RECIRC 418
869{
"L2_OZQ_CANCELS2_DIDNT_RECIRC", {0x900a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- caused because it did not recirculate"},
870#define PME_ITA2_L2_OZQ_CANCELS2_D_IFET 419
871{
"L2_OZQ_CANCELS2_D_IFET", {0xf00a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- a demand ifetch"},
872#define PME_ITA2_L2_OZQ_CANCELS2_L2C_ST_MAT 420
873{
"L2_OZQ_CANCELS2_L2C_ST_MAT", {0x200a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- a store match in L2C"},
874#define PME_ITA2_L2_OZQ_CANCELS2_L2FILL_ST_CONF 421
875{
"L2_OZQ_CANCELS2_L2FILL_ST_CONF", {0x800a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- a L2fill and store conflict in L2C"},
876#define PME_ITA2_L2_OZQ_CANCELS2_OVER_SUB 422
877{
"L2_OZQ_CANCELS2_OVER_SUB", {0xc00a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- oversubscription"},
878#define PME_ITA2_L2_OZQ_CANCELS2_OZ_DATA_CONF 423
879{
"L2_OZQ_CANCELS2_OZ_DATA_CONF", {0x600a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- an OZ data conflict"},
880#define PME_ITA2_L2_OZQ_CANCELS2_READ_WB_CONF 424
881{
"L2_OZQ_CANCELS2_READ_WB_CONF", {0x500a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- a write back conflict (canceling read?)"},
882#define PME_ITA2_L2_OZQ_CANCELS2_RECIRC_OVER_SUB 425
883{
"L2_OZQ_CANCELS2_RECIRC_OVER_SUB", {0xa8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- caused by a recirculate oversubscription"},
884#define PME_ITA2_L2_OZQ_CANCELS2_SCRUB 426
885{
"L2_OZQ_CANCELS2_SCRUB", {0x300a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- 32/64 byte HPW/L2D fill which needs scrub"},
886#define PME_ITA2_L2_OZQ_CANCELS2_WEIRD 427
887{
"L2_OZQ_CANCELS2_WEIRD", {0xa00a8}, 0xf0, 4, {0x4020007},
"L2 OZQ Cancels (Specific Reason Set 2) -- counts the cancels caused by attempted 5-cycle bypasses for non-aligned accesses and bypasses blocking recirculates for too long"},
888#define PME_ITA2_L2_OZQ_FULL_THIS 428
889{
"L2_OZQ_FULL_THIS", {0xbc}, 0xf0, 1, {0x4520000},
"L2D OZQ Is Full -- L2D OZQ is full"},
890#define PME_ITA2_L2_OZQ_RELEASE 429
891{
"L2_OZQ_RELEASE", {0xa3}, 0xf0, 1, {0x4020000},
"Clocks With Release Ordering Attribute Existed in L2 OZQ"},
892#define PME_ITA2_L2_REFERENCES 430
893{
"L2_REFERENCES", {0xb1}, 0xf0, 4, {0x4120007},
"Requests Made To L2"},
894#define PME_ITA2_L2_STORE_HIT_SHARED_ANY 431
895{
"L2_STORE_HIT_SHARED_ANY", {0xba}, 0xf0, 2, {0x4320007},
"Store Hit a Shared Line -- Store hit a shared line"},
896#define PME_ITA2_L2_SYNTH_PROBE 432
897{
"L2_SYNTH_PROBE", {0xb7}, 0xf0, 1, {0x4220007},
"Synthesized Probe"},
898#define PME_ITA2_L2_VICTIMB_FULL_THIS 433
899{
"L2_VICTIMB_FULL_THIS", {0xbe}, 0xf0, 1, {0x4520000},
"L2D Victim Buffer Is Full -- L2D victim buffer is full"},
900#define PME_ITA2_L3_LINES_REPLACED 434
901{
"L3_LINES_REPLACED", {0xdf}, 0xf0, 1, {0xf00000},
"L3 Cache Lines Replaced"},
902#define PME_ITA2_L3_MISSES 435
903{
"L3_MISSES", {0xdc}, 0xf0, 1, {0xf00007},
"L3 Misses"},
904#define PME_ITA2_L3_READS_ALL_ALL 436
905{
"L3_READS_ALL_ALL", {0xf00dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Read References"},
906#define PME_ITA2_L3_READS_ALL_HIT 437
907{
"L3_READS_ALL_HIT", {0xd00dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Read Hits"},
908#define PME_ITA2_L3_READS_ALL_MISS 438
909{
"L3_READS_ALL_MISS", {0xe00dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Read Misses"},
910#define PME_ITA2_L3_READS_DATA_READ_ALL 439
911{
"L3_READS_DATA_READ_ALL", {0xb00dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Load References (excludes reads for ownership used to satisfy stores)"},
912#define PME_ITA2_L3_READS_DATA_READ_HIT 440
913{
"L3_READS_DATA_READ_HIT", {0x900dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Load Hits (excludes reads for ownership used to satisfy stores)"},
914#define PME_ITA2_L3_READS_DATA_READ_MISS 441
915{
"L3_READS_DATA_READ_MISS", {0xa00dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Load Misses (excludes reads for ownership used to satisfy stores)"},
916#define PME_ITA2_L3_READS_DINST_FETCH_ALL 442
917{
"L3_READS_DINST_FETCH_ALL", {0x300dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Demand Instruction References"},
918#define PME_ITA2_L3_READS_DINST_FETCH_HIT 443
919{
"L3_READS_DINST_FETCH_HIT", {0x100dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Demand Instruction Fetch Hits"},
920#define PME_ITA2_L3_READS_DINST_FETCH_MISS 444
921{
"L3_READS_DINST_FETCH_MISS", {0x200dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Demand Instruction Fetch Misses"},
922#define PME_ITA2_L3_READS_INST_FETCH_ALL 445
923{
"L3_READS_INST_FETCH_ALL", {0x700dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Instruction Fetch and Prefetch References"},
924#define PME_ITA2_L3_READS_INST_FETCH_HIT 446
925{
"L3_READS_INST_FETCH_HIT", {0x500dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Instruction Fetch and Prefetch Hits"},
926#define PME_ITA2_L3_READS_INST_FETCH_MISS 447
927{
"L3_READS_INST_FETCH_MISS", {0x600dd}, 0xf0, 1, {0xf00007},
"L3 Reads -- L3 Instruction Fetch and Prefetch Misses"},
928#define PME_ITA2_L3_REFERENCES 448
929{
"L3_REFERENCES", {0xdb}, 0xf0, 1, {0xf00007},
"L3 References"},
930#define PME_ITA2_L3_WRITES_ALL_ALL 449
931{
"L3_WRITES_ALL_ALL", {0xf00de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L3 Write References"},
932#define PME_ITA2_L3_WRITES_ALL_HIT 450
933{
"L3_WRITES_ALL_HIT", {0xd00de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L3 Write Hits"},
934#define PME_ITA2_L3_WRITES_ALL_MISS 451
935{
"L3_WRITES_ALL_MISS", {0xe00de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L3 Write Misses"},
936#define PME_ITA2_L3_WRITES_DATA_WRITE_ALL 452
937{
"L3_WRITES_DATA_WRITE_ALL", {0x700de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L3 Store References (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"},
938#define PME_ITA2_L3_WRITES_DATA_WRITE_HIT 453
939{
"L3_WRITES_DATA_WRITE_HIT", {0x500de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L3 Store Hits (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"},
940#define PME_ITA2_L3_WRITES_DATA_WRITE_MISS 454
941{
"L3_WRITES_DATA_WRITE_MISS", {0x600de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L3 Store Misses (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"},
942#define PME_ITA2_L3_WRITES_L2_WB_ALL 455
943{
"L3_WRITES_L2_WB_ALL", {0xb00de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L2 Write Back References"},
944#define PME_ITA2_L3_WRITES_L2_WB_HIT 456
945{
"L3_WRITES_L2_WB_HIT", {0x900de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L2 Write Back Hits"},
946#define PME_ITA2_L3_WRITES_L2_WB_MISS 457
947{
"L3_WRITES_L2_WB_MISS", {0xa00de}, 0xf0, 1, {0xf00007},
"L3 Writes -- L2 Write Back Misses"},
948#define PME_ITA2_LOADS_RETIRED 458
949{
"LOADS_RETIRED", {0xcd}, 0xf0, 4, {0x5310007},
"Retired Loads"},
950#define PME_ITA2_MEM_READ_CURRENT_ANY 459
951{
"MEM_READ_CURRENT_ANY", {0x30089}, 0xf0, 1, {0xf00000},
"Current Mem Read Transactions On Bus -- CPU or non-CPU (all transactions)."},
952#define PME_ITA2_MEM_READ_CURRENT_IO 460
953{
"MEM_READ_CURRENT_IO", {0x10089}, 0xf0, 1, {0xf00000},
"Current Mem Read Transactions On Bus -- non-CPU priority agents"},
954#define PME_ITA2_MISALIGNED_LOADS_RETIRED 461
955{
"MISALIGNED_LOADS_RETIRED", {0xce}, 0xf0, 4, {0x5310007},
"Retired Misaligned Load Instructions"},
956#define PME_ITA2_MISALIGNED_STORES_RETIRED 462
957{
"MISALIGNED_STORES_RETIRED", {0xd2}, 0xf0, 2, {0x5410007},
"Retired Misaligned Store Instructions"},
958#define PME_ITA2_NOPS_RETIRED 463
959{
"NOPS_RETIRED", {0x50}, 0xf0, 6, {0xf00003},
"Retired NOP Instructions"},
960#define PME_ITA2_PREDICATE_SQUASHED_RETIRED 464
961{
"PREDICATE_SQUASHED_RETIRED", {0x51}, 0xf0, 6, {0xf00003},
"Instructions Squashed Due to Predicate Off"},
962#define PME_ITA2_RSE_CURRENT_REGS_2_TO_0 465
963{
"RSE_CURRENT_REGS_2_TO_0", {0x2b}, 0xf0, 7, {0xf00000},
"Current RSE Registers (Bits 2:0)"},
964#define PME_ITA2_RSE_CURRENT_REGS_5_TO_3 466
965{
"RSE_CURRENT_REGS_5_TO_3", {0x2a}, 0xf0, 7, {0xf00000},
"Current RSE Registers (Bits 5:3)"},
966#define PME_ITA2_RSE_CURRENT_REGS_6 467
967{
"RSE_CURRENT_REGS_6", {0x26}, 0xf0, 1, {0xf00000},
"Current RSE Registers (Bit 6)"},
968#define PME_ITA2_RSE_DIRTY_REGS_2_TO_0 468
969{
"RSE_DIRTY_REGS_2_TO_0", {0x29}, 0xf0, 7, {0xf00000},
"Dirty RSE Registers (Bits 2:0)"},
970#define PME_ITA2_RSE_DIRTY_REGS_5_TO_3 469
971{
"RSE_DIRTY_REGS_5_TO_3", {0x28}, 0xf0, 7, {0xf00000},
"Dirty RSE Registers (Bits 5:3)"},
972#define PME_ITA2_RSE_DIRTY_REGS_6 470
973{
"RSE_DIRTY_REGS_6", {0x24}, 0xf0, 1, {0xf00000},
"Dirty RSE Registers (Bit 6)"},
974#define PME_ITA2_RSE_EVENT_RETIRED 471
975{
"RSE_EVENT_RETIRED", {0x32}, 0xf0, 1, {0xf00000},
"Retired RSE operations"},
976#define PME_ITA2_RSE_REFERENCES_RETIRED_ALL 472
977{
"RSE_REFERENCES_RETIRED_ALL", {0x30020}, 0xf0, 2, {0xf00007},
"RSE Accesses -- Both RSE loads and stores will be counted."},
978#define PME_ITA2_RSE_REFERENCES_RETIRED_LOAD 473
979{
"RSE_REFERENCES_RETIRED_LOAD", {0x10020}, 0xf0, 2, {0xf00007},
"RSE Accesses -- Only RSE loads will be counted."},
980#define PME_ITA2_RSE_REFERENCES_RETIRED_STORE 474
981{
"RSE_REFERENCES_RETIRED_STORE", {0x20020}, 0xf0, 2, {0xf00007},
"RSE Accesses -- Only RSE stores will be counted."},
982#define PME_ITA2_SERIALIZATION_EVENTS 475
983{
"SERIALIZATION_EVENTS", {0x53}, 0xf0, 1, {0xf00000},
"Number of srlz.i Instructions"},
984#define PME_ITA2_STORES_RETIRED 476
985{
"STORES_RETIRED", {0xd1}, 0xf0, 2, {0x5410007},
"Retired Stores"},
986#define PME_ITA2_SYLL_NOT_DISPERSED_ALL 477
987{
"SYLL_NOT_DISPERSED_ALL", {0xf004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Counts all syllables not dispersed. NOTE: Any combination of b0000-b1111 is valid."},
988#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL 478
989{
"SYLL_NOT_DISPERSED_EXPL", {0x1004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits. These consist of programmer specified architected S-bit and templates 1 and 5. Dispersal takes a 6-syllable (3-syllable) hit for every template 1/5 in bundle 0(1). Dispersal takes a 3-syllable (0 syllable) hit for every S-bit in bundle 0(1)"},
990#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE 479
991{
"SYLL_NOT_DISPERSED_EXPL_OR_FE", {0x5004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or front-end not providing valid bundles or providing valid illegal templates."},
992#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI 480
993{
"SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI", {0xd004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLI bundle and resteers to non-0 syllable."},
994#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 481
995{
"SYLL_NOT_DISPERSED_EXPL_OR_IMPL", {0x3004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to explicit/implicit stop bits."},
996#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 482
997{
"SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE", {0x7004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to front-end not providing valid bundles or providing valid illegal template."},
998#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI 483
999{
"SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI", {0xb004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to MLI bundle and resteers to non-0 syllable."},
1000#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_MLI 484
1001{
"SYLL_NOT_DISPERSED_EXPL_OR_MLI", {0x9004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or to MLI bundle and resteers to non-0 syllable."},
1002#define PME_ITA2_SYLL_NOT_DISPERSED_FE 485
1003{
"SYLL_NOT_DISPERSED_FE", {0x4004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to front-end not providing valid bundles or providing valid illegal templates. Dispersal takes a 3-syllable hit for every invalid bundle or valid illegal template from front-end. Bundle 1 with front-end fault, is counted here (3-syllable hit).."},
1004#define PME_ITA2_SYLL_NOT_DISPERSED_FE_OR_MLI 486
1005{
"SYLL_NOT_DISPERSED_FE_OR_MLI", {0xc004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable or due to front-end not providing valid bundles or providing valid illegal templates."},
1006#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL 487
1007{
"SYLL_NOT_DISPERSED_IMPL", {0x2004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits. These consist of all of the non-architected stop bits (asymmetry, oversubscription, implicit). Dispersal takes a 6-syllable(3-syllable) hit for every implicit stop bits in bundle 0(1)."},
1008#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE 488
1009{
"SYLL_NOT_DISPERSED_IMPL_OR_FE", {0x6004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to front-end not providing valid bundles or providing valid illegal templates."},
1010#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI 489
1011{
"SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI", {0xe004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLI bundle and resteers to non-0 syllable."},
1012#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_MLI 490
1013{
"SYLL_NOT_DISPERSED_IMPL_OR_MLI", {0xa004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to MLI bundle and resteers to non-0 syllable."},
1014#define PME_ITA2_SYLL_NOT_DISPERSED_MLI 491
1015{
"SYLL_NOT_DISPERSED_MLI", {0x8004e}, 0xf0, 5, {0xf00001},
"Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable. Dispersal takes a 1 syllable hit for each MLI bundle . Dispersal could take 0-2 syllable hit depending on which syllable we resteer to. Bundle 1 with front-end fault which is split, is counted here (0-2 syllable hit)."},
1016#define PME_ITA2_SYLL_OVERCOUNT_ALL 492
1017{
"SYLL_OVERCOUNT_ALL", {0x3004f}, 0xf0, 2, {0xf00001},
"Syllables Overcounted -- syllables overcounted in implicit & explicit bucket"},
1018#define PME_ITA2_SYLL_OVERCOUNT_EXPL 493
1019{
"SYLL_OVERCOUNT_EXPL", {0x1004f}, 0xf0, 2, {0xf00001},
"Syllables Overcounted -- Only syllables overcounted in the explicit bucket"},
1020#define PME_ITA2_SYLL_OVERCOUNT_IMPL 494
1021{
"SYLL_OVERCOUNT_IMPL", {0x2004f}, 0xf0, 2, {0xf00001},
"Syllables Overcounted -- Only syllables overcounted in the implicit bucket"},
1022#define PME_ITA2_UC_LOADS_RETIRED 495
1023{
"UC_LOADS_RETIRED", {0xcf}, 0xf0, 4, {0x5310007},
"Retired Uncacheable Loads"},
1024#define PME_ITA2_UC_STORES_RETIRED 496
1025{
"UC_STORES_RETIRED", {0xd0}, 0xf0, 2, {0x5410007},
"Retired Uncacheable Stores"},
1027#define PME_ITA2_EVENT_COUNT 497
static pme_ita2_entry_t itanium2_pe[]
1.9.6