This graph shows which files directly or indirectly include this file:

Macros
#define	PME_ITA2_ALAT_CAPACITY_MISS_ALL 0

#define	PME_ITA2_ALAT_CAPACITY_MISS_FP 1

#define	PME_ITA2_ALAT_CAPACITY_MISS_INT 2

#define	PME_ITA2_BACK_END_BUBBLE_ALL 3

#define	PME_ITA2_BACK_END_BUBBLE_FE 4

#define	PME_ITA2_BACK_END_BUBBLE_L1D_FPU_RSE 5

#define	PME_ITA2_BE_BR_MISPRED_DETAIL_ANY 6

#define	PME_ITA2_BE_BR_MISPRED_DETAIL_PFS 7

#define	PME_ITA2_BE_BR_MISPRED_DETAIL_ROT 8

#define	PME_ITA2_BE_BR_MISPRED_DETAIL_STG 9

#define	PME_ITA2_BE_EXE_BUBBLE_ALL 10

#define	PME_ITA2_BE_EXE_BUBBLE_ARCR 11

#define	PME_ITA2_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 12

#define	PME_ITA2_BE_EXE_BUBBLE_BANK_SWITCH 13

#define	PME_ITA2_BE_EXE_BUBBLE_CANCEL 14

#define	PME_ITA2_BE_EXE_BUBBLE_FRALL 15

#define	PME_ITA2_BE_EXE_BUBBLE_GRALL 16

#define	PME_ITA2_BE_EXE_BUBBLE_GRGR 17

#define	PME_ITA2_BE_EXE_BUBBLE_PR 18

#define	PME_ITA2_BE_FLUSH_BUBBLE_ALL 19

#define	PME_ITA2_BE_FLUSH_BUBBLE_BRU 20

#define	PME_ITA2_BE_FLUSH_BUBBLE_XPN 21

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_ALL 22

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_FPU 23

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D 24

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCS 25

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCURECIR 26

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 27

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 28

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_HPW 29

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 30

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCHK 31

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCONF 32

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NAT 33

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NATCONF 34

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 35

#define	PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_TLB 36

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_ALL 37

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_BI 38

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_BRQ 39

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 40

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_BUBBLE 41

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_FEFLUSH 42

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 43

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_IBFULL 44

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_IMISS 45

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_PLP 46

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_TLBMISS 47

#define	PME_ITA2_BE_LOST_BW_DUE_TO_FE_UNREACHED 48

#define	PME_ITA2_BE_RSE_BUBBLE_ALL 49

#define	PME_ITA2_BE_RSE_BUBBLE_AR_DEP 50

#define	PME_ITA2_BE_RSE_BUBBLE_BANK_SWITCH 51

#define	PME_ITA2_BE_RSE_BUBBLE_LOADRS 52

#define	PME_ITA2_BE_RSE_BUBBLE_OVERFLOW 53

#define	PME_ITA2_BE_RSE_BUBBLE_UNDERFLOW 54

#define	PME_ITA2_BRANCH_EVENT 55

#define	PME_ITA2_BR_MISPRED_DETAIL_ALL_ALL_PRED 56

#define	PME_ITA2_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 57

#define	PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_PATH 58

#define	PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 59

#define	PME_ITA2_BR_MISPRED_DETAIL_IPREL_ALL_PRED 60

#define	PME_ITA2_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 61

#define	PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 62

#define	PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 63

#define	PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_ALL_PRED 64

#define	PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED 65

#define	PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH 66

#define	PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET 67

#define	PME_ITA2_BR_MISPRED_DETAIL_RETURN_ALL_PRED 68

#define	PME_ITA2_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 69

#define	PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 70

#define	PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 71

#define	PME_ITA2_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 72

#define	PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 73

#define	PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 74

#define	PME_ITA2_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 75

#define	PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 76

#define	PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 77

#define	PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 78

#define	PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 79

#define	PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 80

#define	PME_ITA2_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 81

#define	PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 82

#define	PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 83

#define	PME_ITA2_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 84

#define	PME_ITA2_BR_PATH_PRED_ALL_MISPRED_TAKEN 85

#define	PME_ITA2_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 86

#define	PME_ITA2_BR_PATH_PRED_ALL_OKPRED_TAKEN 87

#define	PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 88

#define	PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_TAKEN 89

#define	PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 90

#define	PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_TAKEN 91

#define	PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 92

#define	PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 93

#define	PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 94

#define	PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 95

#define	PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 96

#define	PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_TAKEN 97

#define	PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 98

#define	PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_TAKEN 99

#define	PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 100

#define	PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 101

#define	PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 102

#define	PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 103

#define	PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 104

#define	PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 105

#define	PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 106

#define	PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 107

#define	PME_ITA2_BUS_ALL_ANY 108

#define	PME_ITA2_BUS_ALL_IO 109

#define	PME_ITA2_BUS_ALL_SELF 110

#define	PME_ITA2_BUS_BACKSNP_REQ_THIS 111

#define	PME_ITA2_BUS_BRQ_LIVE_REQ_HI 112

#define	PME_ITA2_BUS_BRQ_LIVE_REQ_LO 113

#define	PME_ITA2_BUS_BRQ_REQ_INSERTED 114

#define	PME_ITA2_BUS_DATA_CYCLE 115

#define	PME_ITA2_BUS_HITM 116

#define	PME_ITA2_BUS_IO_ANY 117

#define	PME_ITA2_BUS_IO_IO 118

#define	PME_ITA2_BUS_IO_SELF 119

#define	PME_ITA2_BUS_IOQ_LIVE_REQ_HI 120

#define	PME_ITA2_BUS_IOQ_LIVE_REQ_LO 121

#define	PME_ITA2_BUS_LOCK_ANY 122

#define	PME_ITA2_BUS_LOCK_SELF 123

#define	PME_ITA2_BUS_MEMORY_ALL_ANY 124

#define	PME_ITA2_BUS_MEMORY_ALL_IO 125

#define	PME_ITA2_BUS_MEMORY_ALL_SELF 126

#define	PME_ITA2_BUS_MEMORY_EQ_128BYTE_ANY 127

#define	PME_ITA2_BUS_MEMORY_EQ_128BYTE_IO 128

#define	PME_ITA2_BUS_MEMORY_EQ_128BYTE_SELF 129

#define	PME_ITA2_BUS_MEMORY_LT_128BYTE_ANY 130

#define	PME_ITA2_BUS_MEMORY_LT_128BYTE_IO 131

#define	PME_ITA2_BUS_MEMORY_LT_128BYTE_SELF 132

#define	PME_ITA2_BUS_MEM_READ_ALL_ANY 133

#define	PME_ITA2_BUS_MEM_READ_ALL_IO 134

#define	PME_ITA2_BUS_MEM_READ_ALL_SELF 135

#define	PME_ITA2_BUS_MEM_READ_BIL_ANY 136

#define	PME_ITA2_BUS_MEM_READ_BIL_IO 137

#define	PME_ITA2_BUS_MEM_READ_BIL_SELF 138

#define	PME_ITA2_BUS_MEM_READ_BRIL_ANY 139

#define	PME_ITA2_BUS_MEM_READ_BRIL_IO 140

#define	PME_ITA2_BUS_MEM_READ_BRIL_SELF 141

#define	PME_ITA2_BUS_MEM_READ_BRL_ANY 142

#define	PME_ITA2_BUS_MEM_READ_BRL_IO 143

#define	PME_ITA2_BUS_MEM_READ_BRL_SELF 144

#define	PME_ITA2_BUS_MEM_READ_OUT_HI 145

#define	PME_ITA2_BUS_MEM_READ_OUT_LO 146

#define	PME_ITA2_BUS_OOQ_LIVE_REQ_HI 147

#define	PME_ITA2_BUS_OOQ_LIVE_REQ_LO 148

#define	PME_ITA2_BUS_RD_DATA_ANY 149

#define	PME_ITA2_BUS_RD_DATA_IO 150

#define	PME_ITA2_BUS_RD_DATA_SELF 151

#define	PME_ITA2_BUS_RD_HIT 152

#define	PME_ITA2_BUS_RD_HITM 153

#define	PME_ITA2_BUS_RD_INVAL_ALL_HITM 154

#define	PME_ITA2_BUS_RD_INVAL_HITM 155

#define	PME_ITA2_BUS_RD_IO_ANY 156

#define	PME_ITA2_BUS_RD_IO_IO 157

#define	PME_ITA2_BUS_RD_IO_SELF 158

#define	PME_ITA2_BUS_RD_PRTL_ANY 159

#define	PME_ITA2_BUS_RD_PRTL_IO 160

#define	PME_ITA2_BUS_RD_PRTL_SELF 161

#define	PME_ITA2_BUS_SNOOPQ_REQ 162

#define	PME_ITA2_BUS_SNOOPS_ANY 163

#define	PME_ITA2_BUS_SNOOPS_IO 164

#define	PME_ITA2_BUS_SNOOPS_SELF 165

#define	PME_ITA2_BUS_SNOOPS_HITM_ANY 166

#define	PME_ITA2_BUS_SNOOPS_HITM_SELF 167

#define	PME_ITA2_BUS_SNOOP_STALL_CYCLES_ANY 168

#define	PME_ITA2_BUS_SNOOP_STALL_CYCLES_SELF 169

#define	PME_ITA2_BUS_WR_WB_ALL_ANY 170

#define	PME_ITA2_BUS_WR_WB_ALL_IO 171

#define	PME_ITA2_BUS_WR_WB_ALL_SELF 172

#define	PME_ITA2_BUS_WR_WB_CCASTOUT_ANY 173

#define	PME_ITA2_BUS_WR_WB_CCASTOUT_SELF 174

#define	PME_ITA2_BUS_WR_WB_EQ_128BYTE_ANY 175

#define	PME_ITA2_BUS_WR_WB_EQ_128BYTE_IO 176

#define	PME_ITA2_BUS_WR_WB_EQ_128BYTE_SELF 177

#define	PME_ITA2_CPU_CPL_CHANGES 178

#define	PME_ITA2_CPU_CYCLES 179

#define	PME_ITA2_DATA_DEBUG_REGISTER_FAULT 180

#define	PME_ITA2_DATA_DEBUG_REGISTER_MATCHES 181

#define	PME_ITA2_DATA_EAR_ALAT 182

#define	PME_ITA2_DATA_EAR_CACHE_LAT1024 183

#define	PME_ITA2_DATA_EAR_CACHE_LAT128 184

#define	PME_ITA2_DATA_EAR_CACHE_LAT16 185

#define	PME_ITA2_DATA_EAR_CACHE_LAT2048 186

#define	PME_ITA2_DATA_EAR_CACHE_LAT256 187

#define	PME_ITA2_DATA_EAR_CACHE_LAT32 188

#define	PME_ITA2_DATA_EAR_CACHE_LAT4 189

#define	PME_ITA2_DATA_EAR_CACHE_LAT4096 190

#define	PME_ITA2_DATA_EAR_CACHE_LAT512 191

#define	PME_ITA2_DATA_EAR_CACHE_LAT64 192

#define	PME_ITA2_DATA_EAR_CACHE_LAT8 193

#define	PME_ITA2_DATA_EAR_EVENTS 194

#define	PME_ITA2_DATA_EAR_TLB_ALL 195

#define	PME_ITA2_DATA_EAR_TLB_FAULT 196

#define	PME_ITA2_DATA_EAR_TLB_L2DTLB 197

#define	PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_FAULT 198

#define	PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_VHPT 199

#define	PME_ITA2_DATA_EAR_TLB_VHPT 200

#define	PME_ITA2_DATA_EAR_TLB_VHPT_OR_FAULT 201

#define	PME_ITA2_DATA_REFERENCES_SET0 202

#define	PME_ITA2_DATA_REFERENCES_SET1 203

#define	PME_ITA2_DISP_STALLED 204

#define	PME_ITA2_DTLB_INSERTS_HPW 205

#define	PME_ITA2_DTLB_INSERTS_HPW_RETIRED 206

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 207

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 208

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 209

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 210

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 211

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 212

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 213

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 214

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 215

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 216

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 217

#define	PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 218

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_ALL 219

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0 220

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1 221

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2 222

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3 223

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2 224

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3 225

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3 226

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1 227

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2 228

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3 229

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3 230

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2 231

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3 232

#define	PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN3 233

#define	PME_ITA2_EXTERN_DP_PINS_4_TO_5_ALL 234

#define	PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN4 235

#define	PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN5 236

#define	PME_ITA2_FE_BUBBLE_ALL 237

#define	PME_ITA2_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 238

#define	PME_ITA2_FE_BUBBLE_ALLBUT_IBFULL 239

#define	PME_ITA2_FE_BUBBLE_BRANCH 240

#define	PME_ITA2_FE_BUBBLE_BUBBLE 241

#define	PME_ITA2_FE_BUBBLE_FEFLUSH 242

#define	PME_ITA2_FE_BUBBLE_FILL_RECIRC 243

#define	PME_ITA2_FE_BUBBLE_GROUP1 244

#define	PME_ITA2_FE_BUBBLE_GROUP2 245

#define	PME_ITA2_FE_BUBBLE_GROUP3 246

#define	PME_ITA2_FE_BUBBLE_IBFULL 247

#define	PME_ITA2_FE_BUBBLE_IMISS 248

#define	PME_ITA2_FE_BUBBLE_TLBMISS 249

#define	PME_ITA2_FE_LOST_BW_ALL 250

#define	PME_ITA2_FE_LOST_BW_BI 251

#define	PME_ITA2_FE_LOST_BW_BRQ 252

#define	PME_ITA2_FE_LOST_BW_BR_ILOCK 253

#define	PME_ITA2_FE_LOST_BW_BUBBLE 254

#define	PME_ITA2_FE_LOST_BW_FEFLUSH 255

#define	PME_ITA2_FE_LOST_BW_FILL_RECIRC 256

#define	PME_ITA2_FE_LOST_BW_IBFULL 257

#define	PME_ITA2_FE_LOST_BW_IMISS 258

#define	PME_ITA2_FE_LOST_BW_PLP 259

#define	PME_ITA2_FE_LOST_BW_TLBMISS 260

#define	PME_ITA2_FE_LOST_BW_UNREACHED 261

#define	PME_ITA2_FP_FAILED_FCHKF 262

#define	PME_ITA2_FP_FALSE_SIRSTALL 263

#define	PME_ITA2_FP_FLUSH_TO_ZERO 264

#define	PME_ITA2_FP_OPS_RETIRED 265

#define	PME_ITA2_FP_TRUE_SIRSTALL 266

#define	PME_ITA2_HPW_DATA_REFERENCES 267

#define	PME_ITA2_IA32_INST_RETIRED 268

#define	PME_ITA2_IA32_ISA_TRANSITIONS 269

#define	PME_ITA2_IA64_INST_RETIRED 270

#define	PME_ITA2_IA64_INST_RETIRED_THIS 271

#define	PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8 272

#define	PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9 273

#define	PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8 274

#define	PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9 275

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 276

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 277

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 278

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 279

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 280

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 281

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 282

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 283

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 284

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 285

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 286

#define	PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 287

#define	PME_ITA2_INST_CHKA_LDC_ALAT_ALL 288

#define	PME_ITA2_INST_CHKA_LDC_ALAT_FP 289

#define	PME_ITA2_INST_CHKA_LDC_ALAT_INT 290

#define	PME_ITA2_INST_DISPERSED 291

#define	PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_ALL 292

#define	PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_FP 293

#define	PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_INT 294

#define	PME_ITA2_INST_FAILED_CHKS_RETIRED_ALL 295

#define	PME_ITA2_INST_FAILED_CHKS_RETIRED_FP 296

#define	PME_ITA2_INST_FAILED_CHKS_RETIRED_INT 297

#define	PME_ITA2_ISB_BUNPAIRS_IN 298

#define	PME_ITA2_ITLB_MISSES_FETCH_ALL 299

#define	PME_ITA2_ITLB_MISSES_FETCH_L1ITLB 300

#define	PME_ITA2_ITLB_MISSES_FETCH_L2ITLB 301

#define	PME_ITA2_L1DTLB_TRANSFER 302

#define	PME_ITA2_L1D_READS_SET0 303

#define	PME_ITA2_L1D_READS_SET1 304

#define	PME_ITA2_L1D_READ_MISSES_ALL 305

#define	PME_ITA2_L1D_READ_MISSES_RSE_FILL 306

#define	PME_ITA2_L1ITLB_INSERTS_HPW 307

#define	PME_ITA2_L1I_EAR_CACHE_LAT0 308

#define	PME_ITA2_L1I_EAR_CACHE_LAT1024 309

#define	PME_ITA2_L1I_EAR_CACHE_LAT128 310

#define	PME_ITA2_L1I_EAR_CACHE_LAT16 311

#define	PME_ITA2_L1I_EAR_CACHE_LAT256 312

#define	PME_ITA2_L1I_EAR_CACHE_LAT32 313

#define	PME_ITA2_L1I_EAR_CACHE_LAT4 314

#define	PME_ITA2_L1I_EAR_CACHE_LAT4096 315

#define	PME_ITA2_L1I_EAR_CACHE_LAT8 316

#define	PME_ITA2_L1I_EAR_CACHE_RAB 317

#define	PME_ITA2_L1I_EAR_EVENTS 318

#define	PME_ITA2_L1I_EAR_TLB_ALL 319

#define	PME_ITA2_L1I_EAR_TLB_FAULT 320

#define	PME_ITA2_L1I_EAR_TLB_L2TLB 321

#define	PME_ITA2_L1I_EAR_TLB_L2TLB_OR_FAULT 322

#define	PME_ITA2_L1I_EAR_TLB_L2TLB_OR_VHPT 323

#define	PME_ITA2_L1I_EAR_TLB_VHPT 324

#define	PME_ITA2_L1I_EAR_TLB_VHPT_OR_FAULT 325

#define	PME_ITA2_L1I_FETCH_ISB_HIT 326

#define	PME_ITA2_L1I_FETCH_RAB_HIT 327

#define	PME_ITA2_L1I_FILLS 328

#define	PME_ITA2_L1I_PREFETCHES 329

#define	PME_ITA2_L1I_PREFETCH_STALL_ALL 330

#define	PME_ITA2_L1I_PREFETCH_STALL_FLOW 331

#define	PME_ITA2_L1I_PURGE 332

#define	PME_ITA2_L1I_PVAB_OVERFLOW 333

#define	PME_ITA2_L1I_RAB_ALMOST_FULL 334

#define	PME_ITA2_L1I_RAB_FULL 335

#define	PME_ITA2_L1I_READS 336

#define	PME_ITA2_L1I_SNOOP 337

#define	PME_ITA2_L1I_STRM_PREFETCHES 338

#define	PME_ITA2_L2DTLB_MISSES 339

#define	PME_ITA2_L2_BAD_LINES_SELECTED_ANY 340

#define	PME_ITA2_L2_BYPASS_L2_DATA1 341

#define	PME_ITA2_L2_BYPASS_L2_DATA2 342

#define	PME_ITA2_L2_BYPASS_L2_INST1 343

#define	PME_ITA2_L2_BYPASS_L2_INST2 344

#define	PME_ITA2_L2_BYPASS_L3_DATA1 345

#define	PME_ITA2_L2_BYPASS_L3_INST1 346

#define	PME_ITA2_L2_DATA_REFERENCES_L2_ALL 347

#define	PME_ITA2_L2_DATA_REFERENCES_L2_DATA_READS 348

#define	PME_ITA2_L2_DATA_REFERENCES_L2_DATA_WRITES 349

#define	PME_ITA2_L2_FILLB_FULL_THIS 350

#define	PME_ITA2_L2_FORCE_RECIRC_ANY 351

#define	PME_ITA2_L2_FORCE_RECIRC_FILL_HIT 352

#define	PME_ITA2_L2_FORCE_RECIRC_FRC_RECIRC 353

#define	PME_ITA2_L2_FORCE_RECIRC_IPF_MISS 354

#define	PME_ITA2_L2_FORCE_RECIRC_L1W 355

#define	PME_ITA2_L2_FORCE_RECIRC_OZQ_MISS 356

#define	PME_ITA2_L2_FORCE_RECIRC_SAME_INDEX 357

#define	PME_ITA2_L2_FORCE_RECIRC_SMC_HIT 358

#define	PME_ITA2_L2_FORCE_RECIRC_SNP_OR_L3 359

#define	PME_ITA2_L2_FORCE_RECIRC_TAG_NOTOK 360

#define	PME_ITA2_L2_FORCE_RECIRC_TRAN_PREF 361

#define	PME_ITA2_L2_FORCE_RECIRC_VIC_BUF_FULL 362

#define	PME_ITA2_L2_FORCE_RECIRC_VIC_PEND 363

#define	PME_ITA2_L2_GOT_RECIRC_IFETCH_ANY 364

#define	PME_ITA2_L2_GOT_RECIRC_OZQ_ACC 365

#define	PME_ITA2_L2_IFET_CANCELS_ANY 366

#define	PME_ITA2_L2_IFET_CANCELS_BYPASS 367

#define	PME_ITA2_L2_IFET_CANCELS_CHG_PRIO 368

#define	PME_ITA2_L2_IFET_CANCELS_DATA_RD 369

#define	PME_ITA2_L2_IFET_CANCELS_DIDNT_RECIR 370

#define	PME_ITA2_L2_IFET_CANCELS_IFETCH_BYP 371

#define	PME_ITA2_L2_IFET_CANCELS_PREEMPT 372

#define	PME_ITA2_L2_IFET_CANCELS_RECIR_OVER_SUB 373

#define	PME_ITA2_L2_IFET_CANCELS_ST_FILL_WB 374

#define	PME_ITA2_L2_INST_DEMAND_READS 375

#define	PME_ITA2_L2_INST_PREFETCHES 376

#define	PME_ITA2_L2_ISSUED_RECIRC_IFETCH_ANY 377

#define	PME_ITA2_L2_ISSUED_RECIRC_OZQ_ACC 378

#define	PME_ITA2_L2_L3ACCESS_CANCEL_ANY 379

#define	PME_ITA2_L2_L3ACCESS_CANCEL_DFETCH 380

#define	PME_ITA2_L2_L3ACCESS_CANCEL_EBL_REJECT 381

#define	PME_ITA2_L2_L3ACCESS_CANCEL_FILLD_FULL 382

#define	PME_ITA2_L2_L3ACCESS_CANCEL_IFETCH 383

#define	PME_ITA2_L2_L3ACCESS_CANCEL_INV_L3_BYP 384

#define	PME_ITA2_L2_L3ACCESS_CANCEL_SPEC_L3_BYP 385

#define	PME_ITA2_L2_L3ACCESS_CANCEL_UC_BLOCKED 386

#define	PME_ITA2_L2_MISSES 387

#define	PME_ITA2_L2_OPS_ISSUED_FP_LOAD 388

#define	PME_ITA2_L2_OPS_ISSUED_INT_LOAD 389

#define	PME_ITA2_L2_OPS_ISSUED_NST_NLD 390

#define	PME_ITA2_L2_OPS_ISSUED_RMW 391

#define	PME_ITA2_L2_OPS_ISSUED_STORE 392

#define	PME_ITA2_L2_OZDB_FULL_THIS 393

#define	PME_ITA2_L2_OZQ_ACQUIRE 394

#define	PME_ITA2_L2_OZQ_CANCELS0_ANY 395

#define	PME_ITA2_L2_OZQ_CANCELS0_LATE_ACQUIRE 396

#define	PME_ITA2_L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE 397

#define	PME_ITA2_L2_OZQ_CANCELS0_LATE_RELEASE 398

#define	PME_ITA2_L2_OZQ_CANCELS0_LATE_SPEC_BYP 399

#define	PME_ITA2_L2_OZQ_CANCELS1_BANK_CONF 400

#define	PME_ITA2_L2_OZQ_CANCELS1_CANC_L2M_ST 401

#define	PME_ITA2_L2_OZQ_CANCELS1_CCV 402

#define	PME_ITA2_L2_OZQ_CANCELS1_ECC 403

#define	PME_ITA2_L2_OZQ_CANCELS1_HPW_IFETCH_CONF 404

#define	PME_ITA2_L2_OZQ_CANCELS1_L1DF_L2M 405

#define	PME_ITA2_L2_OZQ_CANCELS1_L1_FILL_CONF 406

#define	PME_ITA2_L2_OZQ_CANCELS1_L2A_ST_MAT 407

#define	PME_ITA2_L2_OZQ_CANCELS1_L2D_ST_MAT 408

#define	PME_ITA2_L2_OZQ_CANCELS1_L2M_ST_MAT 409

#define	PME_ITA2_L2_OZQ_CANCELS1_MFA 410

#define	PME_ITA2_L2_OZQ_CANCELS1_REL 411

#define	PME_ITA2_L2_OZQ_CANCELS1_SEM 412

#define	PME_ITA2_L2_OZQ_CANCELS1_ST_FILL_CONF 413

#define	PME_ITA2_L2_OZQ_CANCELS1_SYNC 414

#define	PME_ITA2_L2_OZQ_CANCELS2_ACQ 415

#define	PME_ITA2_L2_OZQ_CANCELS2_CANC_L2C_ST 416

#define	PME_ITA2_L2_OZQ_CANCELS2_CANC_L2D_ST 417

#define	PME_ITA2_L2_OZQ_CANCELS2_DIDNT_RECIRC 418

#define	PME_ITA2_L2_OZQ_CANCELS2_D_IFET 419

#define	PME_ITA2_L2_OZQ_CANCELS2_L2C_ST_MAT 420

#define	PME_ITA2_L2_OZQ_CANCELS2_L2FILL_ST_CONF 421

#define	PME_ITA2_L2_OZQ_CANCELS2_OVER_SUB 422

#define	PME_ITA2_L2_OZQ_CANCELS2_OZ_DATA_CONF 423

#define	PME_ITA2_L2_OZQ_CANCELS2_READ_WB_CONF 424

#define	PME_ITA2_L2_OZQ_CANCELS2_RECIRC_OVER_SUB 425

#define	PME_ITA2_L2_OZQ_CANCELS2_SCRUB 426

#define	PME_ITA2_L2_OZQ_CANCELS2_WEIRD 427

#define	PME_ITA2_L2_OZQ_FULL_THIS 428

#define	PME_ITA2_L2_OZQ_RELEASE 429

#define	PME_ITA2_L2_REFERENCES 430

#define	PME_ITA2_L2_STORE_HIT_SHARED_ANY 431

#define	PME_ITA2_L2_SYNTH_PROBE 432

#define	PME_ITA2_L2_VICTIMB_FULL_THIS 433

#define	PME_ITA2_L3_LINES_REPLACED 434

#define	PME_ITA2_L3_MISSES 435

#define	PME_ITA2_L3_READS_ALL_ALL 436

#define	PME_ITA2_L3_READS_ALL_HIT 437

#define	PME_ITA2_L3_READS_ALL_MISS 438

#define	PME_ITA2_L3_READS_DATA_READ_ALL 439

#define	PME_ITA2_L3_READS_DATA_READ_HIT 440

#define	PME_ITA2_L3_READS_DATA_READ_MISS 441

#define	PME_ITA2_L3_READS_DINST_FETCH_ALL 442

#define	PME_ITA2_L3_READS_DINST_FETCH_HIT 443

#define	PME_ITA2_L3_READS_DINST_FETCH_MISS 444

#define	PME_ITA2_L3_READS_INST_FETCH_ALL 445

#define	PME_ITA2_L3_READS_INST_FETCH_HIT 446

#define	PME_ITA2_L3_READS_INST_FETCH_MISS 447

#define	PME_ITA2_L3_REFERENCES 448

#define	PME_ITA2_L3_WRITES_ALL_ALL 449

#define	PME_ITA2_L3_WRITES_ALL_HIT 450

#define	PME_ITA2_L3_WRITES_ALL_MISS 451

#define	PME_ITA2_L3_WRITES_DATA_WRITE_ALL 452

#define	PME_ITA2_L3_WRITES_DATA_WRITE_HIT 453

#define	PME_ITA2_L3_WRITES_DATA_WRITE_MISS 454

#define	PME_ITA2_L3_WRITES_L2_WB_ALL 455

#define	PME_ITA2_L3_WRITES_L2_WB_HIT 456

#define	PME_ITA2_L3_WRITES_L2_WB_MISS 457

#define	PME_ITA2_LOADS_RETIRED 458

#define	PME_ITA2_MEM_READ_CURRENT_ANY 459

#define	PME_ITA2_MEM_READ_CURRENT_IO 460

#define	PME_ITA2_MISALIGNED_LOADS_RETIRED 461

#define	PME_ITA2_MISALIGNED_STORES_RETIRED 462

#define	PME_ITA2_NOPS_RETIRED 463

#define	PME_ITA2_PREDICATE_SQUASHED_RETIRED 464

#define	PME_ITA2_RSE_CURRENT_REGS_2_TO_0 465

#define	PME_ITA2_RSE_CURRENT_REGS_5_TO_3 466

#define	PME_ITA2_RSE_CURRENT_REGS_6 467

#define	PME_ITA2_RSE_DIRTY_REGS_2_TO_0 468

#define	PME_ITA2_RSE_DIRTY_REGS_5_TO_3 469

#define	PME_ITA2_RSE_DIRTY_REGS_6 470

#define	PME_ITA2_RSE_EVENT_RETIRED 471

#define	PME_ITA2_RSE_REFERENCES_RETIRED_ALL 472

#define	PME_ITA2_RSE_REFERENCES_RETIRED_LOAD 473

#define	PME_ITA2_RSE_REFERENCES_RETIRED_STORE 474

#define	PME_ITA2_SERIALIZATION_EVENTS 475

#define	PME_ITA2_STORES_RETIRED 476

#define	PME_ITA2_SYLL_NOT_DISPERSED_ALL 477

#define	PME_ITA2_SYLL_NOT_DISPERSED_EXPL 478

#define	PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE 479

#define	PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI 480

#define	PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 481

#define	PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 482

#define	PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI 483

#define	PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_MLI 484

#define	PME_ITA2_SYLL_NOT_DISPERSED_FE 485

#define	PME_ITA2_SYLL_NOT_DISPERSED_FE_OR_MLI 486

#define	PME_ITA2_SYLL_NOT_DISPERSED_IMPL 487

#define	PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE 488

#define	PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI 489

#define	PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_MLI 490

#define	PME_ITA2_SYLL_NOT_DISPERSED_MLI 491

#define	PME_ITA2_SYLL_OVERCOUNT_ALL 492

#define	PME_ITA2_SYLL_OVERCOUNT_EXPL 493

#define	PME_ITA2_SYLL_OVERCOUNT_IMPL 494

#define	PME_ITA2_UC_LOADS_RETIRED 495

#define	PME_ITA2_UC_STORES_RETIRED 496

#define	PME_ITA2_EVENT_COUNT 497

Variables
static pme_ita2_entry_t	itanium2_pe []

Macro Definition Documentation

◆ PME_ITA2_ALAT_CAPACITY_MISS_ALL

#define PME_ITA2_ALAT_CAPACITY_MISS_ALL 0

◆ PME_ITA2_ALAT_CAPACITY_MISS_FP

#define PME_ITA2_ALAT_CAPACITY_MISS_FP 1

◆ PME_ITA2_ALAT_CAPACITY_MISS_INT

#define PME_ITA2_ALAT_CAPACITY_MISS_INT 2

◆ PME_ITA2_BACK_END_BUBBLE_ALL

#define PME_ITA2_BACK_END_BUBBLE_ALL 3

◆ PME_ITA2_BACK_END_BUBBLE_FE

#define PME_ITA2_BACK_END_BUBBLE_FE 4

◆ PME_ITA2_BACK_END_BUBBLE_L1D_FPU_RSE

#define PME_ITA2_BACK_END_BUBBLE_L1D_FPU_RSE 5

◆ PME_ITA2_BE_BR_MISPRED_DETAIL_ANY

#define PME_ITA2_BE_BR_MISPRED_DETAIL_ANY 6

◆ PME_ITA2_BE_BR_MISPRED_DETAIL_PFS

#define PME_ITA2_BE_BR_MISPRED_DETAIL_PFS 7

◆ PME_ITA2_BE_BR_MISPRED_DETAIL_ROT

#define PME_ITA2_BE_BR_MISPRED_DETAIL_ROT 8

◆ PME_ITA2_BE_BR_MISPRED_DETAIL_STG

#define PME_ITA2_BE_BR_MISPRED_DETAIL_STG 9

◆ PME_ITA2_BE_EXE_BUBBLE_ALL

#define PME_ITA2_BE_EXE_BUBBLE_ALL 10

◆ PME_ITA2_BE_EXE_BUBBLE_ARCR

#define PME_ITA2_BE_EXE_BUBBLE_ARCR 11

◆ PME_ITA2_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK

#define PME_ITA2_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 12

◆ PME_ITA2_BE_EXE_BUBBLE_BANK_SWITCH

#define PME_ITA2_BE_EXE_BUBBLE_BANK_SWITCH 13

◆ PME_ITA2_BE_EXE_BUBBLE_CANCEL

#define PME_ITA2_BE_EXE_BUBBLE_CANCEL 14

◆ PME_ITA2_BE_EXE_BUBBLE_FRALL

#define PME_ITA2_BE_EXE_BUBBLE_FRALL 15

◆ PME_ITA2_BE_EXE_BUBBLE_GRALL

#define PME_ITA2_BE_EXE_BUBBLE_GRALL 16

◆ PME_ITA2_BE_EXE_BUBBLE_GRGR

#define PME_ITA2_BE_EXE_BUBBLE_GRGR 17

◆ PME_ITA2_BE_EXE_BUBBLE_PR

#define PME_ITA2_BE_EXE_BUBBLE_PR 18

◆ PME_ITA2_BE_FLUSH_BUBBLE_ALL

#define PME_ITA2_BE_FLUSH_BUBBLE_ALL 19

◆ PME_ITA2_BE_FLUSH_BUBBLE_BRU

#define PME_ITA2_BE_FLUSH_BUBBLE_BRU 20

◆ PME_ITA2_BE_FLUSH_BUBBLE_XPN

#define PME_ITA2_BE_FLUSH_BUBBLE_XPN 21

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_ALL

#define PME_ITA2_BE_L1D_FPU_BUBBLE_ALL 22

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_FPU

#define PME_ITA2_BE_L1D_FPU_BUBBLE_FPU 23

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D 24

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCS

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCS 25

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCURECIR

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCURECIR 26

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FILLCONF

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 27

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 28

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_HPW

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_HPW 29

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 30

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCHK

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCHK 31

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCONF

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCONF 32

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NAT

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NAT 33

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NATCONF

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NATCONF 34

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 35

◆ PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_TLB

#define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_TLB 36

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_ALL

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_ALL 37

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_BI

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BI 38

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_BR_ILOCK

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 40

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_BRQ

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BRQ 39

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_BUBBLE

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BUBBLE 41

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_FEFLUSH

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FEFLUSH 42

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 43

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_IBFULL

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IBFULL 44

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_IMISS

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IMISS 45

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_PLP

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_PLP 46

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_TLBMISS

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_TLBMISS 47

◆ PME_ITA2_BE_LOST_BW_DUE_TO_FE_UNREACHED

#define PME_ITA2_BE_LOST_BW_DUE_TO_FE_UNREACHED 48

◆ PME_ITA2_BE_RSE_BUBBLE_ALL

#define PME_ITA2_BE_RSE_BUBBLE_ALL 49

◆ PME_ITA2_BE_RSE_BUBBLE_AR_DEP

#define PME_ITA2_BE_RSE_BUBBLE_AR_DEP 50

◆ PME_ITA2_BE_RSE_BUBBLE_BANK_SWITCH

#define PME_ITA2_BE_RSE_BUBBLE_BANK_SWITCH 51

◆ PME_ITA2_BE_RSE_BUBBLE_LOADRS

#define PME_ITA2_BE_RSE_BUBBLE_LOADRS 52

◆ PME_ITA2_BE_RSE_BUBBLE_OVERFLOW

#define PME_ITA2_BE_RSE_BUBBLE_OVERFLOW 53

◆ PME_ITA2_BE_RSE_BUBBLE_UNDERFLOW

#define PME_ITA2_BE_RSE_BUBBLE_UNDERFLOW 54

◆ PME_ITA2_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 72

◆ PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 73

◆ PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 74

◆ PME_ITA2_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 75

◆ PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 76

◆ PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 77

◆ PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 78

◆ PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 79

◆ PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 80

◆ PME_ITA2_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 81

◆ PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 82

◆ PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 83

◆ PME_ITA2_BR_MISPRED_DETAIL_ALL_ALL_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_ALL_ALL_PRED 56

◆ PME_ITA2_BR_MISPRED_DETAIL_ALL_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 57

◆ PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_PATH 58

◆ PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_TARGET

#define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 59

◆ PME_ITA2_BR_MISPRED_DETAIL_IPREL_ALL_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_ALL_PRED 60

◆ PME_ITA2_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 61

◆ PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 62

◆ PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET

#define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 63

◆ PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_ALL_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_ALL_PRED 64

◆ PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED 65

◆ PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH 66

◆ PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET

#define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET 67

◆ PME_ITA2_BR_MISPRED_DETAIL_RETURN_ALL_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_ALL_PRED 68

◆ PME_ITA2_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED

#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 69

◆ PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_PATH

#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 70

◆ PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET

#define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 71

◆ PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 100

◆ PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 101

◆ PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 102

◆ PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 103

◆ PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 104

◆ PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 105

◆ PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 106

◆ PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 107

◆ PME_ITA2_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 84

◆ PME_ITA2_BR_PATH_PRED_ALL_MISPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_TAKEN 85

◆ PME_ITA2_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 86

◆ PME_ITA2_BR_PATH_PRED_ALL_OKPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_TAKEN 87

◆ PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 88

◆ PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_TAKEN 89

◆ PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 90

◆ PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_TAKEN 91

◆ PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 92

◆ PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 93

◆ PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 94

◆ PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 95

◆ PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 96

◆ PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_TAKEN 97

◆ PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN

#define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 98

◆ PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_TAKEN

#define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_TAKEN 99

◆ PME_ITA2_BRANCH_EVENT

#define PME_ITA2_BRANCH_EVENT 55

◆ PME_ITA2_BUS_ALL_ANY

#define PME_ITA2_BUS_ALL_ANY 108

◆ PME_ITA2_BUS_ALL_IO

#define PME_ITA2_BUS_ALL_IO 109

◆ PME_ITA2_BUS_ALL_SELF

#define PME_ITA2_BUS_ALL_SELF 110

◆ PME_ITA2_BUS_BACKSNP_REQ_THIS

#define PME_ITA2_BUS_BACKSNP_REQ_THIS 111

◆ PME_ITA2_BUS_BRQ_LIVE_REQ_HI

#define PME_ITA2_BUS_BRQ_LIVE_REQ_HI 112

◆ PME_ITA2_BUS_BRQ_LIVE_REQ_LO

#define PME_ITA2_BUS_BRQ_LIVE_REQ_LO 113

◆ PME_ITA2_BUS_BRQ_REQ_INSERTED

#define PME_ITA2_BUS_BRQ_REQ_INSERTED 114

◆ PME_ITA2_BUS_DATA_CYCLE

#define PME_ITA2_BUS_DATA_CYCLE 115

◆ PME_ITA2_BUS_HITM

#define PME_ITA2_BUS_HITM 116

◆ PME_ITA2_BUS_IO_ANY

#define PME_ITA2_BUS_IO_ANY 117

◆ PME_ITA2_BUS_IO_IO

#define PME_ITA2_BUS_IO_IO 118

◆ PME_ITA2_BUS_IO_SELF

#define PME_ITA2_BUS_IO_SELF 119

◆ PME_ITA2_BUS_IOQ_LIVE_REQ_HI

#define PME_ITA2_BUS_IOQ_LIVE_REQ_HI 120

◆ PME_ITA2_BUS_IOQ_LIVE_REQ_LO

#define PME_ITA2_BUS_IOQ_LIVE_REQ_LO 121

◆ PME_ITA2_BUS_LOCK_ANY

#define PME_ITA2_BUS_LOCK_ANY 122

◆ PME_ITA2_BUS_LOCK_SELF

#define PME_ITA2_BUS_LOCK_SELF 123

◆ PME_ITA2_BUS_MEM_READ_ALL_ANY

#define PME_ITA2_BUS_MEM_READ_ALL_ANY 133

◆ PME_ITA2_BUS_MEM_READ_ALL_IO

#define PME_ITA2_BUS_MEM_READ_ALL_IO 134

◆ PME_ITA2_BUS_MEM_READ_ALL_SELF

#define PME_ITA2_BUS_MEM_READ_ALL_SELF 135

◆ PME_ITA2_BUS_MEM_READ_BIL_ANY

#define PME_ITA2_BUS_MEM_READ_BIL_ANY 136

◆ PME_ITA2_BUS_MEM_READ_BIL_IO

#define PME_ITA2_BUS_MEM_READ_BIL_IO 137

◆ PME_ITA2_BUS_MEM_READ_BIL_SELF

#define PME_ITA2_BUS_MEM_READ_BIL_SELF 138

◆ PME_ITA2_BUS_MEM_READ_BRIL_ANY

#define PME_ITA2_BUS_MEM_READ_BRIL_ANY 139

◆ PME_ITA2_BUS_MEM_READ_BRIL_IO

#define PME_ITA2_BUS_MEM_READ_BRIL_IO 140

◆ PME_ITA2_BUS_MEM_READ_BRIL_SELF

#define PME_ITA2_BUS_MEM_READ_BRIL_SELF 141

◆ PME_ITA2_BUS_MEM_READ_BRL_ANY

#define PME_ITA2_BUS_MEM_READ_BRL_ANY 142

◆ PME_ITA2_BUS_MEM_READ_BRL_IO

#define PME_ITA2_BUS_MEM_READ_BRL_IO 143

◆ PME_ITA2_BUS_MEM_READ_BRL_SELF

#define PME_ITA2_BUS_MEM_READ_BRL_SELF 144

◆ PME_ITA2_BUS_MEM_READ_OUT_HI

#define PME_ITA2_BUS_MEM_READ_OUT_HI 145

◆ PME_ITA2_BUS_MEM_READ_OUT_LO

#define PME_ITA2_BUS_MEM_READ_OUT_LO 146

◆ PME_ITA2_BUS_MEMORY_ALL_ANY

#define PME_ITA2_BUS_MEMORY_ALL_ANY 124

◆ PME_ITA2_BUS_MEMORY_ALL_IO

#define PME_ITA2_BUS_MEMORY_ALL_IO 125

◆ PME_ITA2_BUS_MEMORY_ALL_SELF

#define PME_ITA2_BUS_MEMORY_ALL_SELF 126

◆ PME_ITA2_BUS_MEMORY_EQ_128BYTE_ANY

#define PME_ITA2_BUS_MEMORY_EQ_128BYTE_ANY 127

◆ PME_ITA2_BUS_MEMORY_EQ_128BYTE_IO

#define PME_ITA2_BUS_MEMORY_EQ_128BYTE_IO 128

◆ PME_ITA2_BUS_MEMORY_EQ_128BYTE_SELF

#define PME_ITA2_BUS_MEMORY_EQ_128BYTE_SELF 129

◆ PME_ITA2_BUS_MEMORY_LT_128BYTE_ANY

#define PME_ITA2_BUS_MEMORY_LT_128BYTE_ANY 130

◆ PME_ITA2_BUS_MEMORY_LT_128BYTE_IO

#define PME_ITA2_BUS_MEMORY_LT_128BYTE_IO 131

◆ PME_ITA2_BUS_MEMORY_LT_128BYTE_SELF

#define PME_ITA2_BUS_MEMORY_LT_128BYTE_SELF 132

◆ PME_ITA2_BUS_OOQ_LIVE_REQ_HI

#define PME_ITA2_BUS_OOQ_LIVE_REQ_HI 147

◆ PME_ITA2_BUS_OOQ_LIVE_REQ_LO

#define PME_ITA2_BUS_OOQ_LIVE_REQ_LO 148

◆ PME_ITA2_BUS_RD_DATA_ANY

#define PME_ITA2_BUS_RD_DATA_ANY 149

◆ PME_ITA2_BUS_RD_DATA_IO

#define PME_ITA2_BUS_RD_DATA_IO 150

◆ PME_ITA2_BUS_RD_DATA_SELF

#define PME_ITA2_BUS_RD_DATA_SELF 151

◆ PME_ITA2_BUS_RD_HIT

#define PME_ITA2_BUS_RD_HIT 152

◆ PME_ITA2_BUS_RD_HITM

#define PME_ITA2_BUS_RD_HITM 153

◆ PME_ITA2_BUS_RD_INVAL_ALL_HITM

#define PME_ITA2_BUS_RD_INVAL_ALL_HITM 154

◆ PME_ITA2_BUS_RD_INVAL_HITM

#define PME_ITA2_BUS_RD_INVAL_HITM 155

◆ PME_ITA2_BUS_RD_IO_ANY

#define PME_ITA2_BUS_RD_IO_ANY 156

◆ PME_ITA2_BUS_RD_IO_IO

#define PME_ITA2_BUS_RD_IO_IO 157

◆ PME_ITA2_BUS_RD_IO_SELF

#define PME_ITA2_BUS_RD_IO_SELF 158

◆ PME_ITA2_BUS_RD_PRTL_ANY

#define PME_ITA2_BUS_RD_PRTL_ANY 159

◆ PME_ITA2_BUS_RD_PRTL_IO

#define PME_ITA2_BUS_RD_PRTL_IO 160

◆ PME_ITA2_BUS_RD_PRTL_SELF

#define PME_ITA2_BUS_RD_PRTL_SELF 161

◆ PME_ITA2_BUS_SNOOP_STALL_CYCLES_ANY

#define PME_ITA2_BUS_SNOOP_STALL_CYCLES_ANY 168

◆ PME_ITA2_BUS_SNOOP_STALL_CYCLES_SELF

#define PME_ITA2_BUS_SNOOP_STALL_CYCLES_SELF 169

◆ PME_ITA2_BUS_SNOOPQ_REQ

#define PME_ITA2_BUS_SNOOPQ_REQ 162

◆ PME_ITA2_BUS_SNOOPS_ANY

#define PME_ITA2_BUS_SNOOPS_ANY 163

◆ PME_ITA2_BUS_SNOOPS_HITM_ANY

#define PME_ITA2_BUS_SNOOPS_HITM_ANY 166

◆ PME_ITA2_BUS_SNOOPS_HITM_SELF

#define PME_ITA2_BUS_SNOOPS_HITM_SELF 167

◆ PME_ITA2_BUS_SNOOPS_IO

#define PME_ITA2_BUS_SNOOPS_IO 164

◆ PME_ITA2_BUS_SNOOPS_SELF

#define PME_ITA2_BUS_SNOOPS_SELF 165

◆ PME_ITA2_BUS_WR_WB_ALL_ANY

#define PME_ITA2_BUS_WR_WB_ALL_ANY 170

◆ PME_ITA2_BUS_WR_WB_ALL_IO

#define PME_ITA2_BUS_WR_WB_ALL_IO 171

◆ PME_ITA2_BUS_WR_WB_ALL_SELF

#define PME_ITA2_BUS_WR_WB_ALL_SELF 172

◆ PME_ITA2_BUS_WR_WB_CCASTOUT_ANY

#define PME_ITA2_BUS_WR_WB_CCASTOUT_ANY 173

◆ PME_ITA2_BUS_WR_WB_CCASTOUT_SELF

#define PME_ITA2_BUS_WR_WB_CCASTOUT_SELF 174

◆ PME_ITA2_BUS_WR_WB_EQ_128BYTE_ANY

#define PME_ITA2_BUS_WR_WB_EQ_128BYTE_ANY 175

◆ PME_ITA2_BUS_WR_WB_EQ_128BYTE_IO

#define PME_ITA2_BUS_WR_WB_EQ_128BYTE_IO 176

◆ PME_ITA2_BUS_WR_WB_EQ_128BYTE_SELF

#define PME_ITA2_BUS_WR_WB_EQ_128BYTE_SELF 177

◆ PME_ITA2_CPU_CPL_CHANGES

#define PME_ITA2_CPU_CPL_CHANGES 178

◆ PME_ITA2_CPU_CYCLES

#define PME_ITA2_CPU_CYCLES 179

◆ PME_ITA2_DATA_DEBUG_REGISTER_FAULT

#define PME_ITA2_DATA_DEBUG_REGISTER_FAULT 180

◆ PME_ITA2_DATA_DEBUG_REGISTER_MATCHES

#define PME_ITA2_DATA_DEBUG_REGISTER_MATCHES 181

◆ PME_ITA2_DATA_EAR_ALAT

#define PME_ITA2_DATA_EAR_ALAT 182

◆ PME_ITA2_DATA_EAR_CACHE_LAT1024

#define PME_ITA2_DATA_EAR_CACHE_LAT1024 183

◆ PME_ITA2_DATA_EAR_CACHE_LAT128

#define PME_ITA2_DATA_EAR_CACHE_LAT128 184

◆ PME_ITA2_DATA_EAR_CACHE_LAT16

#define PME_ITA2_DATA_EAR_CACHE_LAT16 185

◆ PME_ITA2_DATA_EAR_CACHE_LAT2048

#define PME_ITA2_DATA_EAR_CACHE_LAT2048 186

◆ PME_ITA2_DATA_EAR_CACHE_LAT256

#define PME_ITA2_DATA_EAR_CACHE_LAT256 187

◆ PME_ITA2_DATA_EAR_CACHE_LAT32

#define PME_ITA2_DATA_EAR_CACHE_LAT32 188

◆ PME_ITA2_DATA_EAR_CACHE_LAT4

#define PME_ITA2_DATA_EAR_CACHE_LAT4 189

◆ PME_ITA2_DATA_EAR_CACHE_LAT4096

#define PME_ITA2_DATA_EAR_CACHE_LAT4096 190

◆ PME_ITA2_DATA_EAR_CACHE_LAT512

#define PME_ITA2_DATA_EAR_CACHE_LAT512 191

◆ PME_ITA2_DATA_EAR_CACHE_LAT64

#define PME_ITA2_DATA_EAR_CACHE_LAT64 192

◆ PME_ITA2_DATA_EAR_CACHE_LAT8

#define PME_ITA2_DATA_EAR_CACHE_LAT8 193

◆ PME_ITA2_DATA_EAR_EVENTS

#define PME_ITA2_DATA_EAR_EVENTS 194

◆ PME_ITA2_DATA_EAR_TLB_ALL

#define PME_ITA2_DATA_EAR_TLB_ALL 195

◆ PME_ITA2_DATA_EAR_TLB_FAULT

#define PME_ITA2_DATA_EAR_TLB_FAULT 196

◆ PME_ITA2_DATA_EAR_TLB_L2DTLB

#define PME_ITA2_DATA_EAR_TLB_L2DTLB 197

◆ PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_FAULT

#define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_FAULT 198

◆ PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_VHPT

#define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_VHPT 199

◆ PME_ITA2_DATA_EAR_TLB_VHPT

#define PME_ITA2_DATA_EAR_TLB_VHPT 200

◆ PME_ITA2_DATA_EAR_TLB_VHPT_OR_FAULT

#define PME_ITA2_DATA_EAR_TLB_VHPT_OR_FAULT 201

◆ PME_ITA2_DATA_REFERENCES_SET0

#define PME_ITA2_DATA_REFERENCES_SET0 202

◆ PME_ITA2_DATA_REFERENCES_SET1

#define PME_ITA2_DATA_REFERENCES_SET1 203

◆ PME_ITA2_DISP_STALLED

#define PME_ITA2_DISP_STALLED 204

◆ PME_ITA2_DTLB_INSERTS_HPW

#define PME_ITA2_DTLB_INSERTS_HPW 205

◆ PME_ITA2_DTLB_INSERTS_HPW_RETIRED

#define PME_ITA2_DTLB_INSERTS_HPW_RETIRED 206

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 211

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 212

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 213

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 214

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 207

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 208

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 209

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET

#define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 210

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED

#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 215

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED

#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 216

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH

#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 217

◆ PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET

#define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 218

◆ PME_ITA2_EVENT_COUNT

#define PME_ITA2_EVENT_COUNT 497

Definition at line 1027 of file itanium2_events.h.

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_ALL

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_ALL 219

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0 220

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1 221

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2 222

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3 223

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2 224

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3 225

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3 226

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1 227

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2 228

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3 229

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3 230

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2 231

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3 232

◆ PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN3

#define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN3 233

◆ PME_ITA2_EXTERN_DP_PINS_4_TO_5_ALL

#define PME_ITA2_EXTERN_DP_PINS_4_TO_5_ALL 234

◆ PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN4

#define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN4 235

◆ PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN5

#define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN5 236

◆ PME_ITA2_FE_BUBBLE_ALL

#define PME_ITA2_FE_BUBBLE_ALL 237

◆ PME_ITA2_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE

#define PME_ITA2_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 238

◆ PME_ITA2_FE_BUBBLE_ALLBUT_IBFULL

#define PME_ITA2_FE_BUBBLE_ALLBUT_IBFULL 239

◆ PME_ITA2_FE_BUBBLE_BRANCH

#define PME_ITA2_FE_BUBBLE_BRANCH 240

◆ PME_ITA2_FE_BUBBLE_BUBBLE

#define PME_ITA2_FE_BUBBLE_BUBBLE 241

◆ PME_ITA2_FE_BUBBLE_FEFLUSH

#define PME_ITA2_FE_BUBBLE_FEFLUSH 242

◆ PME_ITA2_FE_BUBBLE_FILL_RECIRC

#define PME_ITA2_FE_BUBBLE_FILL_RECIRC 243

◆ PME_ITA2_FE_BUBBLE_GROUP1

#define PME_ITA2_FE_BUBBLE_GROUP1 244

◆ PME_ITA2_FE_BUBBLE_GROUP2

#define PME_ITA2_FE_BUBBLE_GROUP2 245

◆ PME_ITA2_FE_BUBBLE_GROUP3

#define PME_ITA2_FE_BUBBLE_GROUP3 246

◆ PME_ITA2_FE_BUBBLE_IBFULL

#define PME_ITA2_FE_BUBBLE_IBFULL 247

◆ PME_ITA2_FE_BUBBLE_IMISS

#define PME_ITA2_FE_BUBBLE_IMISS 248

◆ PME_ITA2_FE_BUBBLE_TLBMISS

#define PME_ITA2_FE_BUBBLE_TLBMISS 249

◆ PME_ITA2_FE_LOST_BW_ALL

#define PME_ITA2_FE_LOST_BW_ALL 250

◆ PME_ITA2_FE_LOST_BW_BI

#define PME_ITA2_FE_LOST_BW_BI 251

◆ PME_ITA2_FE_LOST_BW_BR_ILOCK

#define PME_ITA2_FE_LOST_BW_BR_ILOCK 253

◆ PME_ITA2_FE_LOST_BW_BRQ

#define PME_ITA2_FE_LOST_BW_BRQ 252

◆ PME_ITA2_FE_LOST_BW_BUBBLE

#define PME_ITA2_FE_LOST_BW_BUBBLE 254

◆ PME_ITA2_FE_LOST_BW_FEFLUSH

#define PME_ITA2_FE_LOST_BW_FEFLUSH 255

◆ PME_ITA2_FE_LOST_BW_FILL_RECIRC

#define PME_ITA2_FE_LOST_BW_FILL_RECIRC 256

◆ PME_ITA2_FE_LOST_BW_IBFULL

#define PME_ITA2_FE_LOST_BW_IBFULL 257

◆ PME_ITA2_FE_LOST_BW_IMISS

#define PME_ITA2_FE_LOST_BW_IMISS 258

◆ PME_ITA2_FE_LOST_BW_PLP

#define PME_ITA2_FE_LOST_BW_PLP 259

◆ PME_ITA2_FE_LOST_BW_TLBMISS

#define PME_ITA2_FE_LOST_BW_TLBMISS 260

◆ PME_ITA2_FE_LOST_BW_UNREACHED

#define PME_ITA2_FE_LOST_BW_UNREACHED 261

◆ PME_ITA2_FP_FAILED_FCHKF

#define PME_ITA2_FP_FAILED_FCHKF 262

◆ PME_ITA2_FP_FALSE_SIRSTALL

#define PME_ITA2_FP_FALSE_SIRSTALL 263

◆ PME_ITA2_FP_FLUSH_TO_ZERO

#define PME_ITA2_FP_FLUSH_TO_ZERO 264

◆ PME_ITA2_FP_OPS_RETIRED

#define PME_ITA2_FP_OPS_RETIRED 265

◆ PME_ITA2_FP_TRUE_SIRSTALL

#define PME_ITA2_FP_TRUE_SIRSTALL 266

◆ PME_ITA2_HPW_DATA_REFERENCES

#define PME_ITA2_HPW_DATA_REFERENCES 267

◆ PME_ITA2_IA32_INST_RETIRED

#define PME_ITA2_IA32_INST_RETIRED 268

◆ PME_ITA2_IA32_ISA_TRANSITIONS

#define PME_ITA2_IA32_ISA_TRANSITIONS 269

◆ PME_ITA2_IA64_INST_RETIRED

#define PME_ITA2_IA64_INST_RETIRED 270

◆ PME_ITA2_IA64_INST_RETIRED_THIS

#define PME_ITA2_IA64_INST_RETIRED_THIS 271

◆ PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8

#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8 272

◆ PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9

#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9 273

◆ PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8

#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8 274

◆ PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9

#define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9 275

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 276

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BI

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 277

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 279

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 278

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 280

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 281

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 282

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 283

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 284

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 285

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 286

◆ PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED

#define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 287

◆ PME_ITA2_INST_CHKA_LDC_ALAT_ALL

#define PME_ITA2_INST_CHKA_LDC_ALAT_ALL 288

◆ PME_ITA2_INST_CHKA_LDC_ALAT_FP

#define PME_ITA2_INST_CHKA_LDC_ALAT_FP 289

◆ PME_ITA2_INST_CHKA_LDC_ALAT_INT

#define PME_ITA2_INST_CHKA_LDC_ALAT_INT 290

◆ PME_ITA2_INST_DISPERSED

#define PME_ITA2_INST_DISPERSED 291

◆ PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_ALL

#define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_ALL 292

◆ PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_FP

#define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_FP 293

◆ PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_INT

#define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_INT 294

◆ PME_ITA2_INST_FAILED_CHKS_RETIRED_ALL

#define PME_ITA2_INST_FAILED_CHKS_RETIRED_ALL 295

◆ PME_ITA2_INST_FAILED_CHKS_RETIRED_FP

#define PME_ITA2_INST_FAILED_CHKS_RETIRED_FP 296

◆ PME_ITA2_INST_FAILED_CHKS_RETIRED_INT

#define PME_ITA2_INST_FAILED_CHKS_RETIRED_INT 297

◆ PME_ITA2_ISB_BUNPAIRS_IN

#define PME_ITA2_ISB_BUNPAIRS_IN 298

◆ PME_ITA2_ITLB_MISSES_FETCH_ALL

#define PME_ITA2_ITLB_MISSES_FETCH_ALL 299

◆ PME_ITA2_ITLB_MISSES_FETCH_L1ITLB

#define PME_ITA2_ITLB_MISSES_FETCH_L1ITLB 300

◆ PME_ITA2_ITLB_MISSES_FETCH_L2ITLB

#define PME_ITA2_ITLB_MISSES_FETCH_L2ITLB 301

◆ PME_ITA2_L1D_READ_MISSES_ALL

#define PME_ITA2_L1D_READ_MISSES_ALL 305

◆ PME_ITA2_L1D_READ_MISSES_RSE_FILL

#define PME_ITA2_L1D_READ_MISSES_RSE_FILL 306

◆ PME_ITA2_L1D_READS_SET0

#define PME_ITA2_L1D_READS_SET0 303

◆ PME_ITA2_L1D_READS_SET1

#define PME_ITA2_L1D_READS_SET1 304

◆ PME_ITA2_L1DTLB_TRANSFER

#define PME_ITA2_L1DTLB_TRANSFER 302

◆ PME_ITA2_L1I_EAR_CACHE_LAT0

#define PME_ITA2_L1I_EAR_CACHE_LAT0 308

◆ PME_ITA2_L1I_EAR_CACHE_LAT1024

#define PME_ITA2_L1I_EAR_CACHE_LAT1024 309

◆ PME_ITA2_L1I_EAR_CACHE_LAT128

#define PME_ITA2_L1I_EAR_CACHE_LAT128 310

◆ PME_ITA2_L1I_EAR_CACHE_LAT16

#define PME_ITA2_L1I_EAR_CACHE_LAT16 311

◆ PME_ITA2_L1I_EAR_CACHE_LAT256

#define PME_ITA2_L1I_EAR_CACHE_LAT256 312

◆ PME_ITA2_L1I_EAR_CACHE_LAT32

#define PME_ITA2_L1I_EAR_CACHE_LAT32 313

◆ PME_ITA2_L1I_EAR_CACHE_LAT4

#define PME_ITA2_L1I_EAR_CACHE_LAT4 314

◆ PME_ITA2_L1I_EAR_CACHE_LAT4096

#define PME_ITA2_L1I_EAR_CACHE_LAT4096 315

◆ PME_ITA2_L1I_EAR_CACHE_LAT8

#define PME_ITA2_L1I_EAR_CACHE_LAT8 316

◆ PME_ITA2_L1I_EAR_CACHE_RAB

#define PME_ITA2_L1I_EAR_CACHE_RAB 317

◆ PME_ITA2_L1I_EAR_EVENTS

#define PME_ITA2_L1I_EAR_EVENTS 318

◆ PME_ITA2_L1I_EAR_TLB_ALL

#define PME_ITA2_L1I_EAR_TLB_ALL 319

◆ PME_ITA2_L1I_EAR_TLB_FAULT

#define PME_ITA2_L1I_EAR_TLB_FAULT 320

◆ PME_ITA2_L1I_EAR_TLB_L2TLB

#define PME_ITA2_L1I_EAR_TLB_L2TLB 321

◆ PME_ITA2_L1I_EAR_TLB_L2TLB_OR_FAULT

#define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_FAULT 322

◆ PME_ITA2_L1I_EAR_TLB_L2TLB_OR_VHPT

#define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_VHPT 323

◆ PME_ITA2_L1I_EAR_TLB_VHPT

#define PME_ITA2_L1I_EAR_TLB_VHPT 324

◆ PME_ITA2_L1I_EAR_TLB_VHPT_OR_FAULT

#define PME_ITA2_L1I_EAR_TLB_VHPT_OR_FAULT 325

◆ PME_ITA2_L1I_FETCH_ISB_HIT

#define PME_ITA2_L1I_FETCH_ISB_HIT 326

◆ PME_ITA2_L1I_FETCH_RAB_HIT

#define PME_ITA2_L1I_FETCH_RAB_HIT 327

◆ PME_ITA2_L1I_FILLS

#define PME_ITA2_L1I_FILLS 328

◆ PME_ITA2_L1I_PREFETCH_STALL_ALL

#define PME_ITA2_L1I_PREFETCH_STALL_ALL 330

◆ PME_ITA2_L1I_PREFETCH_STALL_FLOW

#define PME_ITA2_L1I_PREFETCH_STALL_FLOW 331

◆ PME_ITA2_L1I_PREFETCHES

#define PME_ITA2_L1I_PREFETCHES 329

◆ PME_ITA2_L1I_PURGE

#define PME_ITA2_L1I_PURGE 332

◆ PME_ITA2_L1I_PVAB_OVERFLOW

#define PME_ITA2_L1I_PVAB_OVERFLOW 333

◆ PME_ITA2_L1I_RAB_ALMOST_FULL

#define PME_ITA2_L1I_RAB_ALMOST_FULL 334

◆ PME_ITA2_L1I_RAB_FULL

#define PME_ITA2_L1I_RAB_FULL 335

◆ PME_ITA2_L1I_READS

#define PME_ITA2_L1I_READS 336

◆ PME_ITA2_L1I_SNOOP

#define PME_ITA2_L1I_SNOOP 337

◆ PME_ITA2_L1I_STRM_PREFETCHES

#define PME_ITA2_L1I_STRM_PREFETCHES 338

◆ PME_ITA2_L1ITLB_INSERTS_HPW

#define PME_ITA2_L1ITLB_INSERTS_HPW 307

◆ PME_ITA2_L2_BAD_LINES_SELECTED_ANY

#define PME_ITA2_L2_BAD_LINES_SELECTED_ANY 340

◆ PME_ITA2_L2_BYPASS_L2_DATA1

#define PME_ITA2_L2_BYPASS_L2_DATA1 341

◆ PME_ITA2_L2_BYPASS_L2_DATA2

#define PME_ITA2_L2_BYPASS_L2_DATA2 342

◆ PME_ITA2_L2_BYPASS_L2_INST1

#define PME_ITA2_L2_BYPASS_L2_INST1 343

◆ PME_ITA2_L2_BYPASS_L2_INST2

#define PME_ITA2_L2_BYPASS_L2_INST2 344

◆ PME_ITA2_L2_BYPASS_L3_DATA1

#define PME_ITA2_L2_BYPASS_L3_DATA1 345

◆ PME_ITA2_L2_BYPASS_L3_INST1

#define PME_ITA2_L2_BYPASS_L3_INST1 346

◆ PME_ITA2_L2_DATA_REFERENCES_L2_ALL

#define PME_ITA2_L2_DATA_REFERENCES_L2_ALL 347

◆ PME_ITA2_L2_DATA_REFERENCES_L2_DATA_READS

#define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_READS 348

◆ PME_ITA2_L2_DATA_REFERENCES_L2_DATA_WRITES

#define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_WRITES 349

◆ PME_ITA2_L2_FILLB_FULL_THIS

#define PME_ITA2_L2_FILLB_FULL_THIS 350

◆ PME_ITA2_L2_FORCE_RECIRC_ANY

#define PME_ITA2_L2_FORCE_RECIRC_ANY 351

◆ PME_ITA2_L2_FORCE_RECIRC_FILL_HIT

#define PME_ITA2_L2_FORCE_RECIRC_FILL_HIT 352

◆ PME_ITA2_L2_FORCE_RECIRC_FRC_RECIRC

#define PME_ITA2_L2_FORCE_RECIRC_FRC_RECIRC 353

◆ PME_ITA2_L2_FORCE_RECIRC_IPF_MISS

#define PME_ITA2_L2_FORCE_RECIRC_IPF_MISS 354

◆ PME_ITA2_L2_FORCE_RECIRC_L1W

#define PME_ITA2_L2_FORCE_RECIRC_L1W 355

◆ PME_ITA2_L2_FORCE_RECIRC_OZQ_MISS

#define PME_ITA2_L2_FORCE_RECIRC_OZQ_MISS 356

◆ PME_ITA2_L2_FORCE_RECIRC_SAME_INDEX

#define PME_ITA2_L2_FORCE_RECIRC_SAME_INDEX 357

◆ PME_ITA2_L2_FORCE_RECIRC_SMC_HIT

#define PME_ITA2_L2_FORCE_RECIRC_SMC_HIT 358

◆ PME_ITA2_L2_FORCE_RECIRC_SNP_OR_L3

#define PME_ITA2_L2_FORCE_RECIRC_SNP_OR_L3 359

◆ PME_ITA2_L2_FORCE_RECIRC_TAG_NOTOK

#define PME_ITA2_L2_FORCE_RECIRC_TAG_NOTOK 360

◆ PME_ITA2_L2_FORCE_RECIRC_TRAN_PREF

#define PME_ITA2_L2_FORCE_RECIRC_TRAN_PREF 361

◆ PME_ITA2_L2_FORCE_RECIRC_VIC_BUF_FULL

#define PME_ITA2_L2_FORCE_RECIRC_VIC_BUF_FULL 362

◆ PME_ITA2_L2_FORCE_RECIRC_VIC_PEND

#define PME_ITA2_L2_FORCE_RECIRC_VIC_PEND 363

◆ PME_ITA2_L2_GOT_RECIRC_IFETCH_ANY

#define PME_ITA2_L2_GOT_RECIRC_IFETCH_ANY 364

◆ PME_ITA2_L2_GOT_RECIRC_OZQ_ACC

#define PME_ITA2_L2_GOT_RECIRC_OZQ_ACC 365

◆ PME_ITA2_L2_IFET_CANCELS_ANY

#define PME_ITA2_L2_IFET_CANCELS_ANY 366

◆ PME_ITA2_L2_IFET_CANCELS_BYPASS

#define PME_ITA2_L2_IFET_CANCELS_BYPASS 367

◆ PME_ITA2_L2_IFET_CANCELS_CHG_PRIO

#define PME_ITA2_L2_IFET_CANCELS_CHG_PRIO 368

◆ PME_ITA2_L2_IFET_CANCELS_DATA_RD

#define PME_ITA2_L2_IFET_CANCELS_DATA_RD 369

◆ PME_ITA2_L2_IFET_CANCELS_DIDNT_RECIR

#define PME_ITA2_L2_IFET_CANCELS_DIDNT_RECIR 370

◆ PME_ITA2_L2_IFET_CANCELS_IFETCH_BYP

#define PME_ITA2_L2_IFET_CANCELS_IFETCH_BYP 371

◆ PME_ITA2_L2_IFET_CANCELS_PREEMPT

#define PME_ITA2_L2_IFET_CANCELS_PREEMPT 372

◆ PME_ITA2_L2_IFET_CANCELS_RECIR_OVER_SUB

#define PME_ITA2_L2_IFET_CANCELS_RECIR_OVER_SUB 373

◆ PME_ITA2_L2_IFET_CANCELS_ST_FILL_WB

#define PME_ITA2_L2_IFET_CANCELS_ST_FILL_WB 374

◆ PME_ITA2_L2_INST_DEMAND_READS

#define PME_ITA2_L2_INST_DEMAND_READS 375

◆ PME_ITA2_L2_INST_PREFETCHES

#define PME_ITA2_L2_INST_PREFETCHES 376

◆ PME_ITA2_L2_ISSUED_RECIRC_IFETCH_ANY

#define PME_ITA2_L2_ISSUED_RECIRC_IFETCH_ANY 377

◆ PME_ITA2_L2_ISSUED_RECIRC_OZQ_ACC

#define PME_ITA2_L2_ISSUED_RECIRC_OZQ_ACC 378

◆ PME_ITA2_L2_L3ACCESS_CANCEL_ANY

#define PME_ITA2_L2_L3ACCESS_CANCEL_ANY 379

◆ PME_ITA2_L2_L3ACCESS_CANCEL_DFETCH

#define PME_ITA2_L2_L3ACCESS_CANCEL_DFETCH 380

◆ PME_ITA2_L2_L3ACCESS_CANCEL_EBL_REJECT

#define PME_ITA2_L2_L3ACCESS_CANCEL_EBL_REJECT 381

◆ PME_ITA2_L2_L3ACCESS_CANCEL_FILLD_FULL

#define PME_ITA2_L2_L3ACCESS_CANCEL_FILLD_FULL 382

◆ PME_ITA2_L2_L3ACCESS_CANCEL_IFETCH

#define PME_ITA2_L2_L3ACCESS_CANCEL_IFETCH 383

◆ PME_ITA2_L2_L3ACCESS_CANCEL_INV_L3_BYP

#define PME_ITA2_L2_L3ACCESS_CANCEL_INV_L3_BYP 384

◆ PME_ITA2_L2_L3ACCESS_CANCEL_SPEC_L3_BYP

#define PME_ITA2_L2_L3ACCESS_CANCEL_SPEC_L3_BYP 385

◆ PME_ITA2_L2_L3ACCESS_CANCEL_UC_BLOCKED

#define PME_ITA2_L2_L3ACCESS_CANCEL_UC_BLOCKED 386

◆ PME_ITA2_L2_MISSES

#define PME_ITA2_L2_MISSES 387

◆ PME_ITA2_L2_OPS_ISSUED_FP_LOAD

#define PME_ITA2_L2_OPS_ISSUED_FP_LOAD 388

◆ PME_ITA2_L2_OPS_ISSUED_INT_LOAD

#define PME_ITA2_L2_OPS_ISSUED_INT_LOAD 389

◆ PME_ITA2_L2_OPS_ISSUED_NST_NLD

#define PME_ITA2_L2_OPS_ISSUED_NST_NLD 390

◆ PME_ITA2_L2_OPS_ISSUED_RMW

#define PME_ITA2_L2_OPS_ISSUED_RMW 391

◆ PME_ITA2_L2_OPS_ISSUED_STORE

#define PME_ITA2_L2_OPS_ISSUED_STORE 392

◆ PME_ITA2_L2_OZDB_FULL_THIS

#define PME_ITA2_L2_OZDB_FULL_THIS 393

◆ PME_ITA2_L2_OZQ_ACQUIRE

#define PME_ITA2_L2_OZQ_ACQUIRE 394

◆ PME_ITA2_L2_OZQ_CANCELS0_ANY

#define PME_ITA2_L2_OZQ_CANCELS0_ANY 395

◆ PME_ITA2_L2_OZQ_CANCELS0_LATE_ACQUIRE

#define PME_ITA2_L2_OZQ_CANCELS0_LATE_ACQUIRE 396

◆ PME_ITA2_L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE

#define PME_ITA2_L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE 397

◆ PME_ITA2_L2_OZQ_CANCELS0_LATE_RELEASE

#define PME_ITA2_L2_OZQ_CANCELS0_LATE_RELEASE 398

◆ PME_ITA2_L2_OZQ_CANCELS0_LATE_SPEC_BYP

#define PME_ITA2_L2_OZQ_CANCELS0_LATE_SPEC_BYP 399

◆ PME_ITA2_L2_OZQ_CANCELS1_BANK_CONF

#define PME_ITA2_L2_OZQ_CANCELS1_BANK_CONF 400

◆ PME_ITA2_L2_OZQ_CANCELS1_CANC_L2M_ST

#define PME_ITA2_L2_OZQ_CANCELS1_CANC_L2M_ST 401

◆ PME_ITA2_L2_OZQ_CANCELS1_CCV

#define PME_ITA2_L2_OZQ_CANCELS1_CCV 402

◆ PME_ITA2_L2_OZQ_CANCELS1_ECC

#define PME_ITA2_L2_OZQ_CANCELS1_ECC 403

◆ PME_ITA2_L2_OZQ_CANCELS1_HPW_IFETCH_CONF

#define PME_ITA2_L2_OZQ_CANCELS1_HPW_IFETCH_CONF 404

◆ PME_ITA2_L2_OZQ_CANCELS1_L1_FILL_CONF

#define PME_ITA2_L2_OZQ_CANCELS1_L1_FILL_CONF 406

◆ PME_ITA2_L2_OZQ_CANCELS1_L1DF_L2M

#define PME_ITA2_L2_OZQ_CANCELS1_L1DF_L2M 405

◆ PME_ITA2_L2_OZQ_CANCELS1_L2A_ST_MAT

#define PME_ITA2_L2_OZQ_CANCELS1_L2A_ST_MAT 407

◆ PME_ITA2_L2_OZQ_CANCELS1_L2D_ST_MAT

#define PME_ITA2_L2_OZQ_CANCELS1_L2D_ST_MAT 408

◆ PME_ITA2_L2_OZQ_CANCELS1_L2M_ST_MAT

#define PME_ITA2_L2_OZQ_CANCELS1_L2M_ST_MAT 409

◆ PME_ITA2_L2_OZQ_CANCELS1_MFA

#define PME_ITA2_L2_OZQ_CANCELS1_MFA 410

◆ PME_ITA2_L2_OZQ_CANCELS1_REL

#define PME_ITA2_L2_OZQ_CANCELS1_REL 411

◆ PME_ITA2_L2_OZQ_CANCELS1_SEM

#define PME_ITA2_L2_OZQ_CANCELS1_SEM 412

◆ PME_ITA2_L2_OZQ_CANCELS1_ST_FILL_CONF

#define PME_ITA2_L2_OZQ_CANCELS1_ST_FILL_CONF 413

◆ PME_ITA2_L2_OZQ_CANCELS1_SYNC

#define PME_ITA2_L2_OZQ_CANCELS1_SYNC 414

◆ PME_ITA2_L2_OZQ_CANCELS2_ACQ

#define PME_ITA2_L2_OZQ_CANCELS2_ACQ 415

◆ PME_ITA2_L2_OZQ_CANCELS2_CANC_L2C_ST

#define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2C_ST 416

◆ PME_ITA2_L2_OZQ_CANCELS2_CANC_L2D_ST

#define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2D_ST 417

◆ PME_ITA2_L2_OZQ_CANCELS2_D_IFET

#define PME_ITA2_L2_OZQ_CANCELS2_D_IFET 419

◆ PME_ITA2_L2_OZQ_CANCELS2_DIDNT_RECIRC

#define PME_ITA2_L2_OZQ_CANCELS2_DIDNT_RECIRC 418

◆ PME_ITA2_L2_OZQ_CANCELS2_L2C_ST_MAT

#define PME_ITA2_L2_OZQ_CANCELS2_L2C_ST_MAT 420

◆ PME_ITA2_L2_OZQ_CANCELS2_L2FILL_ST_CONF

#define PME_ITA2_L2_OZQ_CANCELS2_L2FILL_ST_CONF 421

◆ PME_ITA2_L2_OZQ_CANCELS2_OVER_SUB

#define PME_ITA2_L2_OZQ_CANCELS2_OVER_SUB 422

◆ PME_ITA2_L2_OZQ_CANCELS2_OZ_DATA_CONF

#define PME_ITA2_L2_OZQ_CANCELS2_OZ_DATA_CONF 423

◆ PME_ITA2_L2_OZQ_CANCELS2_READ_WB_CONF

#define PME_ITA2_L2_OZQ_CANCELS2_READ_WB_CONF 424

◆ PME_ITA2_L2_OZQ_CANCELS2_RECIRC_OVER_SUB

#define PME_ITA2_L2_OZQ_CANCELS2_RECIRC_OVER_SUB 425

◆ PME_ITA2_L2_OZQ_CANCELS2_SCRUB

#define PME_ITA2_L2_OZQ_CANCELS2_SCRUB 426

◆ PME_ITA2_L2_OZQ_CANCELS2_WEIRD

#define PME_ITA2_L2_OZQ_CANCELS2_WEIRD 427

◆ PME_ITA2_L2_OZQ_FULL_THIS

#define PME_ITA2_L2_OZQ_FULL_THIS 428

◆ PME_ITA2_L2_OZQ_RELEASE

#define PME_ITA2_L2_OZQ_RELEASE 429

◆ PME_ITA2_L2_REFERENCES

#define PME_ITA2_L2_REFERENCES 430

◆ PME_ITA2_L2_STORE_HIT_SHARED_ANY

#define PME_ITA2_L2_STORE_HIT_SHARED_ANY 431

◆ PME_ITA2_L2_SYNTH_PROBE

#define PME_ITA2_L2_SYNTH_PROBE 432

◆ PME_ITA2_L2_VICTIMB_FULL_THIS

#define PME_ITA2_L2_VICTIMB_FULL_THIS 433

◆ PME_ITA2_L2DTLB_MISSES

#define PME_ITA2_L2DTLB_MISSES 339

◆ PME_ITA2_L3_LINES_REPLACED

#define PME_ITA2_L3_LINES_REPLACED 434

◆ PME_ITA2_L3_MISSES

#define PME_ITA2_L3_MISSES 435

◆ PME_ITA2_L3_READS_ALL_ALL

#define PME_ITA2_L3_READS_ALL_ALL 436

◆ PME_ITA2_L3_READS_ALL_HIT

#define PME_ITA2_L3_READS_ALL_HIT 437

◆ PME_ITA2_L3_READS_ALL_MISS

#define PME_ITA2_L3_READS_ALL_MISS 438

◆ PME_ITA2_L3_READS_DATA_READ_ALL

#define PME_ITA2_L3_READS_DATA_READ_ALL 439

◆ PME_ITA2_L3_READS_DATA_READ_HIT

#define PME_ITA2_L3_READS_DATA_READ_HIT 440

◆ PME_ITA2_L3_READS_DATA_READ_MISS

#define PME_ITA2_L3_READS_DATA_READ_MISS 441

◆ PME_ITA2_L3_READS_DINST_FETCH_ALL

#define PME_ITA2_L3_READS_DINST_FETCH_ALL 442

◆ PME_ITA2_L3_READS_DINST_FETCH_HIT

#define PME_ITA2_L3_READS_DINST_FETCH_HIT 443

◆ PME_ITA2_L3_READS_DINST_FETCH_MISS

#define PME_ITA2_L3_READS_DINST_FETCH_MISS 444

◆ PME_ITA2_L3_READS_INST_FETCH_ALL

#define PME_ITA2_L3_READS_INST_FETCH_ALL 445

◆ PME_ITA2_L3_READS_INST_FETCH_HIT

#define PME_ITA2_L3_READS_INST_FETCH_HIT 446

◆ PME_ITA2_L3_READS_INST_FETCH_MISS

#define PME_ITA2_L3_READS_INST_FETCH_MISS 447

◆ PME_ITA2_L3_REFERENCES

#define PME_ITA2_L3_REFERENCES 448

◆ PME_ITA2_L3_WRITES_ALL_ALL

#define PME_ITA2_L3_WRITES_ALL_ALL 449

◆ PME_ITA2_L3_WRITES_ALL_HIT

#define PME_ITA2_L3_WRITES_ALL_HIT 450

◆ PME_ITA2_L3_WRITES_ALL_MISS

#define PME_ITA2_L3_WRITES_ALL_MISS 451

◆ PME_ITA2_L3_WRITES_DATA_WRITE_ALL

#define PME_ITA2_L3_WRITES_DATA_WRITE_ALL 452

◆ PME_ITA2_L3_WRITES_DATA_WRITE_HIT

#define PME_ITA2_L3_WRITES_DATA_WRITE_HIT 453

◆ PME_ITA2_L3_WRITES_DATA_WRITE_MISS

#define PME_ITA2_L3_WRITES_DATA_WRITE_MISS 454

◆ PME_ITA2_L3_WRITES_L2_WB_ALL

#define PME_ITA2_L3_WRITES_L2_WB_ALL 455

◆ PME_ITA2_L3_WRITES_L2_WB_HIT

#define PME_ITA2_L3_WRITES_L2_WB_HIT 456

◆ PME_ITA2_L3_WRITES_L2_WB_MISS

#define PME_ITA2_L3_WRITES_L2_WB_MISS 457

◆ PME_ITA2_LOADS_RETIRED

#define PME_ITA2_LOADS_RETIRED 458

◆ PME_ITA2_MEM_READ_CURRENT_ANY

#define PME_ITA2_MEM_READ_CURRENT_ANY 459

◆ PME_ITA2_MEM_READ_CURRENT_IO

#define PME_ITA2_MEM_READ_CURRENT_IO 460

◆ PME_ITA2_MISALIGNED_LOADS_RETIRED

#define PME_ITA2_MISALIGNED_LOADS_RETIRED 461

◆ PME_ITA2_MISALIGNED_STORES_RETIRED

#define PME_ITA2_MISALIGNED_STORES_RETIRED 462

◆ PME_ITA2_NOPS_RETIRED

#define PME_ITA2_NOPS_RETIRED 463

◆ PME_ITA2_PREDICATE_SQUASHED_RETIRED

#define PME_ITA2_PREDICATE_SQUASHED_RETIRED 464

◆ PME_ITA2_RSE_CURRENT_REGS_2_TO_0

#define PME_ITA2_RSE_CURRENT_REGS_2_TO_0 465

◆ PME_ITA2_RSE_CURRENT_REGS_5_TO_3

#define PME_ITA2_RSE_CURRENT_REGS_5_TO_3 466

◆ PME_ITA2_RSE_CURRENT_REGS_6

#define PME_ITA2_RSE_CURRENT_REGS_6 467

◆ PME_ITA2_RSE_DIRTY_REGS_2_TO_0

#define PME_ITA2_RSE_DIRTY_REGS_2_TO_0 468

◆ PME_ITA2_RSE_DIRTY_REGS_5_TO_3

#define PME_ITA2_RSE_DIRTY_REGS_5_TO_3 469

◆ PME_ITA2_RSE_DIRTY_REGS_6

#define PME_ITA2_RSE_DIRTY_REGS_6 470

◆ PME_ITA2_RSE_EVENT_RETIRED

#define PME_ITA2_RSE_EVENT_RETIRED 471

◆ PME_ITA2_RSE_REFERENCES_RETIRED_ALL

#define PME_ITA2_RSE_REFERENCES_RETIRED_ALL 472

◆ PME_ITA2_RSE_REFERENCES_RETIRED_LOAD

#define PME_ITA2_RSE_REFERENCES_RETIRED_LOAD 473

◆ PME_ITA2_RSE_REFERENCES_RETIRED_STORE

#define PME_ITA2_RSE_REFERENCES_RETIRED_STORE 474

◆ PME_ITA2_SERIALIZATION_EVENTS

#define PME_ITA2_SERIALIZATION_EVENTS 475

◆ PME_ITA2_STORES_RETIRED

#define PME_ITA2_STORES_RETIRED 476

◆ PME_ITA2_SYLL_NOT_DISPERSED_ALL

#define PME_ITA2_SYLL_NOT_DISPERSED_ALL 477

◆ PME_ITA2_SYLL_NOT_DISPERSED_EXPL

#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL 478

◆ PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE

#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE 479

◆ PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI

#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI 480

◆ PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL

#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 481

◆ PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE

#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 482

◆ PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI

#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI 483

◆ PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_MLI

#define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_MLI 484

◆ PME_ITA2_SYLL_NOT_DISPERSED_FE

#define PME_ITA2_SYLL_NOT_DISPERSED_FE 485

◆ PME_ITA2_SYLL_NOT_DISPERSED_FE_OR_MLI

#define PME_ITA2_SYLL_NOT_DISPERSED_FE_OR_MLI 486

◆ PME_ITA2_SYLL_NOT_DISPERSED_IMPL

#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL 487

◆ PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE

#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE 488

◆ PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI

#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI 489

◆ PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_MLI

#define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_MLI 490

◆ PME_ITA2_SYLL_NOT_DISPERSED_MLI

#define PME_ITA2_SYLL_NOT_DISPERSED_MLI 491

◆ PME_ITA2_SYLL_OVERCOUNT_ALL

#define PME_ITA2_SYLL_OVERCOUNT_ALL 492

◆ PME_ITA2_SYLL_OVERCOUNT_EXPL

#define PME_ITA2_SYLL_OVERCOUNT_EXPL 493

◆ PME_ITA2_SYLL_OVERCOUNT_IMPL

#define PME_ITA2_SYLL_OVERCOUNT_IMPL 494

◆ PME_ITA2_UC_LOADS_RETIRED

#define PME_ITA2_UC_LOADS_RETIRED 495

◆ PME_ITA2_UC_STORES_RETIRED

#define PME_ITA2_UC_STORES_RETIRED 496

Variable Documentation

◆ itanium2_pe

pme_ita2_entry_t itanium2_pe[]

static

Definition at line 31 of file itanium2_events.h.

Macros

Variables