PAPI 7.1.0.0
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amd64_events_fam15h.h
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1/*
2 * Copyright (c) 2010 Advanced Micro Devices, Inc.
3 * Contributed by Robert Richter <robert.richter@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
16 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
17 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
18 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
19 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * This file is part of libpfm, a performance monitoring support library for
23 * applications on Linux.
24 */
25
26/*
27 * Family 15h Microarchitecture performance monitor events
28 *
29 * History:
30 *
31 * Apr 29 2011 -- Robert Richter, robert.richter@amd.com:
32 * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors,
33 * 42301, Rev 1.15, April 18, 2011
34 *
35 * Dec 09 2010 -- Robert Richter, robert.richter@amd.com:
36 * Source: BIOS and Kernel Developer's Guide for the AMD Family 15h
37 * Processors, Rev 0.90, May 18, 2010
38 */
39
40static pme_amd64_entry_t amd64_fam15h_pe[]={
41
42/* Family 15h */
43
44/* 0 */{.pme_name = "DISPATCHED_FPU_OPS",
45 .pme_code = 0x00,
46 .pme_desc = "FPU Pipe Assignment",
47 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
48 .pme_numasks = 9,
49 .pme_umasks = {
50 { .pme_uname = "OPS_PIPE0",
51 .pme_udesc = "Total number uops assigned to Pipe 0",
52 .pme_ucode = 1 << 0,
53 },
54 { .pme_uname = "OPS_PIPE1",
55 .pme_udesc = "Total number uops assigned to Pipe 1",
56 .pme_ucode = 1 << 1,
57 },
58 { .pme_uname = "OPS_PIPE2",
59 .pme_udesc = "Total number uops assigned to Pipe 2",
60 .pme_ucode = 1 << 2,
61 },
62 { .pme_uname = "OPS_PIPE3",
63 .pme_udesc = "Total number uops assigned to Pipe 3",
64 .pme_ucode = 1 << 3,
65 },
66 { .pme_uname = "OPS_DUAL_PIPE0",
67 .pme_udesc = "Total number dual-pipe uops assigned to Pipe 0",
68 .pme_ucode = 1 << 4,
69 },
70 { .pme_uname = "OPS_DUAL_PIPE1",
71 .pme_udesc = "Total number dual-pipe uops assigned to Pipe 1",
72 .pme_ucode = 1 << 5,
73 },
74 { .pme_uname = "OPS_DUAL_PIPE2",
75 .pme_udesc = "Total number dual-pipe uops assigned to Pipe 2",
76 .pme_ucode = 1 << 6,
77 },
78 { .pme_uname = "OPS_DUAL_PIPE3",
79 .pme_udesc = "Total number dual-pipe uops assigned to Pipe 3",
80 .pme_ucode = 1 << 7,
81 },
82 { .pme_uname = "ALL",
83 .pme_udesc = "All sub-events selected",
84 .pme_ucode = 0xFF,
85 },
86 },
87 },
88/* 1 */{.pme_name = "CYCLES_FPU_EMPTY",
89 .pme_code = 0x01,
90 .pme_desc = "FP Scheduler Empty",
91 },
92/* 2 */{.pme_name = "RETIRED_SSE_OPS",
93 .pme_code = 0x03,
94 .pme_desc = "Retired SSE/BNI Ops",
95 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
96 .pme_numasks = 9,
97 .pme_umasks = {
98 { .pme_uname = "SINGLE_ADD_SUB_OPS",
99 .pme_udesc = "Single-precision add/subtract FLOPS",
100 .pme_ucode = 1 << 0,
101 },
102 { .pme_uname = "SINGLE_MUL_OPS",
103 .pme_udesc = "Single-precision multiply FLOPS",
104 .pme_ucode = 1 << 1,
105 },
106 { .pme_uname = "SINGLE_DIV_OPS",
107 .pme_udesc = "Single-precision divide/square root FLOPS",
108 .pme_ucode = 1 << 2,
109 },
110 { .pme_uname = "SINGLE_MUL_ADD_OPS",
111 .pme_udesc = "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
112 .pme_ucode = 1 << 3,
113 },
114 { .pme_uname = "DOUBLE_ADD_SUB_OPS",
115 .pme_udesc = "Double precision add/subtract FLOPS",
116 .pme_ucode = 1 << 4,
117 },
118 { .pme_uname = "DOUBLE_MUL_OPS",
119 .pme_udesc = "Double precision multiply FLOPS",
120 .pme_ucode = 1 << 5,
121 },
122 { .pme_uname = "DOUBLE_DIV_OPS",
123 .pme_udesc = "Double precision divide/square root FLOPS",
124 .pme_ucode = 1 << 6,
125 },
126 { .pme_uname = "DOUBLE_MUL_ADD_OPS",
127 .pme_udesc = "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
128 .pme_ucode = 1 << 7,
129 },
130 { .pme_uname = "ALL",
131 .pme_udesc = "All sub-events selected",
132 .pme_ucode = 0xFF,
133 },
134 },
135 },
136/* 3 */{.pme_name = "MOVE_SCALAR_OPTIMIZATION",
137 .pme_code = 0x04,
138 .pme_desc = "Number of Move Elimination and Scalar Op Optimization",
139 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
140 .pme_numasks = 5,
141 .pme_umasks = {
142 { .pme_uname = "SSE_MOVE_OPS",
143 .pme_udesc = "Number of SSE Move Ops",
144 .pme_ucode = 1 << 0,
145 },
146 { .pme_uname = "SSE_MOVE_OPS_ELIM",
147 .pme_udesc = "Number of SSE Move Ops eliminated",
148 .pme_ucode = 1 << 1,
149 },
150 { .pme_uname = "OPT_CAND",
151 .pme_udesc = "Number of Ops that are candidates for optimization (Z-bit set or pass)",
152 .pme_ucode = 1 << 2,
153 },
154 { .pme_uname = "SCALAR_OPS_OPTIMIZED",
155 .pme_udesc = "Number of Scalar ops optimized",
156 .pme_ucode = 1 << 3,
157 },
158 { .pme_uname = "ALL",
159 .pme_udesc = "All sub-events selected",
160 .pme_ucode = 0x0F,
161 },
162 },
163 },
164/* 4 */{.pme_name = "RETIRED_SERIALIZING_OPS",
165 .pme_code = 0x05,
166 .pme_desc = "Retired Serializing Ops",
167 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
168 .pme_numasks = 5,
169 .pme_umasks = {
170 { .pme_uname = "SSE_RETIRED",
171 .pme_udesc = "SSE bottom-executing uops retired",
172 .pme_ucode = 1 << 0,
173 },
174 { .pme_uname = "SSE_MISPREDICTED",
175 .pme_udesc = "SSE control word mispredict traps due to mispredictions",
176 .pme_ucode = 1 << 1,
177 },
178 { .pme_uname = "X87_RETIRED",
179 .pme_udesc = "x87 bottom-executing uops retired",
180 .pme_ucode = 1 << 2,
181 },
182 { .pme_uname = "X87_MISPREDICTED",
183 .pme_udesc = "x87 control word mispredict traps due to mispredictions",
184 .pme_ucode = 1 << 3,
185 },
186 { .pme_uname = "ALL",
187 .pme_udesc = "All sub-events selected",
188 .pme_ucode = 0x0F,
189 },
190 },
191 },
192/* 5 */{.pme_name = "BOTTOM_EXECUTE_OP",
193 .pme_code = 0x06,
194 .pme_desc = "Number of Cycles that a Bottom-Execute uop is in the FP Scheduler",
195 },
196/* 6 */{.pme_name = "SEGMENT_REGISTER_LOADS",
197 .pme_code = 0x20,
198 .pme_desc = "Segment Register Loads",
199 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
200 .pme_numasks = 8,
201 .pme_umasks = {
202 { .pme_uname = "ES",
203 .pme_udesc = "ES",
204 .pme_ucode = 1 << 0,
205 },
206 { .pme_uname = "CS",
207 .pme_udesc = "CS",
208 .pme_ucode = 1 << 1,
209 },
210 { .pme_uname = "SS",
211 .pme_udesc = "SS",
212 .pme_ucode = 1 << 2,
213 },
214 { .pme_uname = "DS",
215 .pme_udesc = "DS",
216 .pme_ucode = 1 << 3,
217 },
218 { .pme_uname = "FS",
219 .pme_udesc = "FS",
220 .pme_ucode = 1 << 4,
221 },
222 { .pme_uname = "GS",
223 .pme_udesc = "GS",
224 .pme_ucode = 1 << 5,
225 },
226 { .pme_uname = "HS",
227 .pme_udesc = "HS",
228 .pme_ucode = 1 << 6,
229 },
230 { .pme_uname = "ALL",
231 .pme_udesc = "All sub-events selected",
232 .pme_ucode = 0x7F,
233 },
234 },
235 },
236/* 7 */{.pme_name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
237 .pme_code = 0x21,
238 .pme_desc = "Pipeline Restart Due to Self-Modifying Code",
239 },
240/* 8 */{.pme_name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
241 .pme_code = 0x22,
242 .pme_desc = "Pipeline Restart Due to Probe Hit",
243 },
244/* 9 */{.pme_name = "LOAD_Q_STORE_Q_FULL",
245 .pme_code = 0x23,
246 .pme_desc = "Load Queue/Store Queue Full",
247 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
248 .pme_numasks = 3,
249 .pme_umasks = {
250 { .pme_uname = "LOAD_QUEUE",
251 .pme_udesc = "The number of cycles that the load buffer is full",
252 .pme_ucode = 1 << 0,
253 },
254 { .pme_uname = "STORE_QUEUE",
255 .pme_udesc = "The number of cycles that the store buffer is full",
256 .pme_ucode = 1 << 1,
257 },
258 { .pme_uname = "ALL",
259 .pme_udesc = "All sub-events selected",
260 .pme_ucode = 0x03,
261 },
262 },
263 },
264/* 10 */{.pme_name = "LOCKED_OPS",
265 .pme_code = 0x24,
266 .pme_desc = "Locked Operations",
267 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
268 .pme_numasks = 4,
269 .pme_umasks = {
270 { .pme_uname = "EXECUTED",
271 .pme_udesc = "Number of locked instructions executed",
272 .pme_ucode = 1 << 0,
273 },
274 { .pme_uname = "CYCLES_NON_SPECULATIVE_PHASE",
275 .pme_udesc = "Number of cycles spent in non-speculative phase, excluding cache miss penalty",
276 .pme_ucode = 1 << 2,
277 },
278 { .pme_uname = "CYCLES_WAITING",
279 .pme_udesc = "Number of cycles spent in non-speculative phase, including the cache miss penalty",
280 .pme_ucode = 1 << 3,
281 },
282 { .pme_uname = "ALL",
283 .pme_udesc = "All sub-events selected",
284 .pme_ucode = 0x0D,
285 },
286 },
287 },
288/* 11 */{.pme_name = "RETIRED_CLFLUSH_INSTRUCTIONS",
289 .pme_code = 0x26,
290 .pme_desc = "Retired CLFLUSH Instructions",
291 },
292/* 12 */{.pme_name = "RETIRED_CPUID_INSTRUCTIONS",
293 .pme_code = 0x27,
294 .pme_desc = "Retired CPUID Instructions",
295 },
296/* 13 */{.pme_name = "CANCELLED_STORE_TO_LOAD",
297 .pme_code = 0x2A,
298 .pme_desc = "Canceled Store to Load Forward Operations",
299 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
300 .pme_numasks = 2,
301 .pme_umasks = {
302 { .pme_uname = "SIZE_ADDRESS_MISMATCHES",
303 .pme_udesc = "Store is smaller than load or different starting byte but partial overlap",
304 .pme_ucode = 1 << 0,
305 },
306 { .pme_uname = "ALL",
307 .pme_udesc = "All sub-events selected",
308 .pme_ucode = 0x01,
309 },
310 },
311 },
312/* 14 */{.pme_name = "SMIS_RECEIVED",
313 .pme_code = 0x2B,
314 .pme_desc = "SMIs Received",
315 },
316/* 15 */{.pme_name = "DATA_CACHE_ACCESSES",
317 .pme_code = 0x40,
318 .pme_desc = "Data Cache Accesses",
319 },
320/* 16 */{.pme_name = "DATA_CACHE_MISSES",
321 .pme_code = 0x41,
322 .pme_desc = "Data Cache Misses",
323 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
324 .pme_numasks = 3,
325 .pme_umasks = {
326 { .pme_uname = "DC_MISS_STREAMING_STORE",
327 .pme_udesc = "First data cache miss or streaming store to a 64B cache line",
328 .pme_ucode = 1 << 0,
329 },
330 { .pme_uname = "STREAMING_STORE",
331 .pme_udesc = "First streaming store to a 64B cache line",
332 .pme_ucode = 1 << 1,
333 },
334 { .pme_uname = "ALL",
335 .pme_udesc = "All sub-events selected",
336 .pme_ucode = 0x03,
337 },
338 },
339 },
340/* 17 */{.pme_name = "DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE",
341 .pme_code = 0x42,
342 .pme_desc = "Data Cache Refills from L2 or System",
343 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
344 .pme_numasks = 5,
345 .pme_umasks = {
346 { .pme_uname = "GOOD",
347 .pme_udesc = "Fill with good data. (Final valid status is valid)",
348 .pme_ucode = 1 << 0,
349 },
350 { .pme_uname = "INVALID",
351 .pme_udesc = "Early valid status turned out to be invalid",
352 .pme_ucode = 1 << 1,
353 },
354 { .pme_uname = "POISON",
355 .pme_udesc = "Fill with poison data",
356 .pme_ucode = 1 << 2,
357 },
358 { .pme_uname = "READ_ERROR",
359 .pme_udesc = "Fill with read data error",
360 .pme_ucode = 1 << 3,
361 },
362 { .pme_uname = "ALL",
363 .pme_udesc = "All sub-events selected",
364 .pme_ucode = 0x0F,
365 },
366 },
367 },
368/* 18 */{.pme_name = "DATA_CACHE_REFILLS_FROM_NORTHBRIDGE",
369 .pme_code = 0x43,
370 .pme_desc = "Data Cache Refills from System",
371 },
372/* 19 */{.pme_name = "UNIFIED_TLB_HIT",
373 .pme_code = 0x45,
374 .pme_desc = "Unified TLB Hit",
375 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
376 .pme_numasks = 7,
377 .pme_umasks = {
378 { .pme_uname = "4K_DATA",
379 .pme_udesc = "4 KB unified TLB hit for data",
380 .pme_ucode = 1 << 0,
381 },
382 { .pme_uname = "2M_DATA",
383 .pme_udesc = "2 MB unified TLB hit for data",
384 .pme_ucode = 1 << 1,
385 },
386 { .pme_uname = "1G_DATA",
387 .pme_udesc = "1 GB unified TLB hit for data",
388 .pme_ucode = 1 << 2,
389 },
390 { .pme_uname = "4K_INST",
391 .pme_udesc = "4 KB unified TLB hit for instruction",
392 .pme_ucode = 1 << 4,
393 },
394 { .pme_uname = "2M_INST",
395 .pme_udesc = "2 MB unified TLB hit for instruction",
396 .pme_ucode = 1 << 5,
397 },
398 { .pme_uname = "1G_INST",
399 .pme_udesc = "1 GB unified TLB hit for instruction",
400 .pme_ucode = 1 << 6,
401 },
402 { .pme_uname = "ALL",
403 .pme_udesc = "All sub-events selected",
404 .pme_ucode = 0x77,
405 },
406 },
407 },
408/* 20 */{.pme_name = "UNIFIED_TLB_MISS",
409 .pme_code = 0x46,
410 .pme_desc = "Unified TLB Miss",
411 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
412 .pme_numasks = 7,
413 .pme_umasks = {
414 { .pme_uname = "4K_DATA",
415 .pme_udesc = "4 KB unified TLB miss for data",
416 .pme_ucode = 1 << 0,
417 },
418 { .pme_uname = "2M_DATA",
419 .pme_udesc = "2 MB unified TLB miss for data",
420 .pme_ucode = 1 << 1,
421 },
422 { .pme_uname = "1GB_DATA",
423 .pme_udesc = "1 GB unified TLB miss for data",
424 .pme_ucode = 1 << 2,
425 },
426 { .pme_uname = "4K_INST",
427 .pme_udesc = "4 KB unified TLB miss for instruction",
428 .pme_ucode = 1 << 4,
429 },
430 { .pme_uname = "2M_INST",
431 .pme_udesc = "2 MB unified TLB miss for instruction",
432 .pme_ucode = 1 << 5,
433 },
434 { .pme_uname = "1G_INST",
435 .pme_udesc = "1 GB unified TLB miss for instruction",
436 .pme_ucode = 1 << 6,
437 },
438 { .pme_uname = "ALL",
439 .pme_udesc = "All sub-events selected",
440 .pme_ucode = 0x77,
441 },
442 },
443 },
444/* 21 */{.pme_name = "MISALIGNED_ACCESSES",
445 .pme_code = 0x47,
446 .pme_desc = "Misaligned Accesses",
447 },
448/* 22 */{.pme_name = "PREFETCH_INSTRUCTIONS_DISPATCHED",
449 .pme_code = 0x4B,
450 .pme_desc = "Prefetch Instructions Dispatched",
451 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
452 .pme_numasks = 4,
453 .pme_umasks = {
454 { .pme_uname = "LOAD",
455 .pme_udesc = "Load (Prefetch, PrefetchT0/T1/T2)",
456 .pme_ucode = 1 << 0,
457 },
458 { .pme_uname = "STORE",
459 .pme_udesc = "Store (PrefetchW)",
460 .pme_ucode = 1 << 1,
461 },
462 { .pme_uname = "NTA",
463 .pme_udesc = "NTA (PrefetchNTA)",
464 .pme_ucode = 1 << 2,
465 },
466 { .pme_uname = "ALL",
467 .pme_udesc = "All sub-events selected",
468 .pme_ucode = 0x07,
469 },
470 },
471 },
472/* 23 */{.pme_name = "INEFFECTIVE_SW_PREFETCHES",
473 .pme_code = 0x52,
474 .pme_desc = "Ineffective Software Prefetches",
475 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
476 .pme_numasks = 3,
477 .pme_umasks = {
478 { .pme_uname = "SW_PREFETCH_HIT_IN_L1",
479 .pme_udesc = "Software prefetch hit in the L1",
480 .pme_ucode = 1 << 0,
481 },
482 { .pme_uname = "SW_PREFETCH_HIT_IN_L2",
483 .pme_udesc = "Software prefetch hit in the L2",
484 .pme_ucode = 1 << 3,
485 },
486 { .pme_uname = "ALL",
487 .pme_udesc = "All sub-events selected",
488 .pme_ucode = 0x09,
489 },
490 },
491 },
492/* 24 */{.pme_name = "MEMORY_REQUESTS",
493 .pme_code = 0x65,
494 .pme_desc = "Memory Requests by Type",
495 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
496 .pme_numasks = 4,
497 .pme_umasks = {
498 { .pme_uname = "NON_CACHEABLE",
499 .pme_udesc = "Requests to non-cacheable (UC) memory",
500 .pme_ucode = 1 << 0,
501 },
502 { .pme_uname = "WRITE_COMBINING",
503 .pme_udesc = "Requests to non-cacheable (WC, but not WC+/SS) memory",
504 .pme_ucode = 1 << 1,
505 },
506 { .pme_uname = "STREAMING_STORE",
507 .pme_udesc = "Requests to non-cacheable (WC+/SS, but not WC) memory",
508 .pme_ucode = 1 << 7,
509 },
510 { .pme_uname = "ALL",
511 .pme_udesc = "All sub-events selected",
512 .pme_ucode = 0x83,
513 },
514 },
515 },
516/* 25 */{.pme_name = "DATA_PREFETCHER",
517 .pme_code = 0x67,
518 .pme_desc = "Data Prefetcher",
519 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
520 .pme_numasks = 2,
521 .pme_umasks = {
522 { .pme_uname = "ATTEMPTED",
523 .pme_udesc = "Prefetch attempts",
524 .pme_ucode = 1 << 1,
525 },
526 { .pme_uname = "ALL",
527 .pme_udesc = "All sub-events selected",
528 .pme_ucode = 0x02,
529 },
530 },
531 },
532/* 26 */{.pme_name = "MAB_REQS",
533 .pme_code = 0x68,
534 .pme_desc = "MAB Requests",
535 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
536 .pme_numasks = 9,
537 .pme_umasks = {
538 { .pme_uname = "BUFFER_BIT_0",
539 .pme_udesc = "Buffer entry index bit 0",
540 .pme_ucode = 1 << 0,
541 },
542 { .pme_uname = "BUFFER_BIT_1",
543 .pme_udesc = "Buffer entry index bit 1",
544 .pme_ucode = 1 << 1,
545 },
546 { .pme_uname = "BUFFER_BIT_2",
547 .pme_udesc = "Buffer entry index bit 2",
548 .pme_ucode = 1 << 2,
549 },
550 { .pme_uname = "BUFFER_BIT_3",
551 .pme_udesc = "Buffer entry index bit 3",
552 .pme_ucode = 1 << 3,
553 },
554 { .pme_uname = "BUFFER_BIT_4",
555 .pme_udesc = "Buffer entry index bit 4",
556 .pme_ucode = 1 << 4,
557 },
558 { .pme_uname = "BUFFER_BIT_5",
559 .pme_udesc = "Buffer entry index bit 5",
560 .pme_ucode = 1 << 5,
561 },
562 { .pme_uname = "BUFFER_BIT_6",
563 .pme_udesc = "Buffer entry index bit 6",
564 .pme_ucode = 1 << 6,
565 },
566 { .pme_uname = "BUFFER_BIT_7",
567 .pme_udesc = "Buffer entry index bit 7",
568 .pme_ucode = 1 << 7,
569 },
570 { .pme_uname = "ALL",
571 .pme_udesc = "All sub-events selected",
572 .pme_ucode = 0xFF,
573 },
574 },
575 },
576/* 27 */{.pme_name = "MAB_WAIT",
577 .pme_code = 0x69,
578 .pme_desc = "MAB Wait Cycles",
579 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
580 .pme_numasks = 9,
581 .pme_umasks = {
582 { .pme_uname = "BUFFER_BIT_0",
583 .pme_udesc = "Buffer entry index bit 0",
584 .pme_ucode = 1 << 0,
585 },
586 { .pme_uname = "BUFFER_BIT_1",
587 .pme_udesc = "Buffer entry index bit 1",
588 .pme_ucode = 1 << 1,
589 },
590 { .pme_uname = "BUFFER_BIT_2",
591 .pme_udesc = "Buffer entry index bit 2",
592 .pme_ucode = 1 << 2,
593 },
594 { .pme_uname = "BUFFER_BIT_3",
595 .pme_udesc = "Buffer entry index bit 3",
596 .pme_ucode = 1 << 3,
597 },
598 { .pme_uname = "BUFFER_BIT_4",
599 .pme_udesc = "Buffer entry index bit 4",
600 .pme_ucode = 1 << 4,
601 },
602 { .pme_uname = "BUFFER_BIT_5",
603 .pme_udesc = "Buffer entry index bit 5",
604 .pme_ucode = 1 << 5,
605 },
606 { .pme_uname = "BUFFER_BIT_6",
607 .pme_udesc = "Buffer entry index bit 6",
608 .pme_ucode = 1 << 6,
609 },
610 { .pme_uname = "BUFFER_BIT_7",
611 .pme_udesc = "Buffer entry index bit 7",
612 .pme_ucode = 1 << 7,
613 },
614 { .pme_uname = "ALL",
615 .pme_udesc = "All sub-events selected",
616 .pme_ucode = 0xFF,
617 },
618 },
619 },
620/* 28 */{.pme_name = "SYSTEM_READ_RESPONSES",
621 .pme_code = 0x6C,
622 .pme_desc = "Response From System on Cache Refills",
623 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
624 .pme_numasks = 7,
625 .pme_umasks = {
626 { .pme_uname = "EXCLUSIVE",
627 .pme_udesc = "Exclusive",
628 .pme_ucode = 1 << 0,
629 },
630 { .pme_uname = "MODIFIED",
631 .pme_udesc = "Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)",
632 .pme_ucode = 1 << 1,
633 },
634 { .pme_uname = "SHARED",
635 .pme_udesc = "Shared",
636 .pme_ucode = 1 << 2,
637 },
638 { .pme_uname = "OWNED",
639 .pme_udesc = "Owned",
640 .pme_ucode = 1 << 3,
641 },
642 { .pme_uname = "DATA_ERROR",
643 .pme_udesc = "Data Error",
644 .pme_ucode = 1 << 4,
645 },
646 { .pme_uname = "MODIFIED_UNWRITTEN",
647 .pme_udesc = "Modified unwritten",
648 .pme_ucode = 1 << 5,
649 },
650 { .pme_uname = "ALL",
651 .pme_udesc = "All sub-events selected",
652 .pme_ucode = 0x3F,
653 },
654 },
655 },
656/* 29 */{.pme_name = "OCTWORD_WRITE_TRANSFERS",
657 .pme_code = 0x6D,
658 .pme_desc = "Octwords Written to System",
659 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
660 .pme_numasks = 2,
661 .pme_umasks = {
662 { .pme_uname = "OCTWORD_WRITE_TRANSFER",
663 .pme_udesc = "OW write transfer",
664 .pme_ucode = 1 << 0,
665 },
666 { .pme_uname = "ALL",
667 .pme_udesc = "All sub-events selected",
668 .pme_ucode = 0x01,
669 },
670 },
671 },
672/* 30 */{.pme_name = "CPU_CLK_UNHALTED",
673 .pme_code = 0x76,
674 .pme_desc = "CPU Clocks not Halted",
675 },
676/* 31 */{.pme_name = "REQUESTS_TO_L2",
677 .pme_code = 0x7D,
678 .pme_desc = "Requests to L2 Cache",
679 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
680 .pme_numasks = 7,
681 .pme_umasks = {
682 { .pme_uname = "INSTRUCTIONS",
683 .pme_udesc = "IC fill",
684 .pme_ucode = 1 << 0,
685 },
686 { .pme_uname = "DATA",
687 .pme_udesc = "DC fill",
688 .pme_ucode = 1 << 1,
689 },
690 { .pme_uname = "TLB_WALK",
691 .pme_udesc = "TLB fill (page table walks)",
692 .pme_ucode = 1 << 2,
693 },
694 { .pme_uname = "SNOOP",
695 .pme_udesc = "NB probe request",
696 .pme_ucode = 1 << 3,
697 },
698 { .pme_uname = "CANCELLED",
699 .pme_udesc = "Canceled request",
700 .pme_ucode = 1 << 4,
701 },
702 { .pme_uname = "PREFETCHER",
703 .pme_udesc = "L2 cache prefetcher request",
704 .pme_ucode = 1 << 6,
705 },
706 { .pme_uname = "ALL",
707 .pme_udesc = "All sub-events selected",
708 .pme_ucode = 0x5F,
709 },
710 },
711 },
712/* 32 */{.pme_name = "L2_CACHE_MISS",
713 .pme_code = 0x7E,
714 .pme_desc = "L2 Cache Misses",
715 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
716 .pme_numasks = 5,
717 .pme_umasks = {
718 { .pme_uname = "INSTRUCTIONS",
719 .pme_udesc = "IC fill",
720 .pme_ucode = 1 << 0,
721 },
722 { .pme_uname = "DATA",
723 .pme_udesc = "DC fill (includes possible replays, whereas PMCx041 does not)",
724 .pme_ucode = 1 << 1,
725 },
726 { .pme_uname = "TLB_WALK",
727 .pme_udesc = "TLB page table walk",
728 .pme_ucode = 1 << 2,
729 },
730 { .pme_uname = "PREFETCHER",
731 .pme_udesc = "L2 Cache Prefetcher request",
732 .pme_ucode = 1 << 4,
733 },
734 { .pme_uname = "ALL",
735 .pme_udesc = "All sub-events selected",
736 .pme_ucode = 0x17,
737 },
738 },
739 },
740/* 33 */{.pme_name = "L2_CACHE_FILL_WRITEBACK",
741 .pme_code = 0x7F,
742 .pme_desc = "L2 Fill/Writeback",
743 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
744 .pme_numasks = 4,
745 .pme_umasks = {
746 { .pme_uname = "L2_FILLS",
747 .pme_udesc = "L2 fills from system",
748 .pme_ucode = 1 << 0,
749 },
750 { .pme_uname = "L2_WRITEBACKS",
751 .pme_udesc = "L2 Writebacks to system (Clean and Dirty)",
752 .pme_ucode = 1 << 1,
753 },
754 { .pme_uname = "L2_WRITEBACKS_CLEAN",
755 .pme_udesc = "L2 Clean Writebacks to system",
756 .pme_ucode = 1 << 2,
757 },
758 { .pme_uname = "ALL",
759 .pme_udesc = "All sub-events selected",
760 .pme_ucode = 0x07,
761 },
762 },
763 },
764/* 34 */{.pme_name = "PAGE_SPLINTERING",
765 .pme_code = 0x165,
766 .pme_desc = "Page Splintering",
767 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
768 .pme_numasks = 4,
769 .pme_umasks = {
770 { .pme_uname = "GUEST_LARGER",
771 .pme_udesc = "Guest page size is larger than host page size when nested paging is enabled",
772 .pme_ucode = 1 << 0,
773 },
774 { .pme_uname = "MTRR_MISMATCH",
775 .pme_udesc = "Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region",
776 .pme_ucode = 1 << 1,
777 },
778 { .pme_uname = "HOST_LARGER",
779 .pme_udesc = "Host page size is larger than the guest page size",
780 .pme_ucode = 1 << 2,
781 },
782 { .pme_uname = "ALL",
783 .pme_udesc = "All sub-events selected",
784 .pme_ucode = 0x07,
785 },
786 },
787 },
788/* 35 */{.pme_name = "INSTRUCTION_CACHE_FETCHES",
789 .pme_code = 0x80,
790 .pme_desc = "Instruction Cache Fetches",
791 },
792/* 36 */{.pme_name = "INSTRUCTION_CACHE_MISSES",
793 .pme_code = 0x81,
794 .pme_desc = "Instruction Cache Misses",
795 },
796/* 37 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
797 .pme_code = 0x82,
798 .pme_desc = "Instruction Cache Refills from L2",
799 },
800/* 38 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
801 .pme_code = 0x83,
802 .pme_desc = "Instruction Cache Refills from System",
803 },
804/* 39 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
805 .pme_code = 0x84,
806 .pme_desc = "L1 ITLB Miss, L2 ITLB Hit",
807 },
808/* 40 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
809 .pme_code = 0x85,
810 .pme_desc = "L1 ITLB Miss, L2 ITLB Miss",
811 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
812 .pme_numasks = 4,
813 .pme_umasks = {
814 { .pme_uname = "4K_PAGE_FETCHES",
815 .pme_udesc = "Instruction fetches to a 4 KB page",
816 .pme_ucode = 1 << 0,
817 },
818 { .pme_uname = "2M_PAGE_FETCHES",
819 .pme_udesc = "Instruction fetches to a 2 MB page",
820 .pme_ucode = 1 << 1,
821 },
822 { .pme_uname = "1G_PAGE_FETCHES",
823 .pme_udesc = "Instruction fetches to a 1 GB page",
824 .pme_ucode = 1 << 2,
825 },
826 { .pme_uname = "ALL",
827 .pme_udesc = "All sub-events selected",
828 .pme_ucode = 0x07,
829 },
830 },
831 },
832/* 41 */{.pme_name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
833 .pme_code = 0x86,
834 .pme_desc = "Pipeline Restart Due to Instruction Stream Probe",
835 },
836/* 42 */{.pme_name = "INSTRUCTION_FETCH_STALL",
837 .pme_code = 0x87,
838 .pme_desc = "Instruction Fetch Stall",
839 },
840/* 43 */{.pme_name = "RETURN_STACK_HITS",
841 .pme_code = 0x88,
842 .pme_desc = "Return Stack Hits",
843 },
844/* 44 */{.pme_name = "RETURN_STACK_OVERFLOWS",
845 .pme_code = 0x89,
846 .pme_desc = "Return Stack Overflows",
847 },
848/* 45 */{.pme_name = "INSTRUCTION_CACHE_VICTIMS",
849 .pme_code = 0x8B,
850 .pme_desc = "Instruction Cache Victims",
851 },
852/* 46 */{.pme_name = "INSTRUCTION_CACHE_INVALIDATED",
853 .pme_code = 0x8C,
854 .pme_desc = "Instruction Cache Lines Invalidated",
855 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
856 .pme_numasks = 5,
857 .pme_umasks = {
858 { .pme_uname = "NON_SMC_PROBE_MISS",
859 .pme_udesc = "Non-SMC invalidating probe that missed on in-flight instructions",
860 .pme_ucode = 1 << 0,
861 },
862 { .pme_uname = "NON_SMC_PROBE_HIT",
863 .pme_udesc = "Non-SMC invalidating probe that hit on in-flight instructions",
864 .pme_ucode = 1 << 1,
865 },
866 { .pme_uname = "SMC_PROBE_MISS",
867 .pme_udesc = "SMC invalidating probe that missed on in-flight instructions",
868 .pme_ucode = 1 << 2,
869 },
870 { .pme_uname = "SMC_PROBE_HIT",
871 .pme_udesc = "SMC invalidating probe that hit on in-flight instructions",
872 .pme_ucode = 1 << 3,
873 },
874 { .pme_uname = "ALL",
875 .pme_udesc = "All sub-events selected",
876 .pme_ucode = 0x0F,
877 },
878 },
879 },
880/* 47 */{.pme_name = "ITLB_RELOADS",
881 .pme_code = 0x99,
882 .pme_desc = "ITLB Reloads",
883 },
884/* 48 */{.pme_name = "ITLB_RELOADS_ABORTED",
885 .pme_code = 0x9A,
886 .pme_desc = "ITLB Reloads Aborted",
887 },
888/* 49 */{.pme_name = "RETIRED_INSTRUCTIONS",
889 .pme_code = 0xC0,
890 .pme_desc = "Retired Instructions",
891 },
892/* 50 */{.pme_name = "RETIRED_UOPS",
893 .pme_code = 0xC1,
894 .pme_desc = "Retired uops",
895 },
896/* 51 */{.pme_name = "RETIRED_BRANCH_INSTRUCTIONS",
897 .pme_code = 0xC2,
898 .pme_desc = "Retired Branch Instructions",
899 },
900/* 52 */{.pme_name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
901 .pme_code = 0xC3,
902 .pme_desc = "Retired Mispredicted Branch Instructions",
903 },
904/* 53 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
905 .pme_code = 0xC4,
906 .pme_desc = "Retired Taken Branch Instructions",
907 },
908/* 54 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
909 .pme_code = 0xC5,
910 .pme_desc = "Retired Taken Branch Instructions Mispredicted",
911 },
912/* 55 */{.pme_name = "RETIRED_FAR_CONTROL_TRANSFERS",
913 .pme_code = 0xC6,
914 .pme_desc = "Retired Far Control Transfers",
915 },
916/* 56 */{.pme_name = "RETIRED_BRANCH_RESYNCS",
917 .pme_code = 0xC7,
918 .pme_desc = "Retired Branch Resyncs",
919 },
920/* 57 */{.pme_name = "RETIRED_NEAR_RETURNS",
921 .pme_code = 0xC8,
922 .pme_desc = "Retired Near Returns",
923 },
924/* 58 */{.pme_name = "RETIRED_NEAR_RETURNS_MISPREDICTED",
925 .pme_code = 0xC9,
926 .pme_desc = "Retired Near Returns Mispredicted",
927 },
928/* 59 */{.pme_name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
929 .pme_code = 0xCA,
930 .pme_desc = "Retired Indirect Branches Mispredicted",
931 },
932/* 60 */{.pme_name = "RETIRED_MMX_FP_INSTRUCTIONS",
933 .pme_code = 0xCB,
934 .pme_desc = "Retired MMX/FP Instructions",
935 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
936 .pme_numasks = 4,
937 .pme_umasks = {
938 { .pme_uname = "X87",
939 .pme_udesc = "x87 instructions",
940 .pme_ucode = 1 << 0,
941 },
942 { .pme_uname = "MMX",
943 .pme_udesc = "MMX(tm) instructions",
944 .pme_ucode = 1 << 1,
945 },
946 { .pme_uname = "SSE",
947 .pme_udesc = "SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)",
948 .pme_ucode = 1 << 2,
949 },
950 { .pme_uname = "ALL",
951 .pme_udesc = "All sub-events selected",
952 .pme_ucode = 0x07,
953 },
954 },
955 },
956/* 61 */{.pme_name = "INTERRUPTS_MASKED_CYCLES",
957 .pme_code = 0xCD,
958 .pme_desc = "Interrupts-Masked Cycles",
959 },
960/* 62 */{.pme_name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
961 .pme_code = 0xCE,
962 .pme_desc = "Interrupts-Masked Cycles with Interrupt Pending",
963 },
964/* 63 */{.pme_name = "INTERRUPTS_TAKEN",
965 .pme_code = 0xCF,
966 .pme_desc = "Interrupts Taken",
967 },
968/* 64 */{.pme_name = "DECODER_EMPTY",
969 .pme_code = 0xD0,
970 .pme_desc = "Decoder Empty",
971 },
972/* 65 */{.pme_name = "DISPATCH_STALLS",
973 .pme_code = 0xD1,
974 .pme_desc = "Dispatch Stalls",
975 },
976/* 66 */{.pme_name = "DISPATCH_STALL_FOR_SERIALIZATION",
977 .pme_code = 0xD3,
978 .pme_desc = "Microsequencer Stall due to Serialization",
979 },
980/* 67 */{.pme_name = "DISPATCH_STALL_FOR_RETIRE_QUEUE_FULL",
981 .pme_code = 0xD5,
982 .pme_desc = "Dispatch Stall for Instruction Retire Q Full",
983 },
984/* 68 */{.pme_name = "DISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULL",
985 .pme_code = 0xD6,
986 .pme_desc = "Dispatch Stall for Integer Scheduler Queue Full",
987 },
988/* 69 */{.pme_name = "DISPATCH_STALL_FOR_FPU_FULL",
989 .pme_code = 0xD7,
990 .pme_desc = "Dispatch Stall for FP Scheduler Queue Full",
991 },
992/* 70 */{.pme_name = "DISPATCH_STALL_FOR_LDQ_FULL",
993 .pme_code = 0xD8,
994 .pme_desc = "Dispatch Stall for LDQ Full",
995 },
996/* 71 */{.pme_name = "MICROSEQ_STALL_WAITING_FOR_ALL_QUIET",
997 .pme_code = 0xD9,
998 .pme_desc = "Microsequencer Stall Waiting for All Quiet",
999 },
1000/* 72 */{.pme_name = "FPU_EXCEPTIONS",
1001 .pme_code = 0xDB,
1002 .pme_desc = "FPU Exceptions",
1003 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1004 .pme_numasks = 6,
1005 .pme_umasks = {
1006 { .pme_uname = "TOTAL_FAULTS",
1007 .pme_udesc = "Total microfaults",
1008 .pme_ucode = 1 << 0,
1009 },
1010 { .pme_uname = "TOTAL_TRAPS",
1011 .pme_udesc = "Total microtraps",
1012 .pme_ucode = 1 << 1,
1013 },
1014 { .pme_uname = "INT2EXT_FAULTS",
1015 .pme_udesc = "Int2Ext faults",
1016 .pme_ucode = 1 << 2,
1017 },
1018 { .pme_uname = "EXT2INT_FAULTS",
1019 .pme_udesc = "Ext2Int faults",
1020 .pme_ucode = 1 << 3,
1021 },
1022 { .pme_uname = "BYPASS_FAULTS",
1023 .pme_udesc = "Bypass faults",
1024 .pme_ucode = 1 << 4,
1025 },
1026 { .pme_uname = "ALL",
1027 .pme_udesc = "All sub-events selected",
1028 .pme_ucode = 0x1F,
1029 },
1030 },
1031 },
1032/* 73 */{.pme_name = "DR0_BREAKPOINTS",
1033 .pme_code = 0xDC,
1034 .pme_desc = "DR0 Breakpoint Match",
1035 },
1036/* 74 */{.pme_name = "DR1_BREAKPOINTS",
1037 .pme_code = 0xDD,
1038 .pme_desc = "DR1 Breakpoint Match",
1039 },
1040/* 75 */{.pme_name = "DR2_BREAKPOINTS",
1041 .pme_code = 0xDE,
1042 .pme_desc = "DR2 Breakpoint Match",
1043 },
1044/* 76 */{.pme_name = "DR3_BREAKPOINTS",
1045 .pme_code = 0xDF,
1046 .pme_desc = "DR3 Breakpoint Match",
1047 },
1048/* 77 */{.pme_name = "IBS_OPS_TAGGED",
1049 .pme_code = 0x1CF,
1050 .pme_desc = "Tagged IBS Ops",
1051 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1052 .pme_numasks = 4,
1053 .pme_umasks = {
1054 { .pme_uname = "TAGGED",
1055 .pme_udesc = "Number of ops tagged by IBS",
1056 .pme_ucode = 1 << 0,
1057 },
1058 { .pme_uname = "RETIRED",
1059 .pme_udesc = "Number of ops tagged by IBS that retired",
1060 .pme_ucode = 1 << 1,
1061 },
1062 { .pme_uname = "IGNORED",
1063 .pme_udesc = "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired",
1064 .pme_ucode = 1 << 2,
1065 },
1066 { .pme_uname = "ALL",
1067 .pme_udesc = "All sub-events selected",
1068 .pme_ucode = 0x07,
1069 },
1070 },
1071 },
1072/* Northbridge events (.pme_code & 0x0E0) not yet supported by the kernel */
1073#if 0
1074/* 78 */{.pme_name = "DRAM_ACCESSES",
1075 .pme_code = 0xE0,
1076 .pme_desc = "DRAM Accesses",
1077 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1078 .pme_numasks = 7,
1079 .pme_umasks = {
1080 { .pme_uname = "HIT",
1081 .pme_udesc = "DCT0 Page hit",
1082 .pme_ucode = 1 << 0,
1083 },
1084 { .pme_uname = "MISS",
1085 .pme_udesc = "DCT0 Page Miss",
1086 .pme_ucode = 1 << 1,
1087 },
1088 { .pme_uname = "CONFLICT",
1089 .pme_udesc = "DCT0 Page Conflict",
1090 .pme_ucode = 1 << 2,
1091 },
1092 { .pme_uname = "DCT1_PAGE_HIT",
1093 .pme_udesc = "DCT1 Page hit",
1094 .pme_ucode = 1 << 3,
1095 },
1096 { .pme_uname = "DCT1_PAGE_MISS",
1097 .pme_udesc = "DCT1 Page Miss",
1098 .pme_ucode = 1 << 4,
1099 },
1100 { .pme_uname = "DCT1_PAGE_CONFLICT",
1101 .pme_udesc = "DCT1 Page Conflict",
1102 .pme_ucode = 1 << 5,
1103 },
1104 { .pme_uname = "ALL",
1105 .pme_udesc = "All sub-events selected",
1106 .pme_ucode = 0x3F,
1107 },
1108 },
1109 },
1110/* 79 */{.pme_name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS",
1111 .pme_code = 0xE1,
1112 .pme_desc = "DRAM Controller Page Table Overflows",
1113 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1114 .pme_numasks = 3,
1115 .pme_umasks = {
1116 { .pme_uname = "DCT0_PAGE_TABLE_OVERFLOW",
1117 .pme_udesc = "DCT0 Page Table Overflow",
1118 .pme_ucode = 1 << 0,
1119 },
1120 { .pme_uname = "DCT1_PAGE_TABLE_OVERFLOW",
1121 .pme_udesc = "DCT1 Page Table Overflow",
1122 .pme_ucode = 1 << 1,
1123 },
1124 { .pme_uname = "ALL",
1125 .pme_udesc = "All sub-events selected",
1126 .pme_ucode = 0x03,
1127 },
1128 },
1129 },
1130/* 80 */{.pme_name = "MEMORY_CONTROLLER_SLOT_MISSED",
1131 .pme_code = 0xE2,
1132 .pme_desc = "Memory Controller DRAM Command Slots Missed",
1133 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1134 .pme_numasks = 3,
1135 .pme_umasks = {
1136 { .pme_uname = "DCT0_COMMAND_SLOTS_MISSED",
1137 .pme_udesc = "DCT0 Command Slots Missed (in MemClks)",
1138 .pme_ucode = 1 << 0,
1139 },
1140 { .pme_uname = "DCT1_COMMAND_SLOTS_MISSED",
1141 .pme_udesc = "DCT1 Command Slots Missed (in MemClks)",
1142 .pme_ucode = 1 << 1,
1143 },
1144 { .pme_uname = "ALL",
1145 .pme_udesc = "All sub-events selected",
1146 .pme_ucode = 0x03,
1147 },
1148 },
1149 },
1150/* 81 */{.pme_name = "MEMORY_CONTROLLER_TURNAROUNDS",
1151 .pme_code = 0xE3,
1152 .pme_desc = "Memory Controller Turnarounds",
1153 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1154 .pme_numasks = 7,
1155 .pme_umasks = {
1156 { .pme_uname = "CHIP_SELECT",
1157 .pme_udesc = "DCT0 DIMM (chip select) turnaround",
1158 .pme_ucode = 1 << 0,
1159 },
1160 { .pme_uname = "READ_TO_WRITE",
1161 .pme_udesc = "DCT0 Read to write turnaround",
1162 .pme_ucode = 1 << 1,
1163 },
1164 { .pme_uname = "WRITE_TO_READ",
1165 .pme_udesc = "DCT0 Write to read turnaround",
1166 .pme_ucode = 1 << 2,
1167 },
1168 { .pme_uname = "DCT1_DIMM",
1169 .pme_udesc = "DCT1 DIMM (chip select) turnaround",
1170 .pme_ucode = 1 << 3,
1171 },
1172 { .pme_uname = "DCT1_READ_TO_WRITE_TURNAROUND",
1173 .pme_udesc = "DCT1 Read to write turnaround",
1174 .pme_ucode = 1 << 4,
1175 },
1176 { .pme_uname = "DCT1_WRITE_TO_READ_TURNAROUND",
1177 .pme_udesc = "DCT1 Write to read turnaround",
1178 .pme_ucode = 1 << 5,
1179 },
1180 { .pme_uname = "ALL",
1181 .pme_udesc = "All sub-events selected",
1182 .pme_ucode = 0x3F,
1183 },
1184 },
1185 },
1186/* 82 */{.pme_name = "MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION",
1187 .pme_code = 0xE4,
1188 .pme_desc = "Memory Controller Bypass Counter Saturation",
1189 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1190 .pme_numasks = 5,
1191 .pme_umasks = {
1192 { .pme_uname = "HIGH_PRIORITY",
1193 .pme_udesc = "Memory controller high priority bypass",
1194 .pme_ucode = 1 << 0,
1195 },
1196 { .pme_uname = "MEDIUM_PRIORITY",
1197 .pme_udesc = "Memory controller medium priority bypass",
1198 .pme_ucode = 1 << 1,
1199 },
1200 { .pme_uname = "DCT0_DCQ",
1201 .pme_udesc = "DCT0 DCQ bypass",
1202 .pme_ucode = 1 << 2,
1203 },
1204 { .pme_uname = "DCT1_DCQ",
1205 .pme_udesc = "DCT1 DCQ bypass",
1206 .pme_ucode = 1 << 3,
1207 },
1208 { .pme_uname = "ALL",
1209 .pme_udesc = "All sub-events selected",
1210 .pme_ucode = 0x0F,
1211 },
1212 },
1213 },
1214/* 83 */{.pme_name = "THERMAL_STATUS",
1215 .pme_code = 0xE8,
1216 .pme_desc = "Thermal Status",
1217 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1218 .pme_numasks = 4,
1219 .pme_umasks = {
1220 { .pme_uname = "CLKS_DIE_TEMP_TOO_HIGH",
1221 .pme_udesc = "Number of times the HTC trip point is crossed",
1222 .pme_ucode = 1 << 2,
1223 },
1224 { .pme_uname = "CLOCKS_HTC_P_STATE_INACTIVE",
1225 .pme_udesc = "Number of clocks HTC P-state is inactive",
1226 .pme_ucode = 1 << 5,
1227 },
1228 { .pme_uname = "CLOCKS_HTC_P_STATE_ACTIVE",
1229 .pme_udesc = "Number of clocks HTC P-state is active",
1230 .pme_ucode = 1 << 6,
1231 },
1232 { .pme_uname = "ALL",
1233 .pme_udesc = "All sub-events selected",
1234 .pme_ucode = 0x64,
1235 },
1236 },
1237 },
1238/* 84 */{.pme_name = "CPU_IO_REQUESTS_TO_MEMORY_IO",
1239 .pme_code = 0xE9,
1240 .pme_desc = "CPU/IO Requests to Memory/IO",
1241 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1242 .pme_numasks = 9,
1243 .pme_umasks = {
1244 { .pme_uname = "I_O_TO_I_O",
1245 .pme_udesc = "IO to IO",
1246 .pme_ucode = 1 << 0,
1247 },
1248 { .pme_uname = "I_O_TO_MEM",
1249 .pme_udesc = "IO to Mem",
1250 .pme_ucode = 1 << 1,
1251 },
1252 { .pme_uname = "CPU_TO_I_O",
1253 .pme_udesc = "CPU to IO",
1254 .pme_ucode = 1 << 2,
1255 },
1256 { .pme_uname = "CPU_TO_MEM",
1257 .pme_udesc = "CPU to Mem",
1258 .pme_ucode = 1 << 3,
1259 },
1260 { .pme_uname = "TO_REMOTE_NODE",
1261 .pme_udesc = "To remote node",
1262 .pme_ucode = 1 << 4,
1263 },
1264 { .pme_uname = "TO_LOCAL_NODE",
1265 .pme_udesc = "To local node",
1266 .pme_ucode = 1 << 5,
1267 },
1268 { .pme_uname = "FROM_REMOTE_NODE",
1269 .pme_udesc = "From remote node",
1270 .pme_ucode = 1 << 6,
1271 },
1272 { .pme_uname = "FROM_LOCAL_NODE",
1273 .pme_udesc = "From local node",
1274 .pme_ucode = 1 << 7,
1275 },
1276 { .pme_uname = "ALL",
1277 .pme_udesc = "All sub-events selected",
1278 .pme_ucode = 0xFF,
1279 },
1280 },
1281 },
1282/* 85 */{.pme_name = "CACHE_BLOCK_COMMANDS",
1283 .pme_code = 0xEA,
1284 .pme_desc = "Cache Block Commands",
1285 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1286 .pme_numasks = 6,
1287 .pme_umasks = {
1288 { .pme_uname = "VICTIM_WRITEBACK",
1289 .pme_udesc = "Victim Block (Writeback)",
1290 .pme_ucode = 1 << 0,
1291 },
1292 { .pme_uname = "DCACHE_LOAD_MISS",
1293 .pme_udesc = "Read Block (Dcache load miss refill)",
1294 .pme_ucode = 1 << 2,
1295 },
1296 { .pme_uname = "SHARED_ICACHE_REFILL",
1297 .pme_udesc = "Read Block Shared (Icache refill)",
1298 .pme_ucode = 1 << 3,
1299 },
1300 { .pme_uname = "READ_BLOCK_MODIFIED",
1301 .pme_udesc = "Read Block Modified (Dcache store miss refill)",
1302 .pme_ucode = 1 << 4,
1303 },
1304 { .pme_uname = "CHANGE_TO_DIRTY",
1305 .pme_udesc = "Change-to-Dirty (first store to clean block already in cache)",
1306 .pme_ucode = 1 << 5,
1307 },
1308 { .pme_uname = "ALL",
1309 .pme_udesc = "All sub-events selected",
1310 .pme_ucode = 0x3D,
1311 },
1312 },
1313 },
1314/* 86 */{.pme_name = "SIZED_COMMANDS",
1315 .pme_code = 0xEB,
1316 .pme_desc = "Sized Commands",
1317 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1318 .pme_numasks = 7,
1319 .pme_umasks = {
1320 { .pme_uname = "NON_POSTED_WRITE_BYTE",
1321 .pme_udesc = "Non-Posted SzWr Byte (1-32 bytes)",
1322 .pme_ucode = 1 << 0,
1323 },
1324 { .pme_uname = "NON_POSTED_WRITE_DWORD",
1325 .pme_udesc = "Non-Posted SzWr DW (1-16 dwords)",
1326 .pme_ucode = 1 << 1,
1327 },
1328 { .pme_uname = "POSTED_WRITE_BYTE",
1329 .pme_udesc = "Posted SzWr Byte (1-32 bytes)",
1330 .pme_ucode = 1 << 2,
1331 },
1332 { .pme_uname = "POSTED_WRITE_DWORD",
1333 .pme_udesc = "Posted SzWr DW (1-16 dwords)",
1334 .pme_ucode = 1 << 3,
1335 },
1336 { .pme_uname = "READ_BYTE",
1337 .pme_udesc = "SzRd Byte (4 bytes)",
1338 .pme_ucode = 1 << 4,
1339 },
1340 { .pme_uname = "READ_DWORD",
1341 .pme_udesc = "SzRd DW (1-16 dwords)",
1342 .pme_ucode = 1 << 5,
1343 },
1344 { .pme_uname = "ALL",
1345 .pme_udesc = "All sub-events selected",
1346 .pme_ucode = 0x3F,
1347 },
1348 },
1349 },
1350/* 87 */{.pme_name = "PROBE_RESPONSES_AND_UPSTREAM_REQUESTS",
1351 .pme_code = 0xEC,
1352 .pme_desc = "Probe Responses and Upstream Requests",
1353 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1354 .pme_numasks = 9,
1355 .pme_umasks = {
1356 { .pme_uname = "MISS",
1357 .pme_udesc = "Probe miss",
1358 .pme_ucode = 1 << 0,
1359 },
1360 { .pme_uname = "HIT_CLEAN",
1361 .pme_udesc = "Probe hit clean",
1362 .pme_ucode = 1 << 1,
1363 },
1364 { .pme_uname = "HIT_DIRTY_NO_MEMORY_CANCEL",
1365 .pme_udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
1366 .pme_ucode = 1 << 2,
1367 },
1368 { .pme_uname = "HIT_DIRTY_WITH_MEMORY_CANCEL",
1369 .pme_udesc = "Probe hit dirty with memory cancel (probed by DMA read/cache refill request)",
1370 .pme_ucode = 1 << 3,
1371 },
1372 { .pme_uname = "UPSTREAM_DISPLAY_REFRESH_READS",
1373 .pme_udesc = "Upstream display refresh/ISOC reads",
1374 .pme_ucode = 1 << 4,
1375 },
1376 { .pme_uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS",
1377 .pme_udesc = "Upstream non-display refresh reads",
1378 .pme_ucode = 1 << 5,
1379 },
1380 { .pme_uname = "UPSTREAM_WRITES",
1381 .pme_udesc = "Upstream ISOC writes",
1382 .pme_ucode = 1 << 6,
1383 },
1384 { .pme_uname = "UPSTREAM_NON_ISOC_WRITES",
1385 .pme_udesc = "Upstream non-ISOC writes",
1386 .pme_ucode = 1 << 7,
1387 },
1388 { .pme_uname = "ALL",
1389 .pme_udesc = "All sub-events selected",
1390 .pme_ucode = 0xFF,
1391 },
1392 },
1393 },
1394/* 88 */{.pme_name = "GART_EVENTS",
1395 .pme_code = 0xEE,
1396 .pme_desc = "GART Events",
1397 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1398 .pme_numasks = 6,
1399 .pme_umasks = {
1400 { .pme_uname = "CPU_HIT",
1401 .pme_udesc = "GART aperture hit on access from CPU",
1402 .pme_ucode = 1 << 0,
1403 },
1404 { .pme_uname = "IO_HIT",
1405 .pme_udesc = "GART aperture hit on access from IO",
1406 .pme_ucode = 1 << 1,
1407 },
1408 { .pme_uname = "MISS",
1409 .pme_udesc = "GART miss",
1410 .pme_ucode = 1 << 2,
1411 },
1412 { .pme_uname = "TABLE_WALK",
1413 .pme_udesc = "GART Request hit table walk in progress",
1414 .pme_ucode = 1 << 3,
1415 },
1416 { .pme_uname = "MULTIPLE_TABLE_WALK",
1417 .pme_udesc = "GART multiple table walk in progress",
1418 .pme_ucode = 1 << 7,
1419 },
1420 { .pme_uname = "ALL",
1421 .pme_udesc = "All sub-events selected",
1422 .pme_ucode = 0x8F,
1423 },
1424 },
1425 },
1426/* 89 */{.pme_name = "HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH",
1427 .pme_code = 0xF6,
1428 .pme_desc = "HyperTransport(tm) Link 0 Transmit Bandwidth",
1429 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1430 .pme_numasks = 8,
1431 .pme_umasks = {
1432 { .pme_uname = "COMMAND_DWORD_SENT",
1433 .pme_udesc = "Command DWORD sent",
1434 .pme_ucode = 1 << 0,
1435 },
1436 { .pme_uname = "DATA_DWORD_SENT",
1437 .pme_udesc = "Data DWORD sent",
1438 .pme_ucode = 1 << 1,
1439 },
1440 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1441 .pme_udesc = "Buffer release DWORD sent",
1442 .pme_ucode = 1 << 2,
1443 },
1444 { .pme_uname = "NOP_DWORD_SENT",
1445 .pme_udesc = "Nop DW sent (idle)",
1446 .pme_ucode = 1 << 3,
1447 },
1448 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1449 .pme_udesc = "Address DWORD sent",
1450 .pme_ucode = 1 << 4,
1451 },
1452 { .pme_uname = "PER_PACKET_CRC_SENT",
1453 .pme_udesc = "Per packet CRC sent",
1454 .pme_ucode = 1 << 5,
1455 },
1456 { .pme_uname = "SUBLINK_MASK",
1457 .pme_udesc = "SubLink Mask",
1458 .pme_ucode = 1 << 7,
1459 },
1460 { .pme_uname = "ALL",
1461 .pme_udesc = "All sub-events selected",
1462 .pme_ucode = 0xBF,
1463 },
1464 },
1465 },
1466/* 90 */{.pme_name = "HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH",
1467 .pme_code = 0xF7,
1468 .pme_desc = "HyperTransport(tm) Link 1 Transmit Bandwidth",
1469 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1470 .pme_numasks = 8,
1471 .pme_umasks = {
1472 { .pme_uname = "COMMAND_DWORD_SENT",
1473 .pme_udesc = "Command DWORD sent",
1474 .pme_ucode = 1 << 0,
1475 },
1476 { .pme_uname = "DATA_DWORD_SENT",
1477 .pme_udesc = "Data DWORD sent",
1478 .pme_ucode = 1 << 1,
1479 },
1480 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1481 .pme_udesc = "Buffer release DWORD sent",
1482 .pme_ucode = 1 << 2,
1483 },
1484 { .pme_uname = "NOP_DWORD_SENT",
1485 .pme_udesc = "Nop DW sent (idle)",
1486 .pme_ucode = 1 << 3,
1487 },
1488 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1489 .pme_udesc = "Address DWORD sent",
1490 .pme_ucode = 1 << 4,
1491 },
1492 { .pme_uname = "PER_PACKET_CRC_SENT",
1493 .pme_udesc = "Per packet CRC sent",
1494 .pme_ucode = 1 << 5,
1495 },
1496 { .pme_uname = "SUBLINK_MASK",
1497 .pme_udesc = "SubLink Mask",
1498 .pme_ucode = 1 << 7,
1499 },
1500 { .pme_uname = "ALL",
1501 .pme_udesc = "All sub-events selected",
1502 .pme_ucode = 0xBF,
1503 },
1504 },
1505 },
1506/* 91 */{.pme_name = "HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH",
1507 .pme_code = 0xF8,
1508 .pme_desc = "HyperTransport(tm) Link 2 Transmit Bandwidth",
1509 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1510 .pme_numasks = 8,
1511 .pme_umasks = {
1512 { .pme_uname = "COMMAND_DWORD_SENT",
1513 .pme_udesc = "Command DWORD sent",
1514 .pme_ucode = 1 << 0,
1515 },
1516 { .pme_uname = "DATA_DWORD_SENT",
1517 .pme_udesc = "Data DWORD sent",
1518 .pme_ucode = 1 << 1,
1519 },
1520 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1521 .pme_udesc = "Buffer release DWORD sent",
1522 .pme_ucode = 1 << 2,
1523 },
1524 { .pme_uname = "NOP_DWORD_SENT",
1525 .pme_udesc = "Nop DW sent (idle)",
1526 .pme_ucode = 1 << 3,
1527 },
1528 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1529 .pme_udesc = "Address DWORD sent",
1530 .pme_ucode = 1 << 4,
1531 },
1532 { .pme_uname = "PER_PACKET_CRC_SENT",
1533 .pme_udesc = "Per packet CRC sent",
1534 .pme_ucode = 1 << 5,
1535 },
1536 { .pme_uname = "SUBLINK_MASK",
1537 .pme_udesc = "SubLink Mask",
1538 .pme_ucode = 1 << 7,
1539 },
1540 { .pme_uname = "ALL",
1541 .pme_udesc = "All sub-events selected",
1542 .pme_ucode = 0xBF,
1543 },
1544 },
1545 },
1546/* 92 */{.pme_name = "HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH",
1547 .pme_code = 0x1F9,
1548 .pme_desc = "HyperTransport(tm) Link 3 Transmit Bandwidth",
1549 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1550 .pme_numasks = 8,
1551 .pme_umasks = {
1552 { .pme_uname = "COMMAND_DWORD_SENT",
1553 .pme_udesc = "Command DWORD sent",
1554 .pme_ucode = 1 << 0,
1555 },
1556 { .pme_uname = "DATA_DWORD_SENT",
1557 .pme_udesc = "Data DWORD sent",
1558 .pme_ucode = 1 << 1,
1559 },
1560 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1561 .pme_udesc = "Buffer release DWORD sent",
1562 .pme_ucode = 1 << 2,
1563 },
1564 { .pme_uname = "NOP_DWORD_SENT",
1565 .pme_udesc = "Nop DW sent (idle)",
1566 .pme_ucode = 1 << 3,
1567 },
1568 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1569 .pme_udesc = "Address DWORD sent",
1570 .pme_ucode = 1 << 4,
1571 },
1572 { .pme_uname = "PER_PACKET_CRC_SENT",
1573 .pme_udesc = "Per packet CRC sent",
1574 .pme_ucode = 1 << 5,
1575 },
1576 { .pme_uname = "SUBLINK_MASK",
1577 .pme_udesc = "SubLink Mask",
1578 .pme_ucode = 1 << 7,
1579 },
1580 { .pme_uname = "ALL",
1581 .pme_udesc = "All sub-events selected",
1582 .pme_ucode = 0xBF,
1583 },
1584 },
1585 },
1586/* 93 */{.pme_name = "CPU_DRAM_REQUEST_TO_NODE",
1587 .pme_code = 0x1E0,
1588 .pme_desc = "CPU to DRAM Requests to Target Node",
1589 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1590 .pme_numasks = 9,
1591 .pme_umasks = {
1592 { .pme_uname = "LOCAL_TO_0",
1593 .pme_udesc = "From Local node to Node 0",
1594 .pme_ucode = 1 << 0,
1595 },
1596 { .pme_uname = "LOCAL_TO_1",
1597 .pme_udesc = "From Local node to Node 1",
1598 .pme_ucode = 1 << 1,
1599 },
1600 { .pme_uname = "LOCAL_TO_2",
1601 .pme_udesc = "From Local node to Node 2",
1602 .pme_ucode = 1 << 2,
1603 },
1604 { .pme_uname = "LOCAL_TO_3",
1605 .pme_udesc = "From Local node to Node 3",
1606 .pme_ucode = 1 << 3,
1607 },
1608 { .pme_uname = "LOCAL_TO_4",
1609 .pme_udesc = "From Local node to Node 4",
1610 .pme_ucode = 1 << 4,
1611 },
1612 { .pme_uname = "LOCAL_TO_5",
1613 .pme_udesc = "From Local node to Node 5",
1614 .pme_ucode = 1 << 5,
1615 },
1616 { .pme_uname = "LOCAL_TO_6",
1617 .pme_udesc = "From Local node to Node 6",
1618 .pme_ucode = 1 << 6,
1619 },
1620 { .pme_uname = "LOCAL_TO_7",
1621 .pme_udesc = "From Local node to Node 7",
1622 .pme_ucode = 1 << 7,
1623 },
1624 { .pme_uname = "ALL",
1625 .pme_udesc = "All sub-events selected",
1626 .pme_ucode = 0xFF,
1627 },
1628 },
1629 },
1630/* 94 */{.pme_name = "IO_DRAM_REQUEST_TO_NODE",
1631 .pme_code = 0x1E1,
1632 .pme_desc = "IO to DRAM Requests to Target Node",
1633 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1634 .pme_numasks = 9,
1635 .pme_umasks = {
1636 { .pme_uname = "LOCAL_TO_0",
1637 .pme_udesc = "From Local node to Node 0",
1638 .pme_ucode = 1 << 0,
1639 },
1640 { .pme_uname = "LOCAL_TO_1",
1641 .pme_udesc = "From Local node to Node 1",
1642 .pme_ucode = 1 << 1,
1643 },
1644 { .pme_uname = "LOCAL_TO_2",
1645 .pme_udesc = "From Local node to Node 2",
1646 .pme_ucode = 1 << 2,
1647 },
1648 { .pme_uname = "LOCAL_TO_3",
1649 .pme_udesc = "From Local node to Node 3",
1650 .pme_ucode = 1 << 3,
1651 },
1652 { .pme_uname = "LOCAL_TO_4",
1653 .pme_udesc = "From Local node to Node 4",
1654 .pme_ucode = 1 << 4,
1655 },
1656 { .pme_uname = "LOCAL_TO_5",
1657 .pme_udesc = "From Local node to Node 5",
1658 .pme_ucode = 1 << 5,
1659 },
1660 { .pme_uname = "LOCAL_TO_6",
1661 .pme_udesc = "From Local node to Node 6",
1662 .pme_ucode = 1 << 6,
1663 },
1664 { .pme_uname = "LOCAL_TO_7",
1665 .pme_udesc = "From Local node to Node 7",
1666 .pme_ucode = 1 << 7,
1667 },
1668 { .pme_uname = "ALL",
1669 .pme_udesc = "All sub-events selected",
1670 .pme_ucode = 0xFF,
1671 },
1672 },
1673 },
1674/* 95 */{.pme_name = "CPU_READ_COMMAND_LATENCY_NODE_0_3",
1675 .pme_code = 0x1E2,
1676 .pme_desc = "CPU Read Command Latency to Target Node 0-3",
1677 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1678 .pme_numasks = 9,
1679 .pme_umasks = {
1680 { .pme_uname = "READ_BLOCK",
1681 .pme_udesc = "Read block",
1682 .pme_ucode = 1 << 0,
1683 },
1684 { .pme_uname = "READ_BLOCK_SHARED",
1685 .pme_udesc = "Read block shared",
1686 .pme_ucode = 1 << 1,
1687 },
1688 { .pme_uname = "READ_BLOCK_MODIFIED",
1689 .pme_udesc = "Read block modified",
1690 .pme_ucode = 1 << 2,
1691 },
1692 { .pme_uname = "CHANGE_TO_DIRTY",
1693 .pme_udesc = "Change-to-Dirty",
1694 .pme_ucode = 1 << 3,
1695 },
1696 { .pme_uname = "LOCAL_TO_0",
1697 .pme_udesc = "From Local node to Node 0",
1698 .pme_ucode = 1 << 4,
1699 },
1700 { .pme_uname = "LOCAL_TO_1",
1701 .pme_udesc = "From Local node to Node 1",
1702 .pme_ucode = 1 << 5,
1703 },
1704 { .pme_uname = "LOCAL_TO_2",
1705 .pme_udesc = "From Local node to Node 2",
1706 .pme_ucode = 1 << 6,
1707 },
1708 { .pme_uname = "LOCAL_TO_3",
1709 .pme_udesc = "From Local node to Node 3",
1710 .pme_ucode = 1 << 7,
1711 },
1712 { .pme_uname = "ALL",
1713 .pme_udesc = "All sub-events selected",
1714 .pme_ucode = 0xFF,
1715 },
1716 },
1717 },
1718/* 96 */{.pme_name = "CPU_READ_COMMAND_REQUEST_NODE_0_3",
1719 .pme_code = 0x1E3,
1720 .pme_desc = "CPU Read Command Requests to Target Node 0-3",
1721 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1722 .pme_numasks = 9,
1723 .pme_umasks = {
1724 { .pme_uname = "READ_BLOCK",
1725 .pme_udesc = "Read block",
1726 .pme_ucode = 1 << 0,
1727 },
1728 { .pme_uname = "READ_BLOCK_SHARED",
1729 .pme_udesc = "Read block shared",
1730 .pme_ucode = 1 << 1,
1731 },
1732 { .pme_uname = "READ_BLOCK_MODIFIED",
1733 .pme_udesc = "Read block modified",
1734 .pme_ucode = 1 << 2,
1735 },
1736 { .pme_uname = "CHANGE_TO_DIRTY",
1737 .pme_udesc = "Change-to-Dirty",
1738 .pme_ucode = 1 << 3,
1739 },
1740 { .pme_uname = "LOCAL_TO_0",
1741 .pme_udesc = "From Local node to Node 0",
1742 .pme_ucode = 1 << 4,
1743 },
1744 { .pme_uname = "LOCAL_TO_1",
1745 .pme_udesc = "From Local node to Node 1",
1746 .pme_ucode = 1 << 5,
1747 },
1748 { .pme_uname = "LOCAL_TO_2",
1749 .pme_udesc = "From Local node to Node 2",
1750 .pme_ucode = 1 << 6,
1751 },
1752 { .pme_uname = "LOCAL_TO_3",
1753 .pme_udesc = "From Local node to Node 3",
1754 .pme_ucode = 1 << 7,
1755 },
1756 { .pme_uname = "ALL",
1757 .pme_udesc = "All sub-events selected",
1758 .pme_ucode = 0xFF,
1759 },
1760 },
1761 },
1762/* 97 */{.pme_name = "CPU_READ_COMMAND_LATENCY_NODE_4_7",
1763 .pme_code = 0x1E4,
1764 .pme_desc = "CPU Read Command Latency to Target Node 4-7",
1765 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1766 .pme_numasks = 9,
1767 .pme_umasks = {
1768 { .pme_uname = "READ_BLOCK",
1769 .pme_udesc = "Read block",
1770 .pme_ucode = 1 << 0,
1771 },
1772 { .pme_uname = "READ_BLOCK_SHARED",
1773 .pme_udesc = "Read block shared",
1774 .pme_ucode = 1 << 1,
1775 },
1776 { .pme_uname = "READ_BLOCK_MODIFIED",
1777 .pme_udesc = "Read block modified",
1778 .pme_ucode = 1 << 2,
1779 },
1780 { .pme_uname = "CHANGE_TO_DIRTY",
1781 .pme_udesc = "Change-to-Dirty",
1782 .pme_ucode = 1 << 3,
1783 },
1784 { .pme_uname = "LOCAL_TO_4",
1785 .pme_udesc = "From Local node to Node 4",
1786 .pme_ucode = 1 << 4,
1787 },
1788 { .pme_uname = "LOCAL_TO_5",
1789 .pme_udesc = "From Local node to Node 5",
1790 .pme_ucode = 1 << 5,
1791 },
1792 { .pme_uname = "LOCAL_TO_6",
1793 .pme_udesc = "From Local node to Node 6",
1794 .pme_ucode = 1 << 6,
1795 },
1796 { .pme_uname = "LOCAL_TO_7",
1797 .pme_udesc = "From Local node to Node 7",
1798 .pme_ucode = 1 << 7,
1799 },
1800 { .pme_uname = "ALL",
1801 .pme_udesc = "All sub-events selected",
1802 .pme_ucode = 0xFF,
1803 },
1804 },
1805 },
1806/* 98 */{.pme_name = "CPU_READ_COMMAND_REQUEST_NODE_4_7",
1807 .pme_code = 0x1E5,
1808 .pme_desc = "CPU Read Command Requests to Target Node 4-7",
1809 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1810 .pme_numasks = 9,
1811 .pme_umasks = {
1812 { .pme_uname = "READ_BLOCK",
1813 .pme_udesc = "Read block",
1814 .pme_ucode = 1 << 0,
1815 },
1816 { .pme_uname = "READ_BLOCK_SHARED",
1817 .pme_udesc = "Read block shared",
1818 .pme_ucode = 1 << 1,
1819 },
1820 { .pme_uname = "READ_BLOCK_MODIFIED",
1821 .pme_udesc = "Read block modified",
1822 .pme_ucode = 1 << 2,
1823 },
1824 { .pme_uname = "CHANGE_TO_DIRTY",
1825 .pme_udesc = "Change-to-Dirty",
1826 .pme_ucode = 1 << 3,
1827 },
1828 { .pme_uname = "LOCAL_TO_4",
1829 .pme_udesc = "From Local node to Node 4",
1830 .pme_ucode = 1 << 4,
1831 },
1832 { .pme_uname = "LOCAL_TO_5",
1833 .pme_udesc = "From Local node to Node 5",
1834 .pme_ucode = 1 << 5,
1835 },
1836 { .pme_uname = "LOCAL_TO_6",
1837 .pme_udesc = "From Local node to Node 6",
1838 .pme_ucode = 1 << 6,
1839 },
1840 { .pme_uname = "LOCAL_TO_7",
1841 .pme_udesc = "From Local node to Node 7",
1842 .pme_ucode = 1 << 7,
1843 },
1844 { .pme_uname = "ALL",
1845 .pme_udesc = "All sub-events selected",
1846 .pme_ucode = 0xFF,
1847 },
1848 },
1849 },
1850/* 99 */{.pme_name = "CPU_COMMAND_LATENCY_TARGET",
1851 .pme_code = 0x1E6,
1852 .pme_desc = "CPU Command Latency to Target Node 0-3/4-7",
1853 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1854 .pme_numasks = 9,
1855 .pme_umasks = {
1856 { .pme_uname = "READ_SIZED",
1857 .pme_udesc = "Read Sized",
1858 .pme_ucode = 1 << 0,
1859 },
1860 { .pme_uname = "WRITE_SIZED",
1861 .pme_udesc = "Write Sized",
1862 .pme_ucode = 1 << 1,
1863 },
1864 { .pme_uname = "VICTIM_BLOCK",
1865 .pme_udesc = "Victim Block",
1866 .pme_ucode = 1 << 2,
1867 },
1868 { .pme_uname = "NODE_GROUP_SELECT",
1869 .pme_udesc = "Node Group Select: 0=Nodes 0-3, 1= Nodes 4-7",
1870 .pme_ucode = 1 << 3,
1871 },
1872 { .pme_uname = "LOCAL_TO_0_4",
1873 .pme_udesc = "From Local node to Node 0/4",
1874 .pme_ucode = 1 << 4,
1875 },
1876 { .pme_uname = "LOCAL_TO_1_5",
1877 .pme_udesc = "From Local node to Node 1/5",
1878 .pme_ucode = 1 << 5,
1879 },
1880 { .pme_uname = "LOCAL_TO_2_6",
1881 .pme_udesc = "From Local node to Node 2/6",
1882 .pme_ucode = 1 << 6,
1883 },
1884 { .pme_uname = "LOCAL_TO_3_7",
1885 .pme_udesc = "From Local node to Node 3/7",
1886 .pme_ucode = 1 << 7,
1887 },
1888 { .pme_uname = "ALL",
1889 .pme_udesc = "All sub-events selected",
1890 .pme_ucode = 0xFF,
1891 },
1892 },
1893 },
1894/* 100 */{.pme_name = "CPU_REQUEST_TARGET",
1895 .pme_code = 0x1E7,
1896 .pme_desc = "CPU Requests to Target Node 0-3/4-7",
1897 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1898 .pme_numasks = 9,
1899 .pme_umasks = {
1900 { .pme_uname = "READ_SIZED",
1901 .pme_udesc = "Read Sized",
1902 .pme_ucode = 1 << 0,
1903 },
1904 { .pme_uname = "WRITE_SIZED",
1905 .pme_udesc = "Write Sized",
1906 .pme_ucode = 1 << 1,
1907 },
1908 { .pme_uname = "VICTIM_BLOCK",
1909 .pme_udesc = "Victim Block",
1910 .pme_ucode = 1 << 2,
1911 },
1912 { .pme_uname = "NODE_GROUP_SELECT",
1913 .pme_udesc = "Node Group Select: 0=Nodes 0-3, 1= Nodes 4-7",
1914 .pme_ucode = 1 << 3,
1915 },
1916 { .pme_uname = "LOCAL_TO_0_4",
1917 .pme_udesc = "From Local node to Node 0/4",
1918 .pme_ucode = 1 << 4,
1919 },
1920 { .pme_uname = "LOCAL_TO_1_5",
1921 .pme_udesc = "From Local node to Node 1/5",
1922 .pme_ucode = 1 << 5,
1923 },
1924 { .pme_uname = "LOCAL_TO_2_6",
1925 .pme_udesc = "From Local node to Node 2/6",
1926 .pme_ucode = 1 << 6,
1927 },
1928 { .pme_uname = "LOCAL_TO_3_7",
1929 .pme_udesc = "From Local node to Node 3/7",
1930 .pme_ucode = 1 << 7,
1931 },
1932 { .pme_uname = "ALL",
1933 .pme_udesc = "All sub-events selected",
1934 .pme_ucode = 0xFF,
1935 },
1936 },
1937 },
1938/* 101 */{.pme_name = "MEMORY_CONTROLLER_REQUESTS",
1939 .pme_code = 0x1F0,
1940 .pme_desc = "Memory Controller Requests",
1941 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1942 .pme_numasks = 9,
1943 .pme_umasks = {
1944 { .pme_uname = "WRITE_REQUESTS",
1945 .pme_udesc = "Write requests sent to the DCT",
1946 .pme_ucode = 1 << 0,
1947 },
1948 { .pme_uname = "READ_REQUESTS",
1949 .pme_udesc = "Read requests (including prefetch requests) sent to the DCT",
1950 .pme_ucode = 1 << 1,
1951 },
1952 { .pme_uname = "PREFETCH_REQUESTS",
1953 .pme_udesc = "Prefetch requests sent to the DCT",
1954 .pme_ucode = 1 << 2,
1955 },
1956 { .pme_uname = "32_BYTES_WRITES",
1957 .pme_udesc = "32 Bytes Sized Writes",
1958 .pme_ucode = 1 << 3,
1959 },
1960 { .pme_uname = "64_BYTES_WRITES",
1961 .pme_udesc = "64 Bytes Sized Writes",
1962 .pme_ucode = 1 << 4,
1963 },
1964 { .pme_uname = "32_BYTES_READS",
1965 .pme_udesc = "32 Bytes Sized Reads",
1966 .pme_ucode = 1 << 5,
1967 },
1968 { .pme_uname = "64_BYTES_READS",
1969 .pme_udesc = "64 Byte Sized Reads",
1970 .pme_ucode = 1 << 6,
1971 },
1972 { .pme_uname = "READ_REQUESTS_WHILE_WRITES_REQUESTS",
1973 .pme_udesc = "Read requests sent to the DCT while writes requests are pending in the DCT",
1974 .pme_ucode = 1 << 7,
1975 },
1976 { .pme_uname = "ALL",
1977 .pme_udesc = "All sub-events selected",
1978 .pme_ucode = 0xFF,
1979 },
1980 },
1981 },
1982/* 102 */{.pme_name = "READ_REQUEST_L3_CACHE",
1983 .pme_code = 0x4E0,
1984 .pme_desc = "Read Request to L3 Cache",
1985 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1986 .pme_numasks = 13,
1987 .pme_umasks = {
1988 { .pme_uname = "READ_BLOCK_EXCLUSIVE",
1989 .pme_udesc = "Read Block Exclusive (Data cache read)",
1990 .pme_ucode = 1 << 0,
1991 },
1992 { .pme_uname = "READ_BLOCK_SHARED",
1993 .pme_udesc = "Read Block Shared (Instruction cache read)",
1994 .pme_ucode = 1 << 1,
1995 },
1996 { .pme_uname = "READ_BLOCK_MODIFY",
1997 .pme_udesc = "Read Block Modify",
1998 .pme_ucode = 1 << 2,
1999 },
2000 { .pme_uname = "PREFETCH_ONLY",
2001 .pme_udesc = "1=Count prefetch only, 0=Count prefetch and non-prefetch",
2002 .pme_ucode = 1 << 3,
2003 },
2004 { .pme_uname = "CORE_0_SELECT",
2005 .pme_udesc = "Core 0 Select",
2006 .pme_ucode = 0x00,
2007 },
2008 { .pme_uname = "CORE_1_SELECT",
2009 .pme_udesc = "Core 1 Select",
2010 .pme_ucode = 0x10,
2011 },
2012 { .pme_uname = "CORE_2_SELECT",
2013 .pme_udesc = "Core 2 Select",
2014 .pme_ucode = 0x20,
2015 },
2016 { .pme_uname = "CORE_3_SELECT",
2017 .pme_udesc = "Core 3 Select",
2018 .pme_ucode = 0x30,
2019 },
2020 { .pme_uname = "CORE_4_SELECT",
2021 .pme_udesc = "Core 4 Select",
2022 .pme_ucode = 0x40,
2023 },
2024 { .pme_uname = "CORE_5_SELECT",
2025 .pme_udesc = "Core 5 Select",
2026 .pme_ucode = 0x50,
2027 },
2028 { .pme_uname = "CORE_6_SELECT",
2029 .pme_udesc = "Core 6 Select",
2030 .pme_ucode = 0x60,
2031 },
2032 { .pme_uname = "CORE_7_SELECT",
2033 .pme_udesc = "Core 7 Select",
2034 .pme_ucode = 0x70,
2035 },
2036 { .pme_uname = "ALL_CORES",
2037 .pme_udesc = "All cores",
2038 .pme_ucode = 0xF0,
2039 },
2040 },
2041 },
2042/* 103 */{.pme_name = "L3_CACHE_MISSES",
2043 .pme_code = 0x4E1,
2044 .pme_desc = "L3 Cache Misses",
2045 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2046 .pme_numasks = 13,
2047 .pme_umasks = {
2048 { .pme_uname = "READ_BLOCK_EXCLUSIVE",
2049 .pme_udesc = "Read Block Exclusive (Data cache read)",
2050 .pme_ucode = 1 << 0,
2051 },
2052 { .pme_uname = "READ_BLOCK_SHARED",
2053 .pme_udesc = "Read Block Shared (Instruction cache read)",
2054 .pme_ucode = 1 << 1,
2055 },
2056 { .pme_uname = "READ_BLOCK_MODIFY",
2057 .pme_udesc = "Read Block Modify",
2058 .pme_ucode = 1 << 2,
2059 },
2060 { .pme_uname = "PREFETCH_ONLY",
2061 .pme_udesc = "1=Count prefetch only, 0=Count prefetch and non-prefetch",
2062 .pme_ucode = 1 << 3,
2063 },
2064 { .pme_uname = "CORE_0_SELECT",
2065 .pme_udesc = "Core 0 Select",
2066 .pme_ucode = 0x00,
2067 },
2068 { .pme_uname = "CORE_1_SELECT",
2069 .pme_udesc = "Core 1 Select",
2070 .pme_ucode = 0x10,
2071 },
2072 { .pme_uname = "CORE_2_SELECT",
2073 .pme_udesc = "Core 2 Select",
2074 .pme_ucode = 0x20,
2075 },
2076 { .pme_uname = "CORE_3_SELECT",
2077 .pme_udesc = "Core 3 Select",
2078 .pme_ucode = 0x30,
2079 },
2080 { .pme_uname = "CORE_4_SELECT",
2081 .pme_udesc = "Core 4 Select",
2082 .pme_ucode = 0x40,
2083 },
2084 { .pme_uname = "CORE_5_SELECT",
2085 .pme_udesc = "Core 5 Select",
2086 .pme_ucode = 0x50,
2087 },
2088 { .pme_uname = "CORE_6_SELECT",
2089 .pme_udesc = "Core 6 Select",
2090 .pme_ucode = 0x60,
2091 },
2092 { .pme_uname = "CORE_7_SELECT",
2093 .pme_udesc = "Core 7 Select",
2094 .pme_ucode = 0x70,
2095 },
2096 { .pme_uname = "ALL_CORES",
2097 .pme_udesc = "All cores",
2098 .pme_ucode = 0xF0,
2099 },
2100 },
2101 },
2102/* 104 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
2103 .pme_code = 0x4E2,
2104 .pme_desc = "L3 Fills caused by L2 Evictions",
2105 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2106 .pme_numasks = 13,
2107 .pme_umasks = {
2108 { .pme_uname = "SHARED",
2109 .pme_udesc = "Shared",
2110 .pme_ucode = 1 << 0,
2111 },
2112 { .pme_uname = "EXCLUSIVE",
2113 .pme_udesc = "Exclusive",
2114 .pme_ucode = 1 << 1,
2115 },
2116 { .pme_uname = "OWNED",
2117 .pme_udesc = "Owned",
2118 .pme_ucode = 1 << 2,
2119 },
2120 { .pme_uname = "MODIFIED",
2121 .pme_udesc = "Modified",
2122 .pme_ucode = 1 << 3,
2123 },
2124 { .pme_uname = "CORE_0_SELECT",
2125 .pme_udesc = "Core 0 Select",
2126 .pme_ucode = 0x00,
2127 },
2128 { .pme_uname = "CORE_1_SELECT",
2129 .pme_udesc = "Core 1 Select",
2130 .pme_ucode = 0x10,
2131 },
2132 { .pme_uname = "CORE_2_SELECT",
2133 .pme_udesc = "Core 2 Select",
2134 .pme_ucode = 0x20,
2135 },
2136 { .pme_uname = "CORE_3_SELECT",
2137 .pme_udesc = "Core 3 Select",
2138 .pme_ucode = 0x30,
2139 },
2140 { .pme_uname = "CORE_4_SELECT",
2141 .pme_udesc = "Core 4 Select",
2142 .pme_ucode = 0x40,
2143 },
2144 { .pme_uname = "CORE_5_SELECT",
2145 .pme_udesc = "Core 5 Select",
2146 .pme_ucode = 0x50,
2147 },
2148 { .pme_uname = "CORE_6_SELECT",
2149 .pme_udesc = "Core 6 Select",
2150 .pme_ucode = 0x60,
2151 },
2152 { .pme_uname = "CORE_7_SELECT",
2153 .pme_udesc = "Core 7 Select",
2154 .pme_ucode = 0x70,
2155 },
2156 { .pme_uname = "ALL_CORES",
2157 .pme_udesc = "All cores",
2158 .pme_ucode = 0xF0,
2159 },
2160 },
2161 },
2162/* 105 */{.pme_name = "L3_EVICTIONS",
2163 .pme_code = 0x4E3,
2164 .pme_desc = "L3 Evictions",
2165 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2166 .pme_numasks = 5,
2167 .pme_umasks = {
2168 { .pme_uname = "SHARED",
2169 .pme_udesc = "Shared",
2170 .pme_ucode = 1 << 0,
2171 },
2172 { .pme_uname = "EXCLUSIVE",
2173 .pme_udesc = "Exclusive",
2174 .pme_ucode = 1 << 1,
2175 },
2176 { .pme_uname = "OWNED",
2177 .pme_udesc = "Owned",
2178 .pme_ucode = 1 << 2,
2179 },
2180 { .pme_uname = "MODIFIED",
2181 .pme_udesc = "Modified",
2182 .pme_ucode = 1 << 3,
2183 },
2184 { .pme_uname = "ALL",
2185 .pme_udesc = "All sub-events selected",
2186 .pme_ucode = 0x0F,
2187 },
2188 },
2189 },
2190/* 106 */{.pme_name = "NON_CANCELLED_L3_READ_REQUESTS",
2191 .pme_code = 0x4ED,
2192 .pme_desc = "Non-canceled L3 Read Requests",
2193 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2194 .pme_numasks = 13,
2195 .pme_umasks = {
2196 { .pme_uname = "RDBLK",
2197 .pme_udesc = "RdBlk",
2198 .pme_ucode = 1 << 0,
2199 },
2200 { .pme_uname = "RDBLKS",
2201 .pme_udesc = "RdBlkS",
2202 .pme_ucode = 1 << 1,
2203 },
2204 { .pme_uname = "RDBLKM",
2205 .pme_udesc = "RdBlkM",
2206 .pme_ucode = 1 << 2,
2207 },
2208 { .pme_uname = "PREFETCH_ONLY",
2209 .pme_udesc = "1=Count prefetch only; 0=Count prefetch and non-prefetch",
2210 .pme_ucode = 1 << 3,
2211 },
2212 { .pme_uname = "CORE_0_SELECT",
2213 .pme_udesc = "Core 0 Select",
2214 .pme_ucode = 0x00,
2215 },
2216 { .pme_uname = "CORE_1_SELECT",
2217 .pme_udesc = "Core 1 Select",
2218 .pme_ucode = 0x10,
2219 },
2220 { .pme_uname = "CORE_2_SELECT",
2221 .pme_udesc = "Core 2 Select",
2222 .pme_ucode = 0x20,
2223 },
2224 { .pme_uname = "CORE_3_SELECT",
2225 .pme_udesc = "Core 3 Select",
2226 .pme_ucode = 0x30,
2227 },
2228 { .pme_uname = "CORE_4_SELECT",
2229 .pme_udesc = "Core 4 Select",
2230 .pme_ucode = 0x40,
2231 },
2232 { .pme_uname = "CORE_5_SELECT",
2233 .pme_udesc = "Core 5 Select",
2234 .pme_ucode = 0x50,
2235 },
2236 { .pme_uname = "CORE_6_SELECT",
2237 .pme_udesc = "Core 6 Select",
2238 .pme_ucode = 0x60,
2239 },
2240 { .pme_uname = "CORE_7_SELECT",
2241 .pme_udesc = "Core 7 Select",
2242 .pme_ucode = 0x70,
2243 },
2244 { .pme_uname = "ALL_CORES",
2245 .pme_udesc = "All cores",
2246 .pme_ucode = 0xF0,
2247 },
2248 },
2249 },
2250#endif
2251/* 107 */{.pme_name = "LS_DISPATCH",
2252 .pme_code = 0x29,
2253 .pme_desc = "LS Dispatch",
2254 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2255 .pme_numasks = 4,
2256 .pme_umasks = {
2257 { .pme_uname = "LOADS",
2258 .pme_udesc = "Loads",
2259 .pme_ucode = 1 << 0,
2260 },
2261 { .pme_uname = "STORES",
2262 .pme_udesc = "Stores",
2263 .pme_ucode = 1 << 1,
2264 },
2265 { .pme_uname = "LOAD_OP_STORES",
2266 .pme_udesc = "Load-op-Stores",
2267 .pme_ucode = 1 << 2,
2268 },
2269 { .pme_uname = "ALL",
2270 .pme_udesc = "All sub-events selected",
2271 .pme_ucode = 0x07,
2272 },
2273 },
2274 },
2275/* 108 */{.pme_name = "EXECUTED_CLFLUSH_INSTRUCTIONS",
2276 .pme_code = 0x30,
2277 .pme_desc = "Executed CLFLUSH Instructions",
2278 },
2279/* 109 */{.pme_name = "L2_PREFETCHER_TRIGGER_EVENTS",
2280 .pme_code = 0x16C,
2281 .pme_desc = "L2 Prefetcher Trigger Events",
2282 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2283 .pme_numasks = 3,
2284 .pme_umasks = {
2285 { .pme_uname = "LOAD_L1_MISS_SEEN_BY_PREFETCHER",
2286 .pme_udesc = "Load L1 miss seen by prefetcher",
2287 .pme_ucode = 1 << 0,
2288 },
2289 { .pme_uname = "STORE_L1_MISS_SEEN_BY_PREFETCHER",
2290 .pme_udesc = "Store L1 miss seen by prefetcher",
2291 .pme_ucode = 1 << 1,
2292 },
2293 { .pme_uname = "ALL",
2294 .pme_udesc = "All sub-events selected",
2295 .pme_ucode = 0x03,
2296 },
2297 },
2298 },
2299/* 110 */{.pme_name = "DISPATCH_STALL_FOR_STQ_FULL",
2300 .pme_code = 0x1D8,
2301 .pme_desc = "Dispatch Stall for STQ Full",
2302 },
2303/* Northbridge events (.pme_code & 0x0E0) not yet supported by the kernel */
2304#if 0
2305/* 111 */{.pme_name = "REQUEST_CACHE_STATUS_0",
2306 .pme_code = 0x1EA,
2307 .pme_desc = "Request Cache Status 0",
2308 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2309 .pme_numasks = 9,
2310 .pme_umasks = {
2311 { .pme_uname = "PROBE_HIT_S",
2312 .pme_udesc = "Probe Hit S",
2313 .pme_ucode = 1 << 0,
2314 },
2315 { .pme_uname = "PROBE_HIT_E",
2316 .pme_udesc = "Probe Hit E",
2317 .pme_ucode = 1 << 1,
2318 },
2319 { .pme_uname = "PROBE_HIT_MUW_OR_O",
2320 .pme_udesc = "Probe Hit MuW or O",
2321 .pme_ucode = 1 << 2,
2322 },
2323 { .pme_uname = "PROBE_HIT_M",
2324 .pme_udesc = "Probe Hit M",
2325 .pme_ucode = 1 << 3,
2326 },
2327 { .pme_uname = "PROBE_MISS",
2328 .pme_udesc = "Probe Miss",
2329 .pme_ucode = 1 << 4,
2330 },
2331 { .pme_uname = "DIRECTED_PROBE",
2332 .pme_udesc = "Directed Probe",
2333 .pme_ucode = 1 << 5,
2334 },
2335 { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLK",
2336 .pme_udesc = "Track Cache Stat for RdBlk",
2337 .pme_ucode = 1 << 6,
2338 },
2339 { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLKS",
2340 .pme_udesc = "Track Cache Stat for RdBlkS",
2341 .pme_ucode = 1 << 7,
2342 },
2343 { .pme_uname = "ALL",
2344 .pme_udesc = "All sub-events selected",
2345 .pme_ucode = 0xFF,
2346 },
2347 },
2348 },
2349/* 112 */{.pme_name = "REQUEST_CACHE_STATUS_1",
2350 .pme_code = 0x1EB,
2351 .pme_desc = "Request Cache Status 1",
2352 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2353 .pme_numasks = 9,
2354 .pme_umasks = {
2355 { .pme_uname = "PROBE_HIT_S",
2356 .pme_udesc = "Probe Hit S",
2357 .pme_ucode = 1 << 0,
2358 },
2359 { .pme_uname = "PROBE_HIT_E",
2360 .pme_udesc = "Probe Hit E",
2361 .pme_ucode = 1 << 1,
2362 },
2363 { .pme_uname = "PROBE_HIT_MUW_OR_O",
2364 .pme_udesc = "Probe Hit MuW or O",
2365 .pme_ucode = 1 << 2,
2366 },
2367 { .pme_uname = "PROBE_HIT_M",
2368 .pme_udesc = "Probe Hit M",
2369 .pme_ucode = 1 << 3,
2370 },
2371 { .pme_uname = "PROBE_MISS",
2372 .pme_udesc = "Probe Miss",
2373 .pme_ucode = 1 << 4,
2374 },
2375 { .pme_uname = "DIRECTED_PROBE",
2376 .pme_udesc = "Directed Probe",
2377 .pme_ucode = 1 << 5,
2378 },
2379 { .pme_uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY",
2380 .pme_udesc = "Track Cache Stat for ChgToDirty",
2381 .pme_ucode = 1 << 6,
2382 },
2383 { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLKM",
2384 .pme_udesc = "Track Cache Stat for RdBlkM",
2385 .pme_ucode = 1 << 7,
2386 },
2387 { .pme_uname = "ALL",
2388 .pme_udesc = "All sub-events selected",
2389 .pme_ucode = 0xFF,
2390 },
2391 },
2392 },
2393/* 113 */{.pme_name = "L3_LATENCY",
2394 .pme_code = 0x4EF,
2395 .pme_desc = "L3 Latency",
2396 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2397 .pme_numasks = 3,
2398 .pme_umasks = {
2399 { .pme_uname = "L3CYCCOUNT",
2400 .pme_udesc = "L3CycCount. L3 Request cycle count",
2401 .pme_ucode = 1 << 0,
2402 },
2403 { .pme_uname = "L3REQCOUNT",
2404 .pme_udesc = "L3ReqCount. L3 request count",
2405 .pme_ucode = 1 << 1,
2406 },
2407 { .pme_uname = "ALL",
2408 .pme_udesc = "All sub-events selected",
2409 .pme_ucode = 0x03,
2410 },
2411 },
2412 },
2413#endif
2414};
2415
2416#define PME_AMD64_FAM15H_EVENT_COUNT (sizeof(amd64_fam15h_pe)/sizeof(pme_amd64_entry_t))
2417#define PME_AMD64_FAM15H_CPU_CLK_UNHALTED 30
2418#define PME_AMD64_FAM15H_RETIRED_INSTRUCTIONS 49
amd64_fam15h_pe
static pme_amd64_entry_t amd64_fam15h_pe[]
Definition: amd64_events_fam15h.h:40
PFMLIB_AMD64_UMASK_COMBO
#define PFMLIB_AMD64_UMASK_COMBO
Definition: pfmlib_amd64_priv.h:113
pme_amd64_entry_t
Definition: pfmlib_amd64_priv.h:59
pme_amd64_entry_t::pme_name
char * pme_name
Definition: pfmlib_amd64_priv.h:60