PAPI 7.1.0.0
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amd64_events_fam10h.h
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1/*
2 * Copyright (c) 2007 Advanced Micro Devices, Inc.
3 * Contributed by Robert Richter <robert.richter@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
16 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
17 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
18 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
19 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * This file is part of libpfm, a performance monitoring support library for
23 * applications on Linux.
24 */
25
26/* History
27 *
28 * Feb 06 2009 -- Robert Richter, robert.richter@amd.com:
29 *
30 * Update for Family 10h RevD (Istanbul) from: BIOS and Kernel
31 * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev
32 * 3.20 - February 04, 2009
33 *
34 * Update for Family 10h RevC (Shanghai) from: BIOS and Kernel
35 * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev
36 * 3.20 - February 04, 2009
37 *
38 *
39 * Dec 12 2007 -- Robert Richter, robert.richter@amd.com:
40 *
41 * Created from: BIOS and Kernel Developer's Guide (BKDG) For AMD
42 * Family 10h Processors, 31116 Rev 3.00 - September 07, 2007
43 */
44
45static pme_amd64_entry_t amd64_fam10h_pe[]={
46
47/* Family 10h RevB, Barcelona */
48
49/* 0 */{.pme_name = "DISPATCHED_FPU",
50 .pme_code = 0x00,
51 .pme_desc = "Dispatched FPU Operations",
52 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
53 .pme_numasks = 7,
54 .pme_umasks = {
55 { .pme_uname = "OPS_ADD",
56 .pme_udesc = "Add pipe ops excluding load ops and SSE move ops",
57 .pme_ucode = 0x01,
58 },
59 { .pme_uname = "OPS_MULTIPLY",
60 .pme_udesc = "Multiply pipe ops excluding load ops and SSE move ops",
61 .pme_ucode = 0x02,
62 },
63 { .pme_uname = "OPS_STORE",
64 .pme_udesc = "Store pipe ops excluding load ops and SSE move ops",
65 .pme_ucode = 0x04,
66 },
67 { .pme_uname = "OPS_ADD_PIPE_LOAD_OPS",
68 .pme_udesc = "Add pipe load ops and SSE move ops",
69 .pme_ucode = 0x08,
70 },
71 { .pme_uname = "OPS_MULTIPLY_PIPE_LOAD_OPS",
72 .pme_udesc = "Multiply pipe load ops and SSE move ops",
73 .pme_ucode = 0x10,
74 },
75 { .pme_uname = "OPS_STORE_PIPE_LOAD_OPS",
76 .pme_udesc = "Store pipe load ops and SSE move ops",
77 .pme_ucode = 0x20,
78 },
79 { .pme_uname = "ALL",
80 .pme_udesc = "All sub-events selected",
81 .pme_ucode = 0x3F,
82 },
83 },
84 },
85/* 1 */{.pme_name = "CYCLES_NO_FPU_OPS_RETIRED",
86 .pme_code = 0x01,
87 .pme_desc = "Cycles in which the FPU is Empty",
88 },
89/* 2 */{.pme_name = "DISPATCHED_FPU_OPS_FAST_FLAG",
90 .pme_code = 0x02,
91 .pme_desc = "Dispatched Fast Flag FPU Operations",
92 },
93/* 3 */{.pme_name = "RETIRED_SSE_OPERATIONS",
94 .pme_code = 0x03,
95 .pme_desc = "Retired SSE Operations",
96 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
97 .pme_numasks = 8,
98 .pme_umasks = {
99 { .pme_uname = "SINGLE_ADD_SUB_OPS",
100 .pme_udesc = "Single precision add/subtract ops",
101 .pme_ucode = 0x01,
102 },
103 { .pme_uname = "SINGLE_MUL_OPS",
104 .pme_udesc = "Single precision multiply ops",
105 .pme_ucode = 0x02,
106 },
107 { .pme_uname = "SINGLE_DIV_OPS",
108 .pme_udesc = "Single precision divide/square root ops",
109 .pme_ucode = 0x04,
110 },
111 { .pme_uname = "DOUBLE_ADD_SUB_OPS",
112 .pme_udesc = "Double precision add/subtract ops",
113 .pme_ucode = 0x08,
114 },
115 { .pme_uname = "DOUBLE_MUL_OPS",
116 .pme_udesc = "Double precision multiply ops",
117 .pme_ucode = 0x10,
118 },
119 { .pme_uname = "DOUBLE_DIV_OPS",
120 .pme_udesc = "Double precision divide/square root ops",
121 .pme_ucode = 0x20,
122 },
123 { .pme_uname = "OP_TYPE",
124 .pme_udesc = "Op type: 0=uops. 1=FLOPS",
125 .pme_ucode = 0x40,
126 },
127 { .pme_uname = "ALL",
128 .pme_udesc = "All sub-events selected",
129 .pme_ucode = 0x7F,
130 },
131 },
132 },
133/* 4 */{.pme_name = "RETIRED_MOVE_OPS",
134 .pme_code = 0x04,
135 .pme_desc = "Retired Move Ops",
136 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
137 .pme_numasks = 5,
138 .pme_umasks = {
139 { .pme_uname = "LOW_QW_MOVE_UOPS",
140 .pme_udesc = "Merging low quadword move uops",
141 .pme_ucode = 0x01,
142 },
143 { .pme_uname = "HIGH_QW_MOVE_UOPS",
144 .pme_udesc = "Merging high quadword move uops",
145 .pme_ucode = 0x02,
146 },
147 { .pme_uname = "ALL_OTHER_MERGING_MOVE_UOPS",
148 .pme_udesc = "All other merging move uops",
149 .pme_ucode = 0x04,
150 },
151 { .pme_uname = "ALL_OTHER_MOVE_UOPS",
152 .pme_udesc = "All other move uops",
153 .pme_ucode = 0x08,
154 },
155 { .pme_uname = "ALL",
156 .pme_udesc = "All sub-events selected",
157 .pme_ucode = 0x0F,
158 },
159 },
160 },
161/* 5 */{.pme_name = "RETIRED_SERIALIZING_OPS",
162 .pme_code = 0x05,
163 .pme_desc = "Retired Serializing Ops",
164 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
165 .pme_numasks = 5,
166 .pme_umasks = {
167 { .pme_uname = "SSE_BOTTOM_EXECUTING_UOPS",
168 .pme_udesc = "SSE bottom-executing uops retired",
169 .pme_ucode = 0x01,
170 },
171 { .pme_uname = "SSE_BOTTOM_SERIALIZING_UOPS",
172 .pme_udesc = "SSE bottom-serializing uops retired",
173 .pme_ucode = 0x02,
174 },
175 { .pme_uname = "X87_BOTTOM_EXECUTING_UOPS",
176 .pme_udesc = "x87 bottom-executing uops retired",
177 .pme_ucode = 0x04,
178 },
179 { .pme_uname = "X87_BOTTOM_SERIALIZING_UOPS",
180 .pme_udesc = "x87 bottom-serializing uops retired",
181 .pme_ucode = 0x08,
182 },
183 { .pme_uname = "ALL",
184 .pme_udesc = "All sub-events selected",
185 .pme_ucode = 0x0F,
186 },
187 },
188 },
189/* 6 */{.pme_name = "FP_SCHEDULER_CYCLES",
190 .pme_code = 0x06,
191 .pme_desc = "Number of Cycles that a Serializing uop is in the FP Scheduler",
192 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
193 .pme_numasks = 3,
194 .pme_umasks = {
195 { .pme_uname = "BOTTOM_EXECUTE_CYCLES",
196 .pme_udesc = "Number of cycles a bottom-execute uop is in the FP scheduler",
197 .pme_ucode = 0x01,
198 },
199 { .pme_uname = "BOTTOM_SERIALIZING_CYCLES",
200 .pme_udesc = "Number of cycles a bottom-serializing uop is in the FP scheduler",
201 .pme_ucode = 0x02,
202 },
203 { .pme_uname = "ALL",
204 .pme_udesc = "All sub-events selected",
205 .pme_ucode = 0x03,
206 },
207 },
208 },
209/* 7 */{.pme_name = "SEGMENT_REGISTER_LOADS",
210 .pme_code = 0x20,
211 .pme_desc = "Segment Register Loads",
212 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
213 .pme_numasks = 8,
214 .pme_umasks = {
215 { .pme_uname = "ES",
216 .pme_udesc = "ES",
217 .pme_ucode = 0x01,
218 },
219 { .pme_uname = "CS",
220 .pme_udesc = "CS",
221 .pme_ucode = 0x02,
222 },
223 { .pme_uname = "SS",
224 .pme_udesc = "SS",
225 .pme_ucode = 0x04,
226 },
227 { .pme_uname = "DS",
228 .pme_udesc = "DS",
229 .pme_ucode = 0x08,
230 },
231 { .pme_uname = "FS",
232 .pme_udesc = "FS",
233 .pme_ucode = 0x10,
234 },
235 { .pme_uname = "GS",
236 .pme_udesc = "GS",
237 .pme_ucode = 0x20,
238 },
239 { .pme_uname = "HS",
240 .pme_udesc = "HS",
241 .pme_ucode = 0x40,
242 },
243 { .pme_uname = "ALL",
244 .pme_udesc = "All sub-events selected",
245 .pme_ucode = 0x7F,
246 },
247 },
248 },
249/* 8 */{.pme_name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
250 .pme_code = 0x21,
251 .pme_desc = "Pipeline Restart Due to Self-Modifying Code",
252 },
253/* 9 */{.pme_name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
254 .pme_code = 0x22,
255 .pme_desc = "Pipeline Restart Due to Probe Hit",
256 },
257/* 10 */{.pme_name = "LS_BUFFER_2_FULL_CYCLES",
258 .pme_code = 0x23,
259 .pme_desc = "LS Buffer 2 Full",
260 },
261/* 11 */{.pme_name = "LOCKED_OPS",
262 .pme_code = 0x24,
263 .pme_desc = "Locked Operations",
264 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
265 .pme_numasks = 5,
266 .pme_umasks = {
267 { .pme_uname = "EXECUTED",
268 .pme_udesc = "The number of locked instructions executed",
269 .pme_ucode = 0x01,
270 },
271 { .pme_uname = "CYCLES_SPECULATIVE_PHASE",
272 .pme_udesc = "The number of cycles spent in speculative phase",
273 .pme_ucode = 0x02,
274 },
275 { .pme_uname = "CYCLES_NON_SPECULATIVE_PHASE",
276 .pme_udesc = "The number of cycles spent in non-speculative phase (including cache miss penalty)",
277 .pme_ucode = 0x04,
278 },
279 { .pme_uname = "CYCLES_WAITING",
280 .pme_udesc = "The number of cycles waiting for a cache hit (cache miss penalty).",
281 .pme_ucode = 0x08,
282 },
283 { .pme_uname = "ALL",
284 .pme_udesc = "All sub-events selected",
285 .pme_ucode = 0x0F,
286 },
287 },
288 },
289/* 12 */{.pme_name = "RETIRED_CLFLUSH_INSTRUCTIONS",
290 .pme_code = 0x26,
291 .pme_desc = "Retired CLFLUSH Instructions",
292 },
293/* 13 */{.pme_name = "RETIRED_CPUID_INSTRUCTIONS",
294 .pme_code = 0x27,
295 .pme_desc = "Retired CPUID Instructions",
296 },
297/* 14 */{.pme_name = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS",
298 .pme_code = 0x2A,
299 .pme_desc = "Cancelled Store to Load Forward Operations",
300 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
301 .pme_numasks = 4,
302 .pme_umasks = {
303 { .pme_uname = "ADDRESS_MISMATCHES",
304 .pme_udesc = "Address mismatches (starting byte not the same).",
305 .pme_ucode = 0x01,
306 },
307 { .pme_uname = "STORE_IS_SMALLER_THAN_LOAD",
308 .pme_udesc = "Store is smaller than load.",
309 .pme_ucode = 0x02,
310 },
311 { .pme_uname = "MISALIGNED",
312 .pme_udesc = "Misaligned.",
313 .pme_ucode = 0x04,
314 },
315 { .pme_uname = "ALL",
316 .pme_udesc = "All sub-events selected",
317 .pme_ucode = 0x07,
318 },
319 },
320 },
321/* 15 */{.pme_name = "SMIS_RECEIVED",
322 .pme_code = 0x2B,
323 .pme_desc = "SMIs Received",
324 },
325/* 16 */{.pme_name = "DATA_CACHE_ACCESSES",
326 .pme_code = 0x40,
327 .pme_desc = "Data Cache Accesses",
328 },
329/* 17 */{.pme_name = "DATA_CACHE_MISSES",
330 .pme_code = 0x41,
331 .pme_desc = "Data Cache Misses",
332 },
333/* 18 */{.pme_name = "DATA_CACHE_REFILLS",
334 .pme_code = 0x42,
335 .pme_desc = "Data Cache Refills from L2 or Northbridge",
336 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
337 .pme_numasks = 6,
338 .pme_umasks = {
339 { .pme_uname = "SYSTEM",
340 .pme_udesc = "Refill from the Northbridge",
341 .pme_ucode = 0x01,
342 },
343 { .pme_uname = "L2_SHARED",
344 .pme_udesc = "Shared-state line from L2",
345 .pme_ucode = 0x02,
346 },
347 { .pme_uname = "L2_EXCLUSIVE",
348 .pme_udesc = "Exclusive-state line from L2",
349 .pme_ucode = 0x04,
350 },
351 { .pme_uname = "L2_OWNED",
352 .pme_udesc = "Owned-state line from L2",
353 .pme_ucode = 0x08,
354 },
355 { .pme_uname = "L2_MODIFIED",
356 .pme_udesc = "Modified-state line from L2",
357 .pme_ucode = 0x10,
358 },
359 { .pme_uname = "ALL",
360 .pme_udesc = "All sub-events selected",
361 .pme_ucode = 0x1F,
362 },
363 },
364 },
365/* 19 */{.pme_name = "DATA_CACHE_REFILLS_FROM_SYSTEM",
366 .pme_code = 0x43,
367 .pme_desc = "Data Cache Refills from the Northbridge",
368 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
369 .pme_numasks = 6,
370 .pme_umasks = {
371 { .pme_uname = "INVALID",
372 .pme_udesc = "Invalid",
373 .pme_ucode = 0x01,
374 },
375 { .pme_uname = "SHARED",
376 .pme_udesc = "Shared",
377 .pme_ucode = 0x02,
378 },
379 { .pme_uname = "EXCLUSIVE",
380 .pme_udesc = "Exclusive",
381 .pme_ucode = 0x04,
382 },
383 { .pme_uname = "OWNED",
384 .pme_udesc = "Owned",
385 .pme_ucode = 0x08,
386 },
387 { .pme_uname = "MODIFIED",
388 .pme_udesc = "Modified",
389 .pme_ucode = 0x10,
390 },
391 { .pme_uname = "ALL",
392 .pme_udesc = "All sub-events selected",
393 .pme_ucode = 0x1F,
394 },
395 },
396 },
397/* 20 */{.pme_name = "DATA_CACHE_LINES_EVICTED",
398 .pme_code = 0x44,
399 .pme_desc = "Data Cache Lines Evicted",
400 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
401 .pme_numasks = 8,
402 .pme_umasks = {
403 { .pme_uname = "INVALID",
404 .pme_udesc = "Invalid",
405 .pme_ucode = 0x01,
406 },
407 { .pme_uname = "SHARED",
408 .pme_udesc = "Shared",
409 .pme_ucode = 0x02,
410 },
411 { .pme_uname = "EXCLUSIVE",
412 .pme_udesc = "Exclusive",
413 .pme_ucode = 0x04,
414 },
415 { .pme_uname = "OWNED",
416 .pme_udesc = "Owned",
417 .pme_ucode = 0x08,
418 },
419 { .pme_uname = "MODIFIED",
420 .pme_udesc = "Modified",
421 .pme_ucode = 0x10,
422 },
423 { .pme_uname = "BY_PREFETCHNTA",
424 .pme_udesc = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.",
425 .pme_ucode = 0x20,
426 },
427 { .pme_uname = "NOT_BY_PREFETCHNTA",
428 .pme_udesc = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.",
429 .pme_ucode = 0x40,
430 },
431 { .pme_uname = "ALL",
432 .pme_udesc = "All sub-events selected",
433 .pme_ucode = 0x7F,
434 },
435 },
436 },
437/* 21 */{.pme_name = "L1_DTLB_MISS_AND_L2_DTLB_HIT",
438 .pme_code = 0x45,
439 .pme_desc = "L1 DTLB Miss and L2 DTLB Hit",
440 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
441 .pme_numasks = 5,
442 .pme_umasks = {
443 { .pme_uname = "L2_4K_TLB_HIT",
444 .pme_udesc = "L2 4K TLB hit",
445 .pme_ucode = 0x01,
446 },
447 { .pme_uname = "L2_2M_TLB_HIT",
448 .pme_udesc = "L2 2M TLB hit",
449 .pme_ucode = 0x02,
450 },
451 { .pme_uname = "ALL",
452 .pme_udesc = "All sub-events selected",
453 .pme_ucode = 0x03,
454 .pme_uflags = PFMLIB_AMD64_TILL_FAM10H_REV_B,
455 },
456 { .pme_uname = "L2_1G_TLB_HIT",
457 .pme_udesc = "L2 1G TLB hit",
458 .pme_ucode = 0x04,
459 .pme_uflags = PFMLIB_AMD64_FAM10H_REV_C,
460 },
461 { .pme_uname = "ALL",
462 .pme_udesc = "All sub-events selected",
463 .pme_ucode = 0x07,
464 .pme_uflags = PFMLIB_AMD64_FAM10H_REV_C,
465 },
466 },
467 },
468/* 22 */{.pme_name = "L1_DTLB_AND_L2_DTLB_MISS",
469 .pme_code = 0x46,
470 .pme_desc = "L1 DTLB and L2 DTLB Miss",
471 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
472 .pme_numasks = 4,
473 .pme_umasks = {
474 { .pme_uname = "4K_TLB_RELOAD",
475 .pme_udesc = "4K TLB reload",
476 .pme_ucode = 0x01,
477 },
478 { .pme_uname = "2M_TLB_RELOAD",
479 .pme_udesc = "2M TLB reload",
480 .pme_ucode = 0x02,
481 },
482 { .pme_uname = "1G_TLB_RELOAD",
483 .pme_udesc = "1G TLB reload",
484 .pme_ucode = 0x04,
485 },
486 { .pme_uname = "ALL",
487 .pme_udesc = "All sub-events selected",
488 .pme_ucode = 0x07,
489 },
490 },
491 },
492/* 23 */{.pme_name = "MISALIGNED_ACCESSES",
493 .pme_code = 0x47,
494 .pme_desc = "Misaligned Accesses",
495 },
496/* 24 */{.pme_name = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS",
497 .pme_code = 0x48,
498 .pme_desc = "Microarchitectural Late Cancel of an Access",
499 },
500/* 25 */{.pme_name = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS",
501 .pme_code = 0x49,
502 .pme_desc = "Microarchitectural Early Cancel of an Access",
503 },
504/* 26 */{.pme_name = "SCRUBBER_SINGLE_BIT_ECC_ERRORS",
505 .pme_code = 0x4A,
506 .pme_desc = "Single-bit ECC Errors Recorded by Scrubber",
507 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
508 .pme_numasks = 5,
509 .pme_umasks = {
510 { .pme_uname = "SCRUBBER_ERROR",
511 .pme_udesc = "Scrubber error",
512 .pme_ucode = 0x01,
513 },
514 { .pme_uname = "PIGGYBACK_ERROR",
515 .pme_udesc = "Piggyback scrubber errors",
516 .pme_ucode = 0x02,
517 },
518 { .pme_uname = "LOAD_PIPE_ERROR",
519 .pme_udesc = "Load pipe error",
520 .pme_ucode = 0x04,
521 },
522 { .pme_uname = "STORE_WRITE_PIPE_ERROR",
523 .pme_udesc = "Store write pipe error",
524 .pme_ucode = 0x08,
525 },
526 { .pme_uname = "ALL",
527 .pme_udesc = "All sub-events selected",
528 .pme_ucode = 0x0F,
529 },
530 },
531 },
532/* 27 */{.pme_name = "PREFETCH_INSTRUCTIONS_DISPATCHED",
533 .pme_code = 0x4B,
534 .pme_desc = "Prefetch Instructions Dispatched",
535 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
536 .pme_numasks = 4,
537 .pme_umasks = {
538 { .pme_uname = "LOAD",
539 .pme_udesc = "Load (Prefetch, PrefetchT0/T1/T2)",
540 .pme_ucode = 0x01,
541 },
542 { .pme_uname = "STORE",
543 .pme_udesc = "Store (PrefetchW)",
544 .pme_ucode = 0x02,
545 },
546 { .pme_uname = "NTA",
547 .pme_udesc = "NTA (PrefetchNTA)",
548 .pme_ucode = 0x04,
549 },
550 { .pme_uname = "ALL",
551 .pme_udesc = "All sub-events selected",
552 .pme_ucode = 0x07,
553 },
554 },
555 },
556/* 28 */{.pme_name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
557 .pme_code = 0x4C,
558 .pme_desc = "DCACHE Misses by Locked Instructions",
559 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
560 .pme_numasks = 2,
561 .pme_umasks = {
562 { .pme_uname = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
563 .pme_udesc = "Data cache misses by locked instructions",
564 .pme_ucode = 0x02,
565 },
566 { .pme_uname = "ALL",
567 .pme_udesc = "All sub-events selected",
568 .pme_ucode = 0x02,
569 },
570 },
571 },
572/* 29 */{.pme_name = "L1_DTLB_HIT",
573 .pme_code = 0x4D,
574 .pme_desc = "L1 DTLB Hit",
575 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
576 .pme_numasks = 4,
577 .pme_umasks = {
578 { .pme_uname = "L1_4K_TLB_HIT",
579 .pme_udesc = "L1 4K TLB hit",
580 .pme_ucode = 0x01,
581 },
582 { .pme_uname = "L1_2M_TLB_HIT",
583 .pme_udesc = "L1 2M TLB hit",
584 .pme_ucode = 0x02,
585 },
586 { .pme_uname = "L1_1G_TLB_HIT",
587 .pme_udesc = "L1 1G TLB hit",
588 .pme_ucode = 0x04,
589 },
590 { .pme_uname = "ALL",
591 .pme_udesc = "All sub-events selected",
592 .pme_ucode = 0x07,
593 },
594 },
595 },
596/* 30 */{.pme_name = "INEFFECTIVE_SW_PREFETCHES",
597 .pme_code = 0x52,
598 .pme_desc = "Ineffective Software Prefetches",
599 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
600 .pme_numasks = 3,
601 .pme_umasks = {
602 { .pme_uname = "SW_PREFETCH_HIT_IN_L1",
603 .pme_udesc = "Software prefetch hit in the L1.",
604 .pme_ucode = 0x01,
605 },
606 { .pme_uname = "SW_PREFETCH_HIT_IN_L2",
607 .pme_udesc = "Software prefetch hit in L2.",
608 .pme_ucode = 0x08,
609 },
610 { .pme_uname = "ALL",
611 .pme_udesc = "All sub-events selected",
612 .pme_ucode = 0x09,
613 },
614 },
615 },
616/* 31 */{.pme_name = "GLOBAL_TLB_FLUSHES",
617 .pme_code = 0x54,
618 .pme_desc = "Global TLB Flushes",
619 },
620/* 32 */{.pme_name = "MEMORY_REQUESTS",
621 .pme_code = 0x65,
622 .pme_desc = "Memory Requests by Type",
623 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
624 .pme_numasks = 4,
625 .pme_umasks = {
626 { .pme_uname = "NON_CACHEABLE",
627 .pme_udesc = "Requests to non-cacheable (UC) memory",
628 .pme_ucode = 0x01,
629 },
630 { .pme_uname = "WRITE_COMBINING",
631 .pme_udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",
632 .pme_ucode = 0x02,
633 },
634 { .pme_uname = "STREAMING_STORE",
635 .pme_udesc = "Streaming store (SS) requests",
636 .pme_ucode = 0x80,
637 },
638 { .pme_uname = "ALL",
639 .pme_udesc = "All sub-events selected",
640 .pme_ucode = 0x83,
641 },
642 },
643 },
644/* 33 */{.pme_name = "DATA_PREFETCHES",
645 .pme_code = 0x67,
646 .pme_desc = "Data Prefetcher",
647 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
648 .pme_numasks = 3,
649 .pme_umasks = {
650 { .pme_uname = "CANCELLED",
651 .pme_udesc = "Cancelled prefetches",
652 .pme_ucode = 0x01,
653 },
654 { .pme_uname = "ATTEMPTED",
655 .pme_udesc = "Prefetch attempts",
656 .pme_ucode = 0x02,
657 },
658 { .pme_uname = "ALL",
659 .pme_udesc = "All sub-events selected",
660 .pme_ucode = 0x03,
661 },
662 },
663 },
664/* 34 */{.pme_name = "SYSTEM_READ_RESPONSES",
665 .pme_code = 0x6C,
666 .pme_desc = "Northbridge Read Responses by Coherency State",
667 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
668 .pme_numasks = 6,
669 .pme_umasks = {
670 { .pme_uname = "EXCLUSIVE",
671 .pme_udesc = "Exclusive",
672 .pme_ucode = 0x01,
673 },
674 { .pme_uname = "MODIFIED",
675 .pme_udesc = "Modified",
676 .pme_ucode = 0x02,
677 },
678 { .pme_uname = "SHARED",
679 .pme_udesc = "Shared",
680 .pme_ucode = 0x04,
681 },
682 { .pme_uname = "OWNED",
683 .pme_udesc = "Owned",
684 .pme_ucode = 0x08,
685 },
686 { .pme_uname = "DATA_ERROR",
687 .pme_udesc = "Data Error",
688 .pme_ucode = 0x10,
689 },
690 { .pme_uname = "ALL",
691 .pme_udesc = "All sub-events selected",
692 .pme_ucode = 0x1F,
693 },
694 },
695 },
696/* 35 */{.pme_name = "QUADWORDS_WRITTEN_TO_SYSTEM",
697 .pme_code = 0x6D,
698 .pme_desc = "Octwords Written to System",
699 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
700 .pme_numasks = 2,
701 .pme_umasks = {
702 { .pme_uname = "QUADWORD_WRITE_TRANSFER",
703 .pme_udesc = "Octword write transfer",
704 .pme_ucode = 0x01,
705 },
706 { .pme_uname = "ALL",
707 .pme_udesc = "All sub-events selected",
708 .pme_ucode = 0x01,
709 },
710 },
711 },
712/* 36 */{.pme_name = "CPU_CLK_UNHALTED",
713 .pme_code = 0x76,
714 .pme_desc = "CPU Clocks not Halted",
715 },
716/* 37 */{.pme_name = "REQUESTS_TO_L2",
717 .pme_code = 0x7D,
718 .pme_desc = "Requests to L2 Cache",
719 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
720 .pme_numasks = 7,
721 .pme_umasks = {
722 { .pme_uname = "INSTRUCTIONS",
723 .pme_udesc = "IC fill",
724 .pme_ucode = 0x01,
725 },
726 { .pme_uname = "DATA",
727 .pme_udesc = "DC fill",
728 .pme_ucode = 0x02,
729 },
730 { .pme_uname = "TLB_WALK",
731 .pme_udesc = "TLB fill (page table walks)",
732 .pme_ucode = 0x04,
733 },
734 { .pme_uname = "SNOOP",
735 .pme_udesc = "Tag snoop request",
736 .pme_ucode = 0x08,
737 },
738 { .pme_uname = "CANCELLED",
739 .pme_udesc = "Cancelled request",
740 .pme_ucode = 0x10,
741 },
742 { .pme_uname = "HW_PREFETCH_FROM_DC",
743 .pme_udesc = "Hardware prefetch from DC",
744 .pme_ucode = 0x20,
745 },
746 { .pme_uname = "ALL",
747 .pme_udesc = "All sub-events selected",
748 .pme_ucode = 0x3F,
749 },
750 },
751 },
752/* 38 */{.pme_name = "L2_CACHE_MISS",
753 .pme_code = 0x7E,
754 .pme_desc = "L2 Cache Misses",
755 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
756 .pme_numasks = 5,
757 .pme_umasks = {
758 { .pme_uname = "INSTRUCTIONS",
759 .pme_udesc = "IC fill",
760 .pme_ucode = 0x01,
761 },
762 { .pme_uname = "DATA",
763 .pme_udesc = "DC fill (includes possible replays, whereas EventSelect 041h does not)",
764 .pme_ucode = 0x02,
765 },
766 { .pme_uname = "TLB_WALK",
767 .pme_udesc = "TLB page table walk",
768 .pme_ucode = 0x04,
769 },
770 { .pme_uname = "HW_PREFETCH_FROM_DC",
771 .pme_udesc = "Hardware prefetch from DC",
772 .pme_ucode = 0x08,
773 },
774 { .pme_uname = "ALL",
775 .pme_udesc = "All sub-events selected",
776 .pme_ucode = 0x0F,
777 },
778 },
779 },
780/* 39 */{.pme_name = "L2_FILL_WRITEBACK",
781 .pme_code = 0x7F,
782 .pme_desc = "L2 Fill/Writeback",
783 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
784 .pme_numasks = 3,
785 .pme_umasks = {
786 { .pme_uname = "L2_FILLS",
787 .pme_udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",
788 .pme_ucode = 0x01,
789 },
790 { .pme_uname = "L2_WRITEBACKS",
791 .pme_udesc = "L2 Writebacks to system.",
792 .pme_ucode = 0x02,
793 },
794 { .pme_uname = "ALL",
795 .pme_udesc = "All sub-events selected",
796 .pme_ucode = 0x03,
797 },
798 },
799 },
800/* 40 */{.pme_name = "INSTRUCTION_CACHE_FETCHES",
801 .pme_code = 0x80,
802 .pme_desc = "Instruction Cache Fetches",
803 },
804/* 41 */{.pme_name = "INSTRUCTION_CACHE_MISSES",
805 .pme_code = 0x81,
806 .pme_desc = "Instruction Cache Misses",
807 },
808/* 42 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
809 .pme_code = 0x82,
810 .pme_desc = "Instruction Cache Refills from L2",
811 },
812/* 43 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
813 .pme_code = 0x83,
814 .pme_desc = "Instruction Cache Refills from System",
815 },
816/* 44 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
817 .pme_code = 0x84,
818 .pme_desc = "L1 ITLB Miss and L2 ITLB Hit",
819 },
820/* 45 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
821 .pme_code = 0x85,
822 .pme_desc = "L1 ITLB Miss and L2 ITLB Miss",
823 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
824 .pme_numasks = 3,
825 .pme_umasks = {
826 { .pme_uname = "4K_PAGE_FETCHES",
827 .pme_udesc = "Instruction fetches to a 4K page.",
828 .pme_ucode = 0x01,
829 },
830 { .pme_uname = "2M_PAGE_FETCHES",
831 .pme_udesc = "Instruction fetches to a 2M page.",
832 .pme_ucode = 0x02,
833 },
834 { .pme_uname = "ALL",
835 .pme_udesc = "All sub-events selected",
836 .pme_ucode = 0x03,
837 },
838 },
839 },
840/* 46 */{.pme_name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
841 .pme_code = 0x86,
842 .pme_desc = "Pipeline Restart Due to Instruction Stream Probe",
843 },
844/* 47 */{.pme_name = "INSTRUCTION_FETCH_STALL",
845 .pme_code = 0x87,
846 .pme_desc = "Instruction Fetch Stall",
847 },
848/* 48 */{.pme_name = "RETURN_STACK_HITS",
849 .pme_code = 0x88,
850 .pme_desc = "Return Stack Hits",
851 },
852/* 49 */{.pme_name = "RETURN_STACK_OVERFLOWS",
853 .pme_code = 0x89,
854 .pme_desc = "Return Stack Overflows",
855 },
856/* 50 */{.pme_name = "INSTRUCTION_CACHE_VICTIMS",
857 .pme_code = 0x8B,
858 .pme_desc = "Instruction Cache Victims",
859 },
860/* 51 */{.pme_name = "INSTRUCTION_CACHE_LINES_INVALIDATED",
861 .pme_code = 0x8C,
862 .pme_desc = "Instruction Cache Lines Invalidated",
863 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
864 .pme_numasks = 3,
865 .pme_umasks = {
866 { .pme_uname = "INVALIDATING_PROBE_NO_IN_FLIGHT",
867 .pme_udesc = "Invalidating probe that did not hit any in-flight instructions.",
868 .pme_ucode = 0x01,
869 },
870 { .pme_uname = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT",
871 .pme_udesc = "Invalidating probe that hit one or more in-flight instructions.",
872 .pme_ucode = 0x02,
873 },
874 { .pme_uname = "ALL",
875 .pme_udesc = "All sub-events selected",
876 .pme_ucode = 0x03,
877 },
878 },
879 },
880/* 52 */{.pme_name = "ITLB_RELOADS",
881 .pme_code = 0x99,
882 .pme_desc = "ITLB Reloads",
883 },
884/* 53 */{.pme_name = "ITLB_RELOADS_ABORTED",
885 .pme_code = 0x9A,
886 .pme_desc = "ITLB Reloads Aborted",
887 },
888/* 54 */{.pme_name = "RETIRED_INSTRUCTIONS",
889 .pme_code = 0xC0,
890 .pme_desc = "Retired Instructions",
891 },
892/* 55 */{.pme_name = "RETIRED_UOPS",
893 .pme_code = 0xC1,
894 .pme_desc = "Retired uops",
895 },
896/* 56 */{.pme_name = "RETIRED_BRANCH_INSTRUCTIONS",
897 .pme_code = 0xC2,
898 .pme_desc = "Retired Branch Instructions",
899 },
900/* 57 */{.pme_name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
901 .pme_code = 0xC3,
902 .pme_desc = "Retired Mispredicted Branch Instructions",
903 },
904/* 58 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
905 .pme_code = 0xC4,
906 .pme_desc = "Retired Taken Branch Instructions",
907 },
908/* 59 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
909 .pme_code = 0xC5,
910 .pme_desc = "Retired Taken Branch Instructions Mispredicted",
911 },
912/* 60 */{.pme_name = "RETIRED_FAR_CONTROL_TRANSFERS",
913 .pme_code = 0xC6,
914 .pme_desc = "Retired Far Control Transfers",
915 },
916/* 61 */{.pme_name = "RETIRED_BRANCH_RESYNCS",
917 .pme_code = 0xC7,
918 .pme_desc = "Retired Branch Resyncs",
919 },
920/* 62 */{.pme_name = "RETIRED_NEAR_RETURNS",
921 .pme_code = 0xC8,
922 .pme_desc = "Retired Near Returns",
923 },
924/* 63 */{.pme_name = "RETIRED_NEAR_RETURNS_MISPREDICTED",
925 .pme_code = 0xC9,
926 .pme_desc = "Retired Near Returns Mispredicted",
927 },
928/* 64 */{.pme_name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
929 .pme_code = 0xCA,
930 .pme_desc = "Retired Indirect Branches Mispredicted",
931 },
932/* 65 */{.pme_name = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
933 .pme_code = 0xCB,
934 .pme_desc = "Retired MMX/FP Instructions",
935 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
936 .pme_numasks = 4,
937 .pme_umasks = {
938 { .pme_uname = "X87",
939 .pme_udesc = "x87 instructions",
940 .pme_ucode = 0x01,
941 },
942 { .pme_uname = "MMX_AND_3DNOW",
943 .pme_udesc = "MMX and 3DNow! instructions",
944 .pme_ucode = 0x02,
945 },
946 { .pme_uname = "PACKED_SSE_AND_SSE2",
947 .pme_udesc = "SSE instructions (SSE, SSE2, SSE3, and SSE4A)",
948 .pme_ucode = 0x04,
949 },
950 { .pme_uname = "ALL",
951 .pme_udesc = "All sub-events selected",
952 .pme_ucode = 0x07,
953 },
954 },
955 },
956/* 66 */{.pme_name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS",
957 .pme_code = 0xCC,
958 .pme_desc = "Retired Fastpath Double Op Instructions",
959 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
960 .pme_numasks = 4,
961 .pme_umasks = {
962 { .pme_uname = "POSITION_0",
963 .pme_udesc = "With low op in position 0",
964 .pme_ucode = 0x01,
965 },
966 { .pme_uname = "POSITION_1",
967 .pme_udesc = "With low op in position 1",
968 .pme_ucode = 0x02,
969 },
970 { .pme_uname = "POSITION_2",
971 .pme_udesc = "With low op in position 2",
972 .pme_ucode = 0x04,
973 },
974 { .pme_uname = "ALL",
975 .pme_udesc = "All sub-events selected",
976 .pme_ucode = 0x07,
977 },
978 },
979 },
980/* 67 */{.pme_name = "INTERRUPTS_MASKED_CYCLES",
981 .pme_code = 0xCD,
982 .pme_desc = "Interrupts-Masked Cycles",
983 },
984/* 68 */{.pme_name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
985 .pme_code = 0xCE,
986 .pme_desc = "Interrupts-Masked Cycles with Interrupt Pending",
987 },
988/* 69 */{.pme_name = "INTERRUPTS_TAKEN",
989 .pme_code = 0xCF,
990 .pme_desc = "Interrupts Taken",
991 },
992/* 70 */{.pme_name = "DECODER_EMPTY",
993 .pme_code = 0xD0,
994 .pme_desc = "Decoder Empty",
995 },
996/* 71 */{.pme_name = "DISPATCH_STALLS",
997 .pme_code = 0xD1,
998 .pme_desc = "Dispatch Stalls",
999 },
1000/* 72 */{.pme_name = "DISPATCH_STALL_FOR_BRANCH_ABORT",
1001 .pme_code = 0xD2,
1002 .pme_desc = "Dispatch Stall for Branch Abort to Retire",
1003 },
1004/* 73 */{.pme_name = "DISPATCH_STALL_FOR_SERIALIZATION",
1005 .pme_code = 0xD3,
1006 .pme_desc = "Dispatch Stall for Serialization",
1007 },
1008/* 74 */{.pme_name = "DISPATCH_STALL_FOR_SEGMENT_LOAD",
1009 .pme_code = 0xD4,
1010 .pme_desc = "Dispatch Stall for Segment Load",
1011 },
1012/* 75 */{.pme_name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL",
1013 .pme_code = 0xD5,
1014 .pme_desc = "Dispatch Stall for Reorder Buffer Full",
1015 },
1016/* 76 */{.pme_name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL",
1017 .pme_code = 0xD6,
1018 .pme_desc = "Dispatch Stall for Reservation Station Full",
1019 },
1020/* 77 */{.pme_name = "DISPATCH_STALL_FOR_FPU_FULL",
1021 .pme_code = 0xD7,
1022 .pme_desc = "Dispatch Stall for FPU Full",
1023 },
1024/* 78 */{.pme_name = "DISPATCH_STALL_FOR_LS_FULL",
1025 .pme_code = 0xD8,
1026 .pme_desc = "Dispatch Stall for LS Full",
1027 },
1028/* 79 */{.pme_name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET",
1029 .pme_code = 0xD9,
1030 .pme_desc = "Dispatch Stall Waiting for All Quiet",
1031 },
1032/* 80 */{.pme_name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC",
1033 .pme_code = 0xDA,
1034 .pme_desc = "Dispatch Stall for Far Transfer or Resync to Retire",
1035 },
1036/* 81 */{.pme_name = "FPU_EXCEPTIONS",
1037 .pme_code = 0xDB,
1038 .pme_desc = "FPU Exceptions",
1039 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1040 .pme_numasks = 5,
1041 .pme_umasks = {
1042 { .pme_uname = "X87_RECLASS_MICROFAULTS",
1043 .pme_udesc = "x87 reclass microfaults",
1044 .pme_ucode = 0x01,
1045 },
1046 { .pme_uname = "SSE_RETYPE_MICROFAULTS",
1047 .pme_udesc = "SSE retype microfaults",
1048 .pme_ucode = 0x02,
1049 },
1050 { .pme_uname = "SSE_RECLASS_MICROFAULTS",
1051 .pme_udesc = "SSE reclass microfaults",
1052 .pme_ucode = 0x04,
1053 },
1054 { .pme_uname = "SSE_AND_X87_MICROTRAPS",
1055 .pme_udesc = "SSE and x87 microtraps",
1056 .pme_ucode = 0x08,
1057 },
1058 { .pme_uname = "ALL",
1059 .pme_udesc = "All sub-events selected",
1060 .pme_ucode = 0x0F,
1061 },
1062 },
1063 },
1064/* 82 */{.pme_name = "DR0_BREAKPOINT_MATCHES",
1065 .pme_code = 0xDC,
1066 .pme_desc = "DR0 Breakpoint Matches",
1067 },
1068/* 83 */{.pme_name = "DR1_BREAKPOINT_MATCHES",
1069 .pme_code = 0xDD,
1070 .pme_desc = "DR1 Breakpoint Matches",
1071 },
1072/* 84 */{.pme_name = "DR2_BREAKPOINT_MATCHES",
1073 .pme_code = 0xDE,
1074 .pme_desc = "DR2 Breakpoint Matches",
1075 },
1076/* 85 */{.pme_name = "DR3_BREAKPOINT_MATCHES",
1077 .pme_code = 0xDF,
1078 .pme_desc = "DR3 Breakpoint Matches",
1079 },
1080/* 86 */{.pme_name = "DRAM_ACCESSES_PAGE",
1081 .pme_code = 0xE0,
1082 .pme_desc = "DRAM Accesses",
1083 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1084 .pme_numasks = 7,
1085 .pme_umasks = {
1086 { .pme_uname = "HIT",
1087 .pme_udesc = "DCT0 Page hit",
1088 .pme_ucode = 0x01,
1089 },
1090 { .pme_uname = "MISS",
1091 .pme_udesc = "DCT0 Page Miss",
1092 .pme_ucode = 0x02,
1093 },
1094 { .pme_uname = "CONFLICT",
1095 .pme_udesc = "DCT0 Page Conflict",
1096 .pme_ucode = 0x04,
1097 },
1098 { .pme_uname = "DCT1_PAGE_HIT",
1099 .pme_udesc = "DCT1 Page hit",
1100 .pme_ucode = 0x08,
1101 },
1102 { .pme_uname = "DCT1_PAGE_MISS",
1103 .pme_udesc = "DCT1 Page Miss",
1104 .pme_ucode = 0x10,
1105 },
1106 { .pme_uname = "DCT1_PAGE_CONFLICT",
1107 .pme_udesc = "DCT1 Page Conflict",
1108 .pme_ucode = 0x20,
1109 },
1110 { .pme_uname = "ALL",
1111 .pme_udesc = "All sub-events selected",
1112 .pme_ucode = 0x3F,
1113 },
1114 },
1115 },
1116/* 87 */{.pme_name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS",
1117 .pme_code = 0xE1,
1118 .pme_desc = "DRAM Controller Page Table Overflows",
1119 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1120 .pme_numasks = 3,
1121 .pme_umasks = {
1122 { .pme_uname = "DCT0_PAGE_TABLE_OVERFLOW",
1123 .pme_udesc = "DCT0 Page Table Overflow",
1124 .pme_ucode = 0x01,
1125 },
1126 { .pme_uname = "DCT1_PAGE_TABLE_OVERFLOW",
1127 .pme_udesc = "DCT1 Page Table Overflow",
1128 .pme_ucode = 0x02,
1129 },
1130 { .pme_uname = "ALL",
1131 .pme_udesc = "All sub-events selected",
1132 .pme_ucode = 0x03,
1133 },
1134 },
1135 },
1136/* 88 */{.pme_name = "MEMORY_CONTROLLER_SLOT_MISSES",
1137 .pme_code = 0xE2,
1138 .pme_desc = "Memory Controller DRAM Command Slots Missed",
1139 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1140 .pme_numasks = 3,
1141 .pme_umasks = {
1142 { .pme_uname = "DCT0_COMMAND_SLOTS_MISSED",
1143 .pme_udesc = "DCT0 Command Slots Missed",
1144 .pme_ucode = 0x01,
1145 },
1146 { .pme_uname = "DCT1_COMMAND_SLOTS_MISSED",
1147 .pme_udesc = "DCT1 Command Slots Missed",
1148 .pme_ucode = 0x02,
1149 },
1150 { .pme_uname = "ALL",
1151 .pme_udesc = "All sub-events selected",
1152 .pme_ucode = 0x03,
1153 },
1154 },
1155 },
1156/* 89 */{.pme_name = "MEMORY_CONTROLLER_TURNAROUNDS",
1157 .pme_code = 0xE3,
1158 .pme_desc = "Memory Controller Turnarounds",
1159 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1160 .pme_numasks = 7,
1161 .pme_umasks = {
1162 { .pme_uname = "CHIP_SELECT",
1163 .pme_udesc = "DCT0 DIMM (chip select) turnaround",
1164 .pme_ucode = 0x01,
1165 },
1166 { .pme_uname = "READ_TO_WRITE",
1167 .pme_udesc = "DCT0 Read to write turnaround",
1168 .pme_ucode = 0x02,
1169 },
1170 { .pme_uname = "WRITE_TO_READ",
1171 .pme_udesc = "DCT0 Write to read turnaround",
1172 .pme_ucode = 0x04,
1173 },
1174 { .pme_uname = "DCT1_DIMM",
1175 .pme_udesc = "DCT1 DIMM (chip select) turnaround",
1176 .pme_ucode = 0x08,
1177 },
1178 { .pme_uname = "DCT1_READ_TO_WRITE_TURNAROUND",
1179 .pme_udesc = "DCT1 Read to write turnaround",
1180 .pme_ucode = 0x10,
1181 },
1182 { .pme_uname = "DCT1_WRITE_TO_READ_TURNAROUND",
1183 .pme_udesc = "DCT1 Write to read turnaround",
1184 .pme_ucode = 0x20,
1185 },
1186 { .pme_uname = "ALL",
1187 .pme_udesc = "All sub-events selected",
1188 .pme_ucode = 0x3F,
1189 },
1190 },
1191 },
1192/* 90 */{.pme_name = "MEMORY_CONTROLLER_BYPASS",
1193 .pme_code = 0xE4,
1194 .pme_desc = "Memory Controller Bypass Counter Saturation",
1195 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1196 .pme_numasks = 5,
1197 .pme_umasks = {
1198 { .pme_uname = "HIGH_PRIORITY",
1199 .pme_udesc = "Memory controller high priority bypass",
1200 .pme_ucode = 0x01,
1201 },
1202 { .pme_uname = "LOW_PRIORITY",
1203 .pme_udesc = "Memory controller medium priority bypass",
1204 .pme_ucode = 0x02,
1205 },
1206 { .pme_uname = "DRAM_INTERFACE",
1207 .pme_udesc = "DCT0 DCQ bypass",
1208 .pme_ucode = 0x04,
1209 },
1210 { .pme_uname = "DRAM_QUEUE",
1211 .pme_udesc = "DCT1 DCQ bypass",
1212 .pme_ucode = 0x08,
1213 },
1214 { .pme_uname = "ALL",
1215 .pme_udesc = "All sub-events selected",
1216 .pme_ucode = 0x0F,
1217 },
1218 },
1219 },
1220/* 91 */{.pme_name = "THERMAL_STATUS_AND_ECC_ERRORS",
1221 .pme_code = 0xE8,
1222 .pme_desc = "Thermal Status",
1223 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1224 .pme_numasks = 6,
1225 .pme_umasks = {
1226 { .pme_uname = "CLKS_DIE_TEMP_TOO_HIGH",
1227 .pme_udesc = "Number of times the HTC trip point is crossed",
1228 .pme_ucode = 0x04,
1229 },
1230 { .pme_uname = "CLKS_TEMP_THRESHOLD_EXCEEDED",
1231 .pme_udesc = "Number of clocks when STC trip point active",
1232 .pme_ucode = 0x08,
1233 },
1234 { .pme_uname = "STC_TRIP_POINTS_CROSSED",
1235 .pme_udesc = "Number of times the STC trip point is crossed",
1236 .pme_ucode = 0x10,
1237 },
1238 { .pme_uname = "CLOCKS_HTC_P_STATE_INACTIVE",
1239 .pme_udesc = "Number of clocks HTC P-state is inactive.",
1240 .pme_ucode = 0x20,
1241 },
1242 { .pme_uname = "CLOCKS_HTC_P_STATE_ACTIVE",
1243 .pme_udesc = "Number of clocks HTC P-state is active",
1244 .pme_ucode = 0x40,
1245 },
1246 { .pme_uname = "ALL",
1247 .pme_udesc = "All sub-events selected",
1248 .pme_ucode = 0x7C,
1249 },
1250 },
1251 },
1252/* 92 */{.pme_name = "CPU_IO_REQUESTS_TO_MEMORY_IO",
1253 .pme_code = 0xE9,
1254 .pme_desc = "CPU/IO Requests to Memory/IO",
1255 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1256 .pme_numasks = 9,
1257 .pme_umasks = {
1258 { .pme_uname = "I_O_TO_I_O",
1259 .pme_udesc = "IO to IO",
1260 .pme_ucode = 0x01,
1261 },
1262 { .pme_uname = "I_O_TO_MEM",
1263 .pme_udesc = "IO to Mem",
1264 .pme_ucode = 0x02,
1265 },
1266 { .pme_uname = "CPU_TO_I_O",
1267 .pme_udesc = "CPU to IO",
1268 .pme_ucode = 0x04,
1269 },
1270 { .pme_uname = "CPU_TO_MEM",
1271 .pme_udesc = "CPU to Mem",
1272 .pme_ucode = 0x08,
1273 },
1274 { .pme_uname = "TO_REMOTE_NODE",
1275 .pme_udesc = "To remote node",
1276 .pme_ucode = 0x10,
1277 },
1278 { .pme_uname = "TO_LOCAL_NODE",
1279 .pme_udesc = "To local node",
1280 .pme_ucode = 0x20,
1281 },
1282 { .pme_uname = "FROM_REMOTE_NODE",
1283 .pme_udesc = "From remote node",
1284 .pme_ucode = 0x40,
1285 },
1286 { .pme_uname = "FROM_LOCAL_NODE",
1287 .pme_udesc = "From local node",
1288 .pme_ucode = 0x80,
1289 },
1290 { .pme_uname = "ALL",
1291 .pme_udesc = "All sub-events selected",
1292 .pme_ucode = 0xFF,
1293 },
1294 },
1295 },
1296/* 93 */{.pme_name = "CACHE_BLOCK",
1297 .pme_code = 0xEA,
1298 .pme_desc = "Cache Block Commands",
1299 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1300 .pme_numasks = 6,
1301 .pme_umasks = {
1302 { .pme_uname = "VICTIM_WRITEBACK",
1303 .pme_udesc = "Victim Block (Writeback)",
1304 .pme_ucode = 0x01,
1305 },
1306 { .pme_uname = "DCACHE_LOAD_MISS",
1307 .pme_udesc = "Read Block (Dcache load miss refill)",
1308 .pme_ucode = 0x04,
1309 },
1310 { .pme_uname = "SHARED_ICACHE_REFILL",
1311 .pme_udesc = "Read Block Shared (Icache refill)",
1312 .pme_ucode = 0x08,
1313 },
1314 { .pme_uname = "READ_BLOCK_MODIFIED",
1315 .pme_udesc = "Read Block Modified (Dcache store miss refill)",
1316 .pme_ucode = 0x10,
1317 },
1318 { .pme_uname = "READ_TO_DIRTY",
1319 .pme_udesc = "Change-to-Dirty (first store to clean block already in cache)",
1320 .pme_ucode = 0x20,
1321 },
1322 { .pme_uname = "ALL",
1323 .pme_udesc = "All sub-events selected",
1324 .pme_ucode = 0x3D,
1325 },
1326 },
1327 },
1328/* 94 */{.pme_name = "SIZED_COMMANDS",
1329 .pme_code = 0xEB,
1330 .pme_desc = "Sized Commands",
1331 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1332 .pme_numasks = 7,
1333 .pme_umasks = {
1334 { .pme_uname = "NON_POSTED_WRITE_BYTE",
1335 .pme_udesc = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes",
1336 .pme_ucode = 0x01,
1337 },
1338 { .pme_uname = "NON_POSTED_WRITE_DWORD",
1339 .pme_udesc = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD",
1340 .pme_ucode = 0x02,
1341 },
1342 { .pme_uname = "POSTED_WRITE_BYTE",
1343 .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer",
1344 .pme_ucode = 0x04,
1345 },
1346 { .pme_uname = "POSTED_WRITE_DWORD",
1347 .pme_udesc = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes",
1348 .pme_ucode = 0x08,
1349 },
1350 { .pme_uname = "READ_BYTE_4_BYTES",
1351 .pme_udesc = "SzRd Byte (4 bytes) Legacy or mapped IO",
1352 .pme_ucode = 0x10,
1353 },
1354 { .pme_uname = "READ_DWORD_1_16_DWORDS",
1355 .pme_udesc = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size",
1356 .pme_ucode = 0x20,
1357 },
1358 { .pme_uname = "ALL",
1359 .pme_udesc = "All sub-events selected",
1360 .pme_ucode = 0x3F,
1361 },
1362 },
1363 },
1364/* 95 */{.pme_name = "PROBE",
1365 .pme_code = 0xEC,
1366 .pme_desc = "Probe Responses and Upstream Requests",
1367 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1368 .pme_numasks = 9,
1369 .pme_umasks = {
1370 { .pme_uname = "MISS",
1371 .pme_udesc = "Probe miss",
1372 .pme_ucode = 0x01,
1373 },
1374 { .pme_uname = "HIT_CLEAN",
1375 .pme_udesc = "Probe hit clean",
1376 .pme_ucode = 0x02,
1377 },
1378 { .pme_uname = "HIT_DIRTY_NO_MEMORY_CANCEL",
1379 .pme_udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
1380 .pme_ucode = 0x04,
1381 },
1382 { .pme_uname = "HIT_DIRTY_WITH_MEMORY_CANCEL",
1383 .pme_udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
1384 .pme_ucode = 0x08,
1385 },
1386 { .pme_uname = "UPSTREAM_DISPLAY_REFRESH_READS",
1387 .pme_udesc = "Upstream display refresh/ISOC reads",
1388 .pme_ucode = 0x10,
1389 },
1390 { .pme_uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS",
1391 .pme_udesc = "Upstream non-display refresh reads",
1392 .pme_ucode = 0x20,
1393 },
1394 { .pme_uname = "UPSTREAM_WRITES",
1395 .pme_udesc = "Upstream ISOC writes",
1396 .pme_ucode = 0x40,
1397 },
1398 { .pme_uname = "UPSTREAM_NON_ISOC_WRITES",
1399 .pme_udesc = "Upstream non-ISOC writes",
1400 .pme_ucode = 0x80,
1401 },
1402 { .pme_uname = "ALL",
1403 .pme_udesc = "All sub-events selected",
1404 .pme_ucode = 0xFF,
1405 },
1406 },
1407 },
1408/* 96 */{.pme_name = "GART",
1409 .pme_code = 0xEE,
1410 .pme_desc = "GART Events",
1411 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1412 .pme_numasks = 9,
1413 .pme_umasks = {
1414 { .pme_uname = "APERTURE_HIT_FROM_CPU",
1415 .pme_udesc = "GART aperture hit on access from CPU",
1416 .pme_ucode = 0x01,
1417 },
1418 { .pme_uname = "APERTURE_HIT_FROM_IO",
1419 .pme_udesc = "GART aperture hit on access from IO",
1420 .pme_ucode = 0x02,
1421 },
1422 { .pme_uname = "MISS",
1423 .pme_udesc = "GART miss",
1424 .pme_ucode = 0x04,
1425 },
1426 { .pme_uname = "REQUEST_HIT_TABLE_WALK",
1427 .pme_udesc = "GART/DEV Request hit table walk in progress",
1428 .pme_ucode = 0x08,
1429 },
1430 { .pme_uname = "DEV_HIT",
1431 .pme_udesc = "DEV hit",
1432 .pme_ucode = 0x10,
1433 },
1434 { .pme_uname = "DEV_MISS",
1435 .pme_udesc = "DEV miss",
1436 .pme_ucode = 0x20,
1437 },
1438 { .pme_uname = "DEV_ERROR",
1439 .pme_udesc = "DEV error",
1440 .pme_ucode = 0x40,
1441 },
1442 { .pme_uname = "MULTIPLE_TABLE_WALK",
1443 .pme_udesc = "GART/DEV multiple table walk in progress",
1444 .pme_ucode = 0x80,
1445 },
1446 { .pme_uname = "ALL",
1447 .pme_udesc = "All sub-events selected",
1448 .pme_ucode = 0xFF,
1449 },
1450 },
1451 },
1452/* 97 */{.pme_name = "MEMORY_CONTROLLER_REQUESTS",
1453 .pme_code = 0x1F0,
1454 .pme_desc = "Memory Controller Requests",
1455 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1456 .pme_numasks = 9,
1457 .pme_umasks = {
1458 { .pme_uname = "WRITE_REQUESTS",
1459 .pme_udesc = "Write requests sent to the DCT",
1460 .pme_ucode = 0x01,
1461 },
1462 { .pme_uname = "READ_REQUESTS",
1463 .pme_udesc = "Read requests (including prefetch requests) sent to the DCT",
1464 .pme_ucode = 0x02,
1465 },
1466 { .pme_uname = "PREFETCH_REQUESTS",
1467 .pme_udesc = "Prefetch requests sent to the DCT",
1468 .pme_ucode = 0x04,
1469 },
1470 { .pme_uname = "32_BYTES_WRITES",
1471 .pme_udesc = "32 Bytes Sized Writes",
1472 .pme_ucode = 0x08,
1473 },
1474 { .pme_uname = "64_BYTES_WRITES",
1475 .pme_udesc = "64 Bytes Sized Writes",
1476 .pme_ucode = 0x10,
1477 },
1478 { .pme_uname = "32_BYTES_READS",
1479 .pme_udesc = "32 Bytes Sized Reads",
1480 .pme_ucode = 0x20,
1481 },
1482 { .pme_uname = "64_BYTES_READS",
1483 .pme_udesc = "64 Byte Sized Reads",
1484 .pme_ucode = 0x40,
1485 },
1486 { .pme_uname = "READ_REQUESTS_WHILE_WRITES_REQUESTS",
1487 .pme_udesc = "Read requests sent to the DCT while writes requests are pending in the DCT",
1488 .pme_ucode = 0x80,
1489 },
1490 { .pme_uname = "ALL",
1491 .pme_udesc = "All sub-events selected",
1492 .pme_ucode = 0xFF,
1493 },
1494 },
1495 },
1496/* 98 */{.pme_name = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE",
1497 .pme_code = 0x1E0,
1498 .pme_desc = "CPU to DRAM Requests to Target Node",
1499 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1500 .pme_numasks = 9,
1501 .pme_umasks = {
1502 { .pme_uname = "LOCAL_TO_0",
1503 .pme_udesc = "From Local node to Node 0",
1504 .pme_ucode = 0x01,
1505 },
1506 { .pme_uname = "LOCAL_TO_1",
1507 .pme_udesc = "From Local node to Node 1",
1508 .pme_ucode = 0x02,
1509 },
1510 { .pme_uname = "LOCAL_TO_2",
1511 .pme_udesc = "From Local node to Node 2",
1512 .pme_ucode = 0x04,
1513 },
1514 { .pme_uname = "LOCAL_TO_3",
1515 .pme_udesc = "From Local node to Node 3",
1516 .pme_ucode = 0x08,
1517 },
1518 { .pme_uname = "LOCAL_TO_4",
1519 .pme_udesc = "From Local node to Node 4",
1520 .pme_ucode = 0x10,
1521 },
1522 { .pme_uname = "LOCAL_TO_5",
1523 .pme_udesc = "From Local node to Node 5",
1524 .pme_ucode = 0x20,
1525 },
1526 { .pme_uname = "LOCAL_TO_6",
1527 .pme_udesc = "From Local node to Node 6",
1528 .pme_ucode = 0x40,
1529 },
1530 { .pme_uname = "LOCAL_TO_7",
1531 .pme_udesc = "From Local node to Node 7",
1532 .pme_ucode = 0x80,
1533 },
1534 { .pme_uname = "ALL",
1535 .pme_udesc = "All sub-events selected",
1536 .pme_ucode = 0xFF,
1537 },
1538 },
1539 },
1540/* 99 */{.pme_name = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE",
1541 .pme_code = 0x1E1,
1542 .pme_desc = "IO to DRAM Requests to Target Node",
1543 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1544 .pme_numasks = 9,
1545 .pme_umasks = {
1546 { .pme_uname = "LOCAL_TO_0",
1547 .pme_udesc = "From Local node to Node 0",
1548 .pme_ucode = 0x01,
1549 },
1550 { .pme_uname = "LOCAL_TO_1",
1551 .pme_udesc = "From Local node to Node 1",
1552 .pme_ucode = 0x02,
1553 },
1554 { .pme_uname = "LOCAL_TO_2",
1555 .pme_udesc = "From Local node to Node 2",
1556 .pme_ucode = 0x04,
1557 },
1558 { .pme_uname = "LOCAL_TO_3",
1559 .pme_udesc = "From Local node to Node 3",
1560 .pme_ucode = 0x08,
1561 },
1562 { .pme_uname = "LOCAL_TO_4",
1563 .pme_udesc = "From Local node to Node 4",
1564 .pme_ucode = 0x10,
1565 },
1566 { .pme_uname = "LOCAL_TO_5",
1567 .pme_udesc = "From Local node to Node 5",
1568 .pme_ucode = 0x20,
1569 },
1570 { .pme_uname = "LOCAL_TO_6",
1571 .pme_udesc = "From Local node to Node 6",
1572 .pme_ucode = 0x40,
1573 },
1574 { .pme_uname = "LOCAL_TO_7",
1575 .pme_udesc = "From Local node to Node 7",
1576 .pme_ucode = 0x80,
1577 },
1578 { .pme_uname = "ALL",
1579 .pme_udesc = "All sub-events selected",
1580 .pme_ucode = 0xFF,
1581 },
1582 },
1583 },
1584/* 100 */{.pme_name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3",
1585 .pme_code = 0x1E2,
1586 .pme_desc = "CPU Read Command Latency to Target Node 0-3",
1587 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1588 .pme_numasks = 9,
1589 .pme_umasks = {
1590 { .pme_uname = "READ_BLOCK",
1591 .pme_udesc = "Read block",
1592 .pme_ucode = 0x01,
1593 },
1594 { .pme_uname = "READ_BLOCK_SHARED",
1595 .pme_udesc = "Read block shared",
1596 .pme_ucode = 0x02,
1597 },
1598 { .pme_uname = "READ_BLOCK_MODIFIED",
1599 .pme_udesc = "Read block modified",
1600 .pme_ucode = 0x04,
1601 },
1602 { .pme_uname = "CHANGE_TO_DIRTY",
1603 .pme_udesc = "Change-to-Dirty",
1604 .pme_ucode = 0x08,
1605 },
1606 { .pme_uname = "LOCAL_TO_0",
1607 .pme_udesc = "From Local node to Node 0",
1608 .pme_ucode = 0x10,
1609 },
1610 { .pme_uname = "LOCAL_TO_1",
1611 .pme_udesc = "From Local node to Node 1",
1612 .pme_ucode = 0x20,
1613 },
1614 { .pme_uname = "LOCAL_TO_2",
1615 .pme_udesc = "From Local node to Node 2",
1616 .pme_ucode = 0x40,
1617 },
1618 { .pme_uname = "LOCAL_TO_3",
1619 .pme_udesc = "From Local node to Node 3",
1620 .pme_ucode = 0x80,
1621 },
1622 { .pme_uname = "ALL",
1623 .pme_udesc = "All sub-events selected",
1624 .pme_ucode = 0xFF,
1625 },
1626 },
1627 },
1628/* 101 */{.pme_name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3",
1629 .pme_code = 0x1E3,
1630 .pme_desc = "CPU Read Command Requests to Target Node 0-3",
1631 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1632 .pme_numasks = 9,
1633 .pme_umasks = {
1634 { .pme_uname = "READ_BLOCK",
1635 .pme_udesc = "Read block",
1636 .pme_ucode = 0x01,
1637 },
1638 { .pme_uname = "READ_BLOCK_SHARED",
1639 .pme_udesc = "Read block shared",
1640 .pme_ucode = 0x02,
1641 },
1642 { .pme_uname = "READ_BLOCK_MODIFIED",
1643 .pme_udesc = "Read block modified",
1644 .pme_ucode = 0x04,
1645 },
1646 { .pme_uname = "CHANGE_TO_DIRTY",
1647 .pme_udesc = "Change-to-Dirty",
1648 .pme_ucode = 0x08,
1649 },
1650 { .pme_uname = "LOCAL_TO_0",
1651 .pme_udesc = "From Local node to Node 0",
1652 .pme_ucode = 0x10,
1653 },
1654 { .pme_uname = "LOCAL_TO_1",
1655 .pme_udesc = "From Local node to Node 1",
1656 .pme_ucode = 0x20,
1657 },
1658 { .pme_uname = "LOCAL_TO_2",
1659 .pme_udesc = "From Local node to Node 2",
1660 .pme_ucode = 0x40,
1661 },
1662 { .pme_uname = "LOCAL_TO_3",
1663 .pme_udesc = "From Local node to Node 3",
1664 .pme_ucode = 0x80,
1665 },
1666 { .pme_uname = "ALL",
1667 .pme_udesc = "All sub-events selected",
1668 .pme_ucode = 0xFF,
1669 },
1670 },
1671 },
1672/* 102 */{.pme_name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7",
1673 .pme_code = 0x1E4,
1674 .pme_desc = "CPU Read Command Latency to Target Node 4-7",
1675 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1676 .pme_numasks = 9,
1677 .pme_umasks = {
1678 { .pme_uname = "READ_BLOCK",
1679 .pme_udesc = "Read block",
1680 .pme_ucode = 0x01,
1681 },
1682 { .pme_uname = "READ_BLOCK_SHARED",
1683 .pme_udesc = "Read block shared",
1684 .pme_ucode = 0x02,
1685 },
1686 { .pme_uname = "READ_BLOCK_MODIFIED",
1687 .pme_udesc = "Read block modified",
1688 .pme_ucode = 0x04,
1689 },
1690 { .pme_uname = "CHANGE_TO_DIRTY",
1691 .pme_udesc = "Change-to-Dirty",
1692 .pme_ucode = 0x08,
1693 },
1694 { .pme_uname = "LOCAL_TO_4",
1695 .pme_udesc = "From Local node to Node 4",
1696 .pme_ucode = 0x10,
1697 },
1698 { .pme_uname = "LOCAL_TO_5",
1699 .pme_udesc = "From Local node to Node 5",
1700 .pme_ucode = 0x20,
1701 },
1702 { .pme_uname = "LOCAL_TO_6",
1703 .pme_udesc = "From Local node to Node 6",
1704 .pme_ucode = 0x40,
1705 },
1706 { .pme_uname = "LOCAL_TO_7",
1707 .pme_udesc = "From Local node to Node 7",
1708 .pme_ucode = 0x80,
1709 },
1710 { .pme_uname = "ALL",
1711 .pme_udesc = "All sub-events selected",
1712 .pme_ucode = 0xFF,
1713 },
1714 },
1715 },
1716/* 103 */{.pme_name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7",
1717 .pme_code = 0x1E5,
1718 .pme_desc = "CPU Read Command Requests to Target Node 4-7",
1719 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1720 .pme_numasks = 9,
1721 .pme_umasks = {
1722 { .pme_uname = "READ_BLOCK",
1723 .pme_udesc = "Read block",
1724 .pme_ucode = 0x01,
1725 },
1726 { .pme_uname = "READ_BLOCK_SHARED",
1727 .pme_udesc = "Read block shared",
1728 .pme_ucode = 0x02,
1729 },
1730 { .pme_uname = "READ_BLOCK_MODIFIED",
1731 .pme_udesc = "Read block modified",
1732 .pme_ucode = 0x04,
1733 },
1734 { .pme_uname = "CHANGE_TO_DIRTY",
1735 .pme_udesc = "Change-to-Dirty",
1736 .pme_ucode = 0x08,
1737 },
1738 { .pme_uname = "LOCAL_TO_4",
1739 .pme_udesc = "From Local node to Node 4",
1740 .pme_ucode = 0x10,
1741 },
1742 { .pme_uname = "LOCAL_TO_5",
1743 .pme_udesc = "From Local node to Node 5",
1744 .pme_ucode = 0x20,
1745 },
1746 { .pme_uname = "LOCAL_TO_6",
1747 .pme_udesc = "From Local node to Node 6",
1748 .pme_ucode = 0x40,
1749 },
1750 { .pme_uname = "LOCAL_TO_7",
1751 .pme_udesc = "From Local node to Node 7",
1752 .pme_ucode = 0x80,
1753 },
1754 { .pme_uname = "ALL",
1755 .pme_udesc = "All sub-events selected",
1756 .pme_ucode = 0xFF,
1757 },
1758 },
1759 },
1760/* 104 */{.pme_name = "CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7",
1761 .pme_code = 0x1E6,
1762 .pme_desc = "CPU Command Latency to Target Node 0-3/4-7",
1763 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1764 .pme_numasks = 9,
1765 .pme_umasks = {
1766 { .pme_uname = "READ_SIZED",
1767 .pme_udesc = "Read Sized",
1768 .pme_ucode = 0x01,
1769 },
1770 { .pme_uname = "WRITE_SIZED",
1771 .pme_udesc = "Write Sized",
1772 .pme_ucode = 0x02,
1773 },
1774 { .pme_uname = "VICTIM_BLOCK",
1775 .pme_udesc = "Victim Block",
1776 .pme_ucode = 0x04,
1777 },
1778 { .pme_uname = "NODE_GROUP_SELECT",
1779 .pme_udesc = "Node Group Select. 0=Nodes 0-3. 1= Nodes 4-7.",
1780 .pme_ucode = 0x08,
1781 },
1782 { .pme_uname = "LOCAL_TO_0_4",
1783 .pme_udesc = "From Local node to Node 0/4",
1784 .pme_ucode = 0x10,
1785 },
1786 { .pme_uname = "LOCAL_TO_1_5",
1787 .pme_udesc = "From Local node to Node 1/5",
1788 .pme_ucode = 0x20,
1789 },
1790 { .pme_uname = "LOCAL_TO_2_6",
1791 .pme_udesc = "From Local node to Node 2/6",
1792 .pme_ucode = 0x40,
1793 },
1794 { .pme_uname = "LOCAL_TO_3_7",
1795 .pme_udesc = "From Local node to Node 3/7",
1796 .pme_ucode = 0x80,
1797 },
1798 { .pme_uname = "ALL",
1799 .pme_udesc = "All sub-events selected",
1800 .pme_ucode = 0xFF,
1801 },
1802 },
1803 },
1804/* 105 */{.pme_name = "CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7",
1805 .pme_code = 0x1E7,
1806 .pme_desc = "CPU Requests to Target Node 0-3/4-7",
1807 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1808 .pme_numasks = 9,
1809 .pme_umasks = {
1810 { .pme_uname = "READ_SIZED",
1811 .pme_udesc = "Read Sized",
1812 .pme_ucode = 0x01,
1813 },
1814 { .pme_uname = "WRITE_SIZED",
1815 .pme_udesc = "Write Sized",
1816 .pme_ucode = 0x02,
1817 },
1818 { .pme_uname = "VICTIM_BLOCK",
1819 .pme_udesc = "Victim Block",
1820 .pme_ucode = 0x04,
1821 },
1822 { .pme_uname = "NODE_GROUP_SELECT",
1823 .pme_udesc = "Node Group Select. 0=Nodes 0-3. 1= Nodes 4-7.",
1824 .pme_ucode = 0x08,
1825 },
1826 { .pme_uname = "LOCAL_TO_0_4",
1827 .pme_udesc = "From Local node to Node 0/4",
1828 .pme_ucode = 0x10,
1829 },
1830 { .pme_uname = "LOCAL_TO_1_5",
1831 .pme_udesc = "From Local node to Node 1/5",
1832 .pme_ucode = 0x20,
1833 },
1834 { .pme_uname = "LOCAL_TO_2_6",
1835 .pme_udesc = "From Local node to Node 2/6",
1836 .pme_ucode = 0x40,
1837 },
1838 { .pme_uname = "LOCAL_TO_3_7",
1839 .pme_udesc = "From Local node to Node 3/7",
1840 .pme_ucode = 0x80,
1841 },
1842 { .pme_uname = "ALL",
1843 .pme_udesc = "All sub-events selected",
1844 .pme_ucode = 0xFF,
1845 },
1846 },
1847 },
1848/* 106 */{.pme_name = "HYPERTRANSPORT_LINK0",
1849 .pme_code = 0xF6,
1850 .pme_desc = "HyperTransport Link 0 Transmit Bandwidth",
1851 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1852 .pme_numasks = 8,
1853 .pme_umasks = {
1854 { .pme_uname = "COMMAND_DWORD_SENT",
1855 .pme_udesc = "Command DWORD sent",
1856 .pme_ucode = 0x01,
1857 },
1858 { .pme_uname = "DATA_DWORD_SENT",
1859 .pme_udesc = "Data DWORD sent",
1860 .pme_ucode = 0x02,
1861 },
1862 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1863 .pme_udesc = "Buffer release DWORD sent",
1864 .pme_ucode = 0x04,
1865 },
1866 { .pme_uname = "NOP_DWORD_SENT",
1867 .pme_udesc = "Nop DW sent (idle)",
1868 .pme_ucode = 0x08,
1869 },
1870 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1871 .pme_udesc = "Address extension DWORD sent",
1872 .pme_ucode = 0x10,
1873 },
1874 { .pme_uname = "PER_PACKET_CRC_SENT",
1875 .pme_udesc = "Per packet CRC sent",
1876 .pme_ucode = 0x20,
1877 },
1878 { .pme_uname = "SUBLINK_MASK",
1879 .pme_udesc = "SubLink Mask",
1880 .pme_ucode = 0x80,
1881 },
1882 { .pme_uname = "ALL",
1883 .pme_udesc = "All sub-events selected",
1884 .pme_ucode = 0xBF,
1885 },
1886 },
1887 },
1888/* 107 */{.pme_name = "HYPERTRANSPORT_LINK1",
1889 .pme_code = 0xF7,
1890 .pme_desc = "HyperTransport Link 1 Transmit Bandwidth",
1891 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1892 .pme_numasks = 8,
1893 .pme_umasks = {
1894 { .pme_uname = "COMMAND_DWORD_SENT",
1895 .pme_udesc = "Command DWORD sent",
1896 .pme_ucode = 0x01,
1897 },
1898 { .pme_uname = "DATA_DWORD_SENT",
1899 .pme_udesc = "Data DWORD sent",
1900 .pme_ucode = 0x02,
1901 },
1902 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1903 .pme_udesc = "Buffer release DWORD sent",
1904 .pme_ucode = 0x04,
1905 },
1906 { .pme_uname = "NOP_DWORD_SENT",
1907 .pme_udesc = "Nop DW sent (idle)",
1908 .pme_ucode = 0x08,
1909 },
1910 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1911 .pme_udesc = "Address extension DWORD sent",
1912 .pme_ucode = 0x10,
1913 },
1914 { .pme_uname = "PER_PACKET_CRC_SENT",
1915 .pme_udesc = "Per packet CRC sent",
1916 .pme_ucode = 0x20,
1917 },
1918 { .pme_uname = "SUBLINK_MASK",
1919 .pme_udesc = "SubLink Mask",
1920 .pme_ucode = 0x80,
1921 },
1922 { .pme_uname = "ALL",
1923 .pme_udesc = "All sub-events selected",
1924 .pme_ucode = 0xBF,
1925 },
1926 },
1927 },
1928/* 108 */{.pme_name = "HYPERTRANSPORT_LINK2",
1929 .pme_code = 0xF8,
1930 .pme_desc = "HyperTransport Link 2 Transmit Bandwidth",
1931 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1932 .pme_numasks = 8,
1933 .pme_umasks = {
1934 { .pme_uname = "COMMAND_DWORD_SENT",
1935 .pme_udesc = "Command DWORD sent",
1936 .pme_ucode = 0x01,
1937 },
1938 { .pme_uname = "DATA_DWORD_SENT",
1939 .pme_udesc = "Data DWORD sent",
1940 .pme_ucode = 0x02,
1941 },
1942 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1943 .pme_udesc = "Buffer release DWORD sent",
1944 .pme_ucode = 0x04,
1945 },
1946 { .pme_uname = "NOP_DWORD_SENT",
1947 .pme_udesc = "Nop DW sent (idle)",
1948 .pme_ucode = 0x08,
1949 },
1950 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1951 .pme_udesc = "Address extension DWORD sent",
1952 .pme_ucode = 0x10,
1953 },
1954 { .pme_uname = "PER_PACKET_CRC_SENT",
1955 .pme_udesc = "Per packet CRC sent",
1956 .pme_ucode = 0x20,
1957 },
1958 { .pme_uname = "SUBLINK_MASK",
1959 .pme_udesc = "SubLink Mask",
1960 .pme_ucode = 0x80,
1961 },
1962 { .pme_uname = "ALL",
1963 .pme_udesc = "All sub-events selected",
1964 .pme_ucode = 0xBF,
1965 },
1966 },
1967 },
1968/* 109 */{.pme_name = "HYPERTRANSPORT_LINK3",
1969 .pme_code = 0x1F9,
1970 .pme_desc = "HyperTransport Link 3 Transmit Bandwidth",
1971 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
1972 .pme_numasks = 8,
1973 .pme_umasks = {
1974 { .pme_uname = "COMMAND_DWORD_SENT",
1975 .pme_udesc = "Command DWORD sent",
1976 .pme_ucode = 0x01,
1977 },
1978 { .pme_uname = "DATA_DWORD_SENT",
1979 .pme_udesc = "Data DWORD sent",
1980 .pme_ucode = 0x02,
1981 },
1982 { .pme_uname = "BUFFER_RELEASE_DWORD_SENT",
1983 .pme_udesc = "Buffer release DWORD sent",
1984 .pme_ucode = 0x04,
1985 },
1986 { .pme_uname = "NOP_DWORD_SENT",
1987 .pme_udesc = "Nop DW sent (idle)",
1988 .pme_ucode = 0x08,
1989 },
1990 { .pme_uname = "ADDRESS_EXT_DWORD_SENT",
1991 .pme_udesc = "Address DWORD sent",
1992 .pme_ucode = 0x10,
1993 },
1994 { .pme_uname = "PER_PACKET_CRC_SENT",
1995 .pme_udesc = "Per packet CRC sent",
1996 .pme_ucode = 0x20,
1997 },
1998 { .pme_uname = "SUBLINK_MASK",
1999 .pme_udesc = "SubLink Mask",
2000 .pme_ucode = 0x80,
2001 },
2002 { .pme_uname = "ALL",
2003 .pme_udesc = "All sub-events selected",
2004 .pme_ucode = 0xBF,
2005 },
2006 },
2007 },
2008/* 110 */{.pme_name = "READ_REQUEST_TO_L3_CACHE",
2009 .pme_code = 0x4E0,
2010 .pme_desc = "Read Request to L3 Cache",
2011 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C,
2012 .pme_numasks = 5,
2013 .pme_umasks = {
2014 { .pme_uname = "READ_BLOCK_EXCLUSIVE",
2015 .pme_udesc = "Read Block Exclusive (Data cache read)",
2016 .pme_ucode = 0x01,
2017 },
2018 { .pme_uname = "READ_BLOCK_SHARED",
2019 .pme_udesc = "Read Block Shared (Instruction cache read)",
2020 .pme_ucode = 0x02,
2021 },
2022 { .pme_uname = "READ_BLOCK_MODIFY",
2023 .pme_udesc = "Read Block Modify",
2024 .pme_ucode = 0x04,
2025 },
2026 { .pme_uname = "ANY_READ",
2027 .pme_udesc = "any read modes (exclusive, shared, modify)",
2028 .pme_ucode = 0x07,
2029 },
2030#if 0
2031/*
2032 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
2033 *
2034 * Issue number 437 on page 131.
2035 *
2036 */
2037 { .pme_uname = "CORE_0_SELECT",
2038 .pme_udesc = "Core 0 Select",
2039 .pme_ucode = 0x10,
2040 },
2041 { .pme_uname = "CORE_1_SELECT",
2042 .pme_udesc = "Core 1 Select",
2043 .pme_ucode = 0x20,
2044 },
2045 { .pme_uname = "CORE_2_SELECT",
2046 .pme_udesc = "Core 2 Select",
2047 .pme_ucode = 0x40,
2048 },
2049 { .pme_uname = "CORE_3_SELECT",
2050 .pme_udesc = "Core 3 Select",
2051 .pme_ucode = 0x80,
2052 },
2053#endif
2054 { .pme_uname = "ALL_CORES",
2055 .pme_udesc = "All cores",
2056 .pme_ucode = 0xF0,
2057 },
2058 },
2059 },
2060/* 111 */{.pme_name = "L3_CACHE_MISSES",
2061 .pme_code = 0x4E1,
2062 .pme_desc = "L3 Cache Misses",
2063 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C,
2064 .pme_numasks = 5,
2065 .pme_umasks = {
2066 { .pme_uname = "READ_BLOCK_EXCLUSIVE",
2067 .pme_udesc = "Read Block Exclusive (Data cache read)",
2068 .pme_ucode = 0x01,
2069 },
2070 { .pme_uname = "READ_BLOCK_SHARED",
2071 .pme_udesc = "Read Block Shared (Instruction cache read)",
2072 .pme_ucode = 0x02,
2073 },
2074 { .pme_uname = "READ_BLOCK_MODIFY",
2075 .pme_udesc = "Read Block Modify",
2076 .pme_ucode = 0x04,
2077 },
2078 { .pme_uname = "ANY_READ",
2079 .pme_udesc = "any read modes (exclusive, shared, modify)",
2080 .pme_ucode = 0x07,
2081 },
2082#if 0
2083/*
2084 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
2085 *
2086 * Issue number 437 on page 131.
2087 *
2088 */
2089 { .pme_uname = "CORE_0_SELECT",
2090 .pme_udesc = "Core 0 Select",
2091 .pme_ucode = 0x10,
2092 },
2093 { .pme_uname = "CORE_1_SELECT",
2094 .pme_udesc = "Core 1 Select",
2095 .pme_ucode = 0x20,
2096 },
2097 { .pme_uname = "CORE_2_SELECT",
2098 .pme_udesc = "Core 2 Select",
2099 .pme_ucode = 0x40,
2100 },
2101 { .pme_uname = "CORE_3_SELECT",
2102 .pme_udesc = "Core 3 Select",
2103 .pme_ucode = 0x80,
2104 },
2105#endif
2106 { .pme_uname = "ALL_CORES",
2107 .pme_udesc = "All cores",
2108 .pme_ucode = 0xF0,
2109 },
2110 },
2111 },
2112/* 112 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
2113 .pme_code = 0x4E2,
2114 .pme_desc = "L3 Fills caused by L2 Evictions",
2115 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C,
2116 .pme_numasks = 6,
2117 .pme_umasks = {
2118 { .pme_uname = "SHARED",
2119 .pme_udesc = "Shared",
2120 .pme_ucode = 0x01,
2121 },
2122 { .pme_uname = "EXCLUSIVE",
2123 .pme_udesc = "Exclusive",
2124 .pme_ucode = 0x02,
2125 },
2126 { .pme_uname = "OWNED",
2127 .pme_udesc = "Owned",
2128 .pme_ucode = 0x04,
2129 },
2130 { .pme_uname = "MODIFIED",
2131 .pme_udesc = "Modified",
2132 .pme_ucode = 0x08,
2133 },
2134 { .pme_uname = "ANY_STATE",
2135 .pme_udesc = "any line state (shared, owned, exclusive, modified)",
2136 .pme_ucode = 0x0F,
2137 },
2138#if 0
2139/*
2140 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
2141 *
2142 * Issue number 437 on page 131.
2143 *
2144 */
2145 { .pme_uname = "CORE_0_SELECT",
2146 .pme_udesc = "Core 0 Select",
2147 .pme_ucode = 0x10,
2148 },
2149 { .pme_uname = "CORE_1_SELECT",
2150 .pme_udesc = "Core 1 Select",
2151 .pme_ucode = 0x20,
2152 },
2153 { .pme_uname = "CORE_2_SELECT",
2154 .pme_udesc = "Core 2 Select",
2155 .pme_ucode = 0x40,
2156 },
2157 { .pme_uname = "CORE_3_SELECT",
2158 .pme_udesc = "Core 3 Select",
2159 .pme_ucode = 0x80,
2160 },
2161#endif
2162 { .pme_uname = "ALL_CORES",
2163 .pme_udesc = "All cores",
2164 .pme_ucode = 0xF0,
2165 },
2166 },
2167 },
2168/* 113 */{.pme_name = "L3_EVICTIONS",
2169 .pme_code = 0x4E3,
2170 .pme_desc = "L3 Evictions",
2171 .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
2172 .pme_numasks = 5,
2173 .pme_umasks = {
2174 { .pme_uname = "SHARED",
2175 .pme_udesc = "Shared",
2176 .pme_ucode = 0x01,
2177 },
2178 { .pme_uname = "EXCLUSIVE",
2179 .pme_udesc = "Exclusive",
2180 .pme_ucode = 0x02,
2181 },
2182 { .pme_uname = "OWNED",
2183 .pme_udesc = "Owned",
2184 .pme_ucode = 0x04,
2185 },
2186 { .pme_uname = "MODIFIED",
2187 .pme_udesc = "Modified",
2188 .pme_ucode = 0x08,
2189 },
2190 { .pme_uname = "ALL",
2191 .pme_udesc = "All sub-events selected",
2192 .pme_ucode = 0x0F,
2193 },
2194 },
2195 },
2196
2197/* Family 10h RevC, Shanghai */
2198
2199/* 114 */{.pme_name = "PAGE_SIZE_MISMATCHES",
2200 .pme_code = 0x165,
2201 .pme_desc = "Page Size Mismatches",
2202 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_C,
2203 .pme_numasks = 4,
2204 .pme_umasks = {
2205 { .pme_uname = "GUEST_LARGER",
2206 .pme_udesc = "Guest page size is larger than the host page size.",
2207 .pme_ucode = 0x01,
2208 },
2209 { .pme_uname = "MTRR_MISMATCH",
2210 .pme_udesc = "MTRR mismatch.",
2211 .pme_ucode = 0x02,
2212 },
2213 { .pme_uname = "HOST_LARGER",
2214 .pme_udesc = "Host page size is larger than the guest page size.",
2215 .pme_ucode = 0x04,
2216 },
2217 { .pme_uname = "ALL",
2218 .pme_udesc = "All sub-events selected",
2219 .pme_ucode = 0x07,
2220 },
2221 },
2222 },
2223/* 115 */{.pme_name = "RETIRED_X87_OPS",
2224 .pme_code = 0x1C0,
2225 .pme_desc = "Retired x87 Floating Point Operations",
2226 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_C,
2227 .pme_numasks = 4,
2228 .pme_umasks = {
2229 { .pme_uname = "ADD_SUB_OPS",
2230 .pme_udesc = "Add/subtract ops",
2231 .pme_ucode = 0x01,
2232 },
2233 { .pme_uname = "MUL_OPS",
2234 .pme_udesc = "Multiply ops",
2235 .pme_ucode = 0x02,
2236 },
2237 { .pme_uname = "DIV_OPS",
2238 .pme_udesc = "Divide ops",
2239 .pme_ucode = 0x04,
2240 },
2241 { .pme_uname = "ALL",
2242 .pme_udesc = "All sub-events selected",
2243 .pme_ucode = 0x07,
2244 },
2245 },
2246 },
2247/* 116 */{.pme_name = "IBS_OPS_TAGGED",
2248 .pme_code = 0x1CF,
2249 .pme_desc = "IBS Ops Tagged",
2250 .pme_flags = PFMLIB_AMD64_FAM10H_REV_C,
2251 },
2252/* 117 */{.pme_name = "LFENCE_INST_RETIRED",
2253 .pme_code = 0x1D3,
2254 .pme_desc = "LFENCE Instructions Retired",
2255 .pme_flags = PFMLIB_AMD64_FAM10H_REV_C,
2256 },
2257/* 118 */{.pme_name = "SFENCE_INST_RETIRED",
2258 .pme_code = 0x1D4,
2259 .pme_desc = "SFENCE Instructions Retired",
2260 .pme_flags = PFMLIB_AMD64_FAM10H_REV_C,
2261 },
2262/* 119 */{.pme_name = "MFENCE_INST_RETIRED",
2263 .pme_code = 0x1D5,
2264 .pme_desc = "MFENCE Instructions Retired",
2265 .pme_flags = PFMLIB_AMD64_FAM10H_REV_C,
2266 },
2267
2268/* Family 10h RevD, Istanbul */
2269
2270/* 120 */{.pme_name = "READ_REQUEST_TO_L3_CACHE",
2271 .pme_code = 0x4E0,
2272 .pme_desc = "Read Request to L3 Cache",
2273 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D,
2274 .pme_numasks = 5,
2275 .pme_umasks = {
2276 { .pme_uname = "READ_BLOCK_EXCLUSIVE",
2277 .pme_udesc = "Read Block Exclusive (Data cache read)",
2278 .pme_ucode = 0x01,
2279 },
2280 { .pme_uname = "READ_BLOCK_SHARED",
2281 .pme_udesc = "Read Block Shared (Instruction cache read)",
2282 .pme_ucode = 0x02,
2283 },
2284 { .pme_uname = "READ_BLOCK_MODIFY",
2285 .pme_udesc = "Read Block Modify",
2286 .pme_ucode = 0x04,
2287 },
2288 { .pme_uname = "ANY_READ",
2289 .pme_udesc = "any read modes (exclusive, shared, modify)",
2290 .pme_ucode = 0x07,
2291 },
2292#if 0
2293/*
2294 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
2295 *
2296 * Issue number 437 on page 131.
2297 *
2298 */
2299
2300 { .pme_uname = "CORE_0_SELECT",
2301 .pme_udesc = "Core 0 Select",
2302 .pme_ucode = 0x00,
2303 },
2304 { .pme_uname = "CORE_1_SELECT",
2305 .pme_udesc = "Core 1 Select",
2306 .pme_ucode = 0x10,
2307 },
2308 { .pme_uname = "CORE_2_SELECT",
2309 .pme_udesc = "Core 2 Select",
2310 .pme_ucode = 0x20,
2311 },
2312 { .pme_uname = "CORE_3_SELECT",
2313 .pme_udesc = "Core 3 Select",
2314 .pme_ucode = 0x30,
2315 },
2316 { .pme_uname = "CORE_4_SELECT",
2317 .pme_udesc = "Core 4 Select",
2318 .pme_ucode = 0x40,
2319 },
2320 { .pme_uname = "CORE_5_SELECT",
2321 .pme_udesc = "Core 5 Select",
2322 .pme_ucode = 0x50,
2323 },
2324 { .pme_uname = "ANY_CORE",
2325 .pme_udesc = "Any core",
2326 .pme_ucode = 0xF0,
2327 },
2328#endif
2329 { .pme_uname = "ALL_CORES",
2330 .pme_udesc = "All cores",
2331 .pme_ucode = 0xF0,
2332 },
2333 },
2334 },
2335/* 121 */{.pme_name = "L3_CACHE_MISSES",
2336 .pme_code = 0x4E1,
2337 .pme_desc = "L3 Cache Misses",
2338 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D,
2339 .pme_numasks = 5,
2340 .pme_umasks = {
2341 { .pme_uname = "READ_BLOCK_EXCLUSIVE",
2342 .pme_udesc = "Read Block Exclusive (Data cache read)",
2343 .pme_ucode = 0x01,
2344 },
2345 { .pme_uname = "READ_BLOCK_SHARED",
2346 .pme_udesc = "Read Block Shared (Instruction cache read)",
2347 .pme_ucode = 0x02,
2348 },
2349 { .pme_uname = "READ_BLOCK_MODIFY",
2350 .pme_udesc = "Read Block Modify",
2351 .pme_ucode = 0x04,
2352 },
2353 { .pme_uname = "ANY_READ",
2354 .pme_udesc = "any read modes (exclusive, shared, modify)",
2355 .pme_ucode = 0x07,
2356 },
2357#if 0
2358/*
2359 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
2360 *
2361 * Issue number 437 on page 131.
2362 *
2363 */
2364
2365 { .pme_uname = "CORE_0_SELECT",
2366 .pme_udesc = "Core 0 Select",
2367 .pme_ucode = 0x00,
2368 },
2369 { .pme_uname = "CORE_1_SELECT",
2370 .pme_udesc = "Core 1 Select",
2371 .pme_ucode = 0x10,
2372 },
2373 { .pme_uname = "CORE_2_SELECT",
2374 .pme_udesc = "Core 2 Select",
2375 .pme_ucode = 0x20,
2376 },
2377 { .pme_uname = "CORE_3_SELECT",
2378 .pme_udesc = "Core 3 Select",
2379 .pme_ucode = 0x30,
2380 },
2381 { .pme_uname = "CORE_4_SELECT",
2382 .pme_udesc = "Core 4 Select",
2383 .pme_ucode = 0x40,
2384 },
2385 { .pme_uname = "CORE_5_SELECT",
2386 .pme_udesc = "Core 5 Select",
2387 .pme_ucode = 0x50,
2388 },
2389 { .pme_uname = "ANY_CORE",
2390 .pme_udesc = "Any core",
2391 .pme_ucode = 0xF0,
2392 },
2393#endif
2394 { .pme_uname = "ALL_CORES",
2395 .pme_udesc = "All cores",
2396 .pme_ucode = 0xF0,
2397 },
2398 },
2399 },
2400/* 122 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
2401 .pme_code = 0x4E2,
2402 .pme_desc = "L3 Fills caused by L2 Evictions",
2403 .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D,
2404 .pme_numasks = 6,
2405 .pme_umasks = {
2406 { .pme_uname = "SHARED",
2407 .pme_udesc = "Shared",
2408 .pme_ucode = 0x01,
2409 },
2410 { .pme_uname = "EXCLUSIVE",
2411 .pme_udesc = "Exclusive",
2412 .pme_ucode = 0x02,
2413 },
2414 { .pme_uname = "OWNED",
2415 .pme_udesc = "Owned",
2416 .pme_ucode = 0x04,
2417 },
2418 { .pme_uname = "MODIFIED",
2419 .pme_udesc = "Modified",
2420 .pme_ucode = 0x08,
2421 },
2422 { .pme_uname = "ANY_STATE",
2423 .pme_udesc = "any line state (shared, owned, exclusive, modified)",
2424 .pme_ucode = 0x0F,
2425 },
2426#if 0
2427/*
2428 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
2429 *
2430 * Issue number 437 on page 131.
2431 *
2432 */
2433
2434 { .pme_uname = "CORE_0_SELECT",
2435 .pme_udesc = "Core 0 Select",
2436 .pme_ucode = 0x00,
2437 },
2438 { .pme_uname = "CORE_1_SELECT",
2439 .pme_udesc = "Core 1 Select",
2440 .pme_ucode = 0x10,
2441 },
2442 { .pme_uname = "CORE_2_SELECT",
2443 .pme_udesc = "Core 2 Select",
2444 .pme_ucode = 0x20,
2445 },
2446 { .pme_uname = "CORE_3_SELECT",
2447 .pme_udesc = "Core 3 Select",
2448 .pme_ucode = 0x30,
2449 },
2450 { .pme_uname = "CORE_4_SELECT",
2451 .pme_udesc = "Core 4 Select",
2452 .pme_ucode = 0x40,
2453 },
2454 { .pme_uname = "CORE_5_SELECT",
2455 .pme_udesc = "Core 5 Select",
2456 .pme_ucode = 0x50,
2457 },
2458 { .pme_uname = "ANY_CORE",
2459 .pme_udesc = "Any core",
2460 .pme_ucode = 0xF0,
2461 },
2462#endif
2463 { .pme_uname = "ALL_CORES",
2464 .pme_udesc = "All cores",
2465 .pme_ucode = 0xF0,
2466 },
2467 },
2468 },
2469/* 123 */{.pme_name = "IBSOP_EVENT",
2470 .pme_code = 0xFF,
2471 .pme_desc = "Enable IBS OP mode (pseudo event)",
2472 .pme_flags = 0,
2473 .pme_numasks = 2,
2474 .pme_umasks = {
2475 { .pme_uname = "CYCLES",
2476 .pme_udesc = "sample cycles",
2477 .pme_ucode = 0x01,
2478 },
2479 { .pme_uname = "UOPS",
2480 .pme_udesc = "sample dispatched uops (Rev C and later)",
2481 .pme_ucode = 0x02,
2482 },
2483 },
2484 },
2485/* 124 */{.pme_name = "IBSFETCH_EVENT",
2486 .pme_code = 0xFF,
2487 .pme_desc = "Enable IBS Fetch mode (pseudo event)",
2488 .pme_flags = 0,
2489 .pme_numasks = 2,
2490 .pme_umasks = {
2491 { .pme_uname = "RANDOM",
2492 .pme_udesc = "randomize period",
2493 .pme_ucode = 0x01,
2494 },
2495 { .pme_uname = "NO_RANDOM",
2496 .pme_udesc = "do not randomize period",
2497 .pme_ucode = 0x00,
2498 },
2499 },
2500 },
2501/* 125 */{.pme_name = "MAB_REQUESTS",
2502 .pme_code = 0x68,
2503 .pme_desc = "Average L1 refill latency for Icache and Dcache misses (request count for cache refills)",
2504 .pme_numasks = 10,
2505 .pme_umasks = {
2506 { .pme_uname = "BUFFER_0",
2507 .pme_udesc = "Buffer 0",
2508 .pme_ucode = 0x00,
2509 },
2510 { .pme_uname = "BUFFER_1",
2511 .pme_udesc = "Buffer 1",
2512 .pme_ucode = 0x01,
2513 },
2514 { .pme_uname = "BUFFER_2",
2515 .pme_udesc = "Buffer 2",
2516 .pme_ucode = 0x02,
2517 },
2518 { .pme_uname = "BUFFER_3",
2519 .pme_udesc = "Buffer 3",
2520 .pme_ucode = 0x03,
2521 },
2522 { .pme_uname = "BUFFER_4",
2523 .pme_udesc = "Buffer 4",
2524 .pme_ucode = 0x04,
2525 },
2526 { .pme_uname = "BUFFER_5",
2527 .pme_udesc = "Buffer 5",
2528 .pme_ucode = 0x05,
2529 },
2530 { .pme_uname = "BUFFER_6",
2531 .pme_udesc = "Buffer 6",
2532 .pme_ucode = 0x06,
2533 },
2534 { .pme_uname = "BUFFER_7",
2535 .pme_udesc = "Buffer 7",
2536 .pme_ucode = 0x07,
2537 },
2538 { .pme_uname = "BUFFER_8",
2539 .pme_udesc = "Buffer 8",
2540 .pme_ucode = 0x08,
2541 },
2542 { .pme_uname = "BUFFER_9",
2543 .pme_udesc = "Buffer 9",
2544 .pme_ucode = 0x09,
2545 },
2546 },
2547 },
2548/* 126 */{.pme_name = "MAB_WAIT_CYCLES",
2549 .pme_code = 0x69,
2550 .pme_desc = "Average L1 refill latency for Icache and Dcache misses (cycles that requests spent waiting for the refills)",
2551 .pme_numasks = 10,
2552 .pme_umasks = {
2553 { .pme_uname = "BUFFER_0",
2554 .pme_udesc = "Buffer 0",
2555 .pme_ucode = 0x00,
2556 },
2557 { .pme_uname = "BUFFER_1",
2558 .pme_udesc = "Buffer 1",
2559 .pme_ucode = 0x01,
2560 },
2561 { .pme_uname = "BUFFER_2",
2562 .pme_udesc = "Buffer 2",
2563 .pme_ucode = 0x02,
2564 },
2565 { .pme_uname = "BUFFER_3",
2566 .pme_udesc = "Buffer 3",
2567 .pme_ucode = 0x03,
2568 },
2569 { .pme_uname = "BUFFER_4",
2570 .pme_udesc = "Buffer 4",
2571 .pme_ucode = 0x04,
2572 },
2573 { .pme_uname = "BUFFER_5",
2574 .pme_udesc = "Buffer 5",
2575 .pme_ucode = 0x05,
2576 },
2577 { .pme_uname = "BUFFER_6",
2578 .pme_udesc = "Buffer 6",
2579 .pme_ucode = 0x06,
2580 },
2581 { .pme_uname = "BUFFER_7",
2582 .pme_udesc = "Buffer 7",
2583 .pme_ucode = 0x07,
2584 },
2585 { .pme_uname = "BUFFER_8",
2586 .pme_udesc = "Buffer 8",
2587 .pme_ucode = 0x08,
2588 },
2589 { .pme_uname = "BUFFER_9",
2590 .pme_udesc = "Buffer 9",
2591 .pme_ucode = 0x09,
2592 },
2593 },
2594 },
2595/* 127 */{.pme_name = "NON_CANCELLED_L3_READ_REQUESTS",
2596 .pme_code = 0x4ED,
2597 .pme_desc = "Non-cancelled L3 Read Requests",
2598 .pme_numasks = 5,
2599 .pme_umasks = {
2600 { .pme_uname = "READ_BLOCK_EXCLUSIVE",
2601 .pme_udesc = "Read Block Exclusive (Data cache read)",
2602 .pme_ucode = 0x01,
2603 },
2604 { .pme_uname = "READ_BLOCK_SHARED",
2605 .pme_udesc = "Read Block Shared (Instruction cache read)",
2606 .pme_ucode = 0x02,
2607 },
2608 { .pme_uname = "READ_BLOCK_MODIFY",
2609 .pme_udesc = "Read Block Modify",
2610 .pme_ucode = 0x04,
2611 },
2612 { .pme_uname = "ANY_READ",
2613 .pme_udesc = "any read modes (exclusive, shared, modify)",
2614 .pme_ucode = 0x07,
2615 },
2616#if 0
2617/*
2618 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
2619 *
2620 * Issue number 437 on page 131.
2621 *
2622 */
2623 { .pme_uname = "CORE_0_SELECT",
2624 .pme_udesc = "Core 0 Select",
2625 .pme_ucode = 0x00,
2626 },
2627 { .pme_uname = "CORE_1_SELECT",
2628 .pme_udesc = "Core 1 Select",
2629 .pme_ucode = 0x10,
2630 },
2631 { .pme_uname = "CORE_2_SELECT",
2632 .pme_udesc = "Core 2 Select",
2633 .pme_ucode = 0x20,
2634 },
2635 { .pme_uname = "CORE_3_SELECT",
2636 .pme_udesc = "Core 3 Select",
2637 .pme_ucode = 0x30,
2638 },
2639 { .pme_uname = "CORE_4_SELECT",
2640 .pme_udesc = "Core 4 Select",
2641 .pme_ucode = 0x40,
2642 },
2643 { .pme_uname = "CORE_5_SELECT",
2644 .pme_udesc = "Core 5 Select",
2645 .pme_ucode = 0x50,
2646 },
2647#endif
2648 { .pme_uname = "ALL_CORES",
2649 .pme_udesc = "All cores",
2650 .pme_ucode = 0xF0,
2651 },
2652 },
2653 },
2654};
2655
2656#define PME_AMD64_FAM10H_EVENT_COUNT (sizeof(amd64_fam10h_pe)/sizeof(pme_amd64_entry_t))
2657#define PME_AMD64_FAM10H_CPU_CLK_UNHALTED 36
2658#define PME_AMD64_FAM10H_RETIRED_INSTRUCTIONS 54
2659#define PME_AMD64_IBSOP 123
2660#define PME_AMD64_IBSFETCH 124
amd64_fam10h_pe
static pme_amd64_entry_t amd64_fam10h_pe[]
Definition: amd64_events_fam10h.h:45
PFMLIB_AMD64_TILL_FAM10H_REV_C
#define PFMLIB_AMD64_TILL_FAM10H_REV_C
Definition: pfmlib_amd64_priv.h:124
PFMLIB_AMD64_UMASK_COMBO
#define PFMLIB_AMD64_UMASK_COMBO
Definition: pfmlib_amd64_priv.h:113
PFMLIB_AMD64_FAM10H_REV_D
#define PFMLIB_AMD64_FAM10H_REV_D
Definition: pfmlib_amd64_priv.h:125
PFMLIB_AMD64_TILL_FAM10H_REV_B
#define PFMLIB_AMD64_TILL_FAM10H_REV_B
Definition: pfmlib_amd64_priv.h:122
PFMLIB_AMD64_FAM10H_REV_C
#define PFMLIB_AMD64_FAM10H_REV_C
Definition: pfmlib_amd64_priv.h:123
pme_amd64_entry_t
Definition: pfmlib_amd64_priv.h:59
pme_amd64_entry_t::pme_name
char * pme_name
Definition: pfmlib_amd64_priv.h:60