2023 Workshop: HPC on Heterogeneous Hardware (H3)

The HPC on Heterogeneous Hardware (H3) Workshop is intended as a hybrid event in Hamburg, Germany. It does so by providing a platform for pioneering work on algorithmic research, software library design, programming models, and workflow development for increasingly heterogeneous hardware. In the workshop context, such hardware spans from ARM processors featuring long-vector extensions through GPU-accelerated systems to architectures deploying special function units, FPGAs, or deep learning processors. The workshop will compose of a well-balanced mix of invited talks, peer-reviewed conference contributions, and a panel bringing together worldwide experts in heterogeneous computing.

Introduction

The DOE Report on Productive Computational Science in the Era of Extreme Heterogeneity identified 8 areas that would affected by the inevitable arrival and eminence of heterogeneity: programming environments, O/S, SysOps, productivity metrics/tools, software methodology, I/O, workflows, and modeling. These themes rang particularly true at our own Heterogeneity Panel featured recently at SC21 with hybrid online/virtual attendance of about 180 participants.

Very few companies, now including only Intel, Samsung, and TSMC, manage to mass produce CMOS device at the single-nm scale: a somewhat whimsically called Angstrom era of lithography entering more convenient unit of measurement Angstrom for atomic-scale transistor features. With Dennard Scaling long gone and Moore's Law at cross-roads, heterogeneity became the prevailing paradigm to maximally exploit the efficiency of the on-chip transistors at the 10s of Angstroms scale in what now may be considered new era of chip design.

Scope

Perhaps the most challenging aspect is to limit the workshop's scope to the very few thematic areas that currently dominate the efforts of the community. This year, these include the following topics of interest:

Topics of Interest

A more specific list of topics of interest to focus the submissions and draw specific speakers and invite broad participation of attendees will be the following:

  1. Heterogeneous algorithms that scale not just in terms of the system size but across diverse hardware kinds.
  2. Heterogeneity in data approaches that incorporate mixed-precision storage and compute include data compression as well as hierarchical and randomized projections.
  3. Software systems and libraries that support heterogeneous compute hardware and networking.
  4. Programming models and tools that incorporate heterogeneity of both on-node compute and cross-node networking.

Important Dates

Steering Committee

Program Committee

Format of the Workshop

H3 Workshop is initially meant as a half-day workshop to enable a selection of a good set of contributed manuscripts and talks. We would also like to ensure a programmatically balanced program and maintain a reasonable burden on the reviewers in order to provide sufficient quality of the paper reviews and informative feedback for the authors. The workshop will be held as a in-person event.

A sample schedule of the afternoon workshop to accommodate in-person attendees in Hamburg, Germany, and potential online attendees across multiple time zones will follow this general outline:

Paper Submission and Publication

Papers should be submitted to the workshop with EasyChair. All papers must be original and not simultaneously submitted to another journal or conference. They will be reviewed and should include abstract, keywords, the e-mail address of the corresponding author, and must not exceed 12 pages, including text, tables, figures, and references at a main font size no smaller than in LNCS style. Submission of a paper should be regarded as a commitment that, should the paper be accepted, at least one of the authors will register and attend the workshop to present the work.

Accepted papers will be published in a Springer LNCS volume (SCOPUS indexed). The format must be according to the Springer LNCS Style. Initial submissions are in PDF but the authors of accepted papers will be requested to provide source files. Extra page allotment will be provided to accommodate reviewers comments.

Questions

Any inquires should be directed to organizers.

Abstracts

Mixed-precision computing leveraging Tensor Cores on GPUs can exceed numerical and performance characteristics of IEEE754 single precision for scientific computing by Harun Bayraktar
Recent increases in computational throughput of GPUs have come from reduced and mixed-precision matrix multiplication units known as Tensor Cores primarily targeting applications in artificial intelligence. This has motivated the development of mixed-precision algorithms that leverage these capabilities while preserving a level of accuracy required by applications in science and engineering. The HPL-MxP TOP500 benchmark based on the iterative refinement method is a notable example of this. These methods, while often useful, are not universally applicable due to their numerical sensitivity and inability to guarantee convergence. The goal of this work is to address such shortcomings by developing a "drop-in" replacement for single-precision matrix multiplications and tensor contractions that leverage Tensor Cores to meet or exceed the numerical accuracy of IEEE754 based implementations while delivering significant performance benefits. In addition to explaining the mixed-precision techniques used, we demonstrate numerical accuracy claims through error analysis and two scientific applications: weather forecast and quantum computing simulations.