Co-Scheduling HPC Workloads on Cache-Partitioned CMP Platforms

TitleCo-Scheduling HPC Workloads on Cache-Partitioned CMP Platforms
Publication TypeJournal Article
Year of Publication2019
AuthorsAupy, G., A. Benoit, B. Goglin, L. Pottier, and Y. Robert
JournalInternational Journal of High Performance Computing Applications
Date Published2019-11
Keywordscache partitioning, chip multiprocessor, co-scheduling, HPC application

With the recent advent of many-core architectures such as chip multiprocessors (CMPs), the number of processing units accessing a global shared memory is constantly increasing. Co-scheduling techniques are used to improve application throughput on such architectures, but sharing resources often generates critical interferences. In this article, we focus on the interferences in the last level of cache (LLC) and use the Cache Allocation Technology (CAT) recently provided by Intel to partition the LLC and give each co-scheduled application their own cache area. We consider m iterative HPC applications running concurrently and answer to the following questions: (i) How to precisely model the behavior of these applications on the cache-partitioned platform? and (ii) how many cores and cache fractions should be assigned to each application to maximize the platform efficiency? Here, platform efficiency is defined as maximizing the performance either globally, or as guaranteeing a fixed ratio of iterations per second for each application. Through extensive experiments using CAT, we demonstrate the impact of cache partitioning when multiple HPC applications are co-scheduled onto CMP platforms.

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