PAPI 7.1.0.0
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pfmlib_gen_ia32.h
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1/*
2 * Intel architectural PMU v1, v2, v3
3 *
4 * Copyright (c) 2006-2007 Hewlett-Packard Development Company, L.P.
5 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
11 * of the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
18 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
19 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
20 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
21 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
22 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24#ifndef __PFMLIB_GEN_IA32_H__
25#define __PFMLIB_GEN_IA32_H__
26
27#include <perfmon/pfmlib.h>
28/*
29 * privilege level mask usage for architected PMU:
30 *
31 * PFM_PLM0 = OS (kernel, hypervisor, ..)
32 * PFM_PLM1 = unused (ignored)
33 * PFM_PLM2 = unused (ignored)
34 * PFM_PLM3 = USR (user level)
35 */
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41/*
42 * upper limit, actual number determined dynamically
43 */
44#define PMU_GEN_IA32_MAX_COUNTERS PFMLIB_MAX_PMCS
45
46/*
47 * Even though, CPUID 0xa returns in eax the actual counter
48 * width, the architecture specifies that writes are limited
49 * to lower 32-bits. As such, only the lower 32-bit have full
50 * degree of freedom. That is the "useable" counter width.
51 */
52#define PMU_GEN_IA32_COUNTER_WIDTH 32
53
54typedef union {
55 unsigned long long val; /* complete register value */
56 struct {
57 unsigned long sel_event_select:8; /* event mask */
58 unsigned long sel_unit_mask:8; /* unit mask */
59 unsigned long sel_usr:1; /* user level */
60 unsigned long sel_os:1; /* system level */
61 unsigned long sel_edge:1; /* edge detec */
62 unsigned long sel_pc:1; /* pin control */
63 unsigned long sel_int:1; /* enable APIC intr */
64 unsigned long sel_any:1; /* any thread (v3) */
65 unsigned long sel_en:1; /* enable */
66 unsigned long sel_inv:1; /* invert counter mask */
67 unsigned long sel_cnt_mask:8; /* counter mask */
68 unsigned long sel_res2:32;
69 } perfevtsel;
71
72typedef struct {
73 unsigned long cnt_mask; /* threshold (cnt_mask) */
74 unsigned int flags; /* counter specific flag */
76
77#define PFM_GEN_IA32_SEL_INV 0x1 /* inverse */
78#define PFM_GEN_IA32_SEL_EDGE 0x2 /* edge detect */
79#define PFM_GEN_IA32_SEL_ANYTHR 0x4 /* measure on any thread (v3 and up) */
80
81/*
82 * model-specific parameters for the library
83 */
84typedef struct {
86 uint64_t reserved[4]; /* for future use */
88
89typedef struct {
90 uint64_t reserved[8]; /* for future use */
92
93#ifdef __cplusplus /* extern C */
94}
95#endif
96
97#endif /* __PFMLIB_GEN_IA32_H__ */
uint16_t reserved
#define PMU_GEN_IA32_MAX_COUNTERS
unsigned long long val
unsigned long sel_event_select
unsigned long sel_cnt_mask
unsigned long sel_unit_mask