papi_events_table.h

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static char *papi_events_table =
"#\n"
"# Every CPU automatically has PAPI_TOT_CYC and PAPI_TOT_INS added\n"
"#\n"
"# Processor identifier and additional flags.\n"
"# The processor identifier *can not* contain any comma characters as these\n"
"# characters serve to delimit fields.\n"
"#\n"
"CPU,AMD64 (K7)\n"
"CPU,amd64_k7\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"#\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN\n"
"#\n"
"CPU,AMD64\n"
"CPU,AMD64 (unknown model)\n"
"CPU,AMD64 (K8 RevB)\n"
"CPU,AMD64 (K8 RevC)\n"
"CPU,AMD64 (K8 RevD)\n"
"CPU,AMD64 (K8 RevE)\n"
"CPU,AMD64 (K8 RevF)\n"
"CPU,AMD64 (K8 RevG)\n"
"CPU,amd64_k8_revb\n"
"CPU,amd64_k8_revc\n"
"CPU,amd64_k8_revd\n"
"CPU,amd64_k8_reve\n"
"CPU,amd64_k8_revf\n"
"CPU,amd64_k8_revg\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES\n"
"#\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"#\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN\n"
"#\n"
"PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:PACKED_SSE_AND_SSE2\n"
"#    This definition give an accurate count of the instructions retired through the FP unit\n"
"#    It counts just about everything except MMX and 3DNow instructions\n"
"#    Unfortunately, it also counts loads and stores. Therefore the count will be uniformly\n"
"#    high, but proportional to the work done.\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2\n"
"#/*  This definition is speculative but gives good answers on our simple test cases\n"
"#    It overcounts FP operations, sometimes by A LOT, but doesn't count loads and stores\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY:OPS_ADD,NOTE,'Counts speculative adds and multiplies. Variable and higher than theoretical.'\n"
"#\n"
"CPU,AMD64 FPU RETIRED\n"
"#\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,NOTE,'Counts all retired floating point operations, including data movement. Precise, and proportional to work done, but much higher than theoretical.'\n"
"#\n"
"CPU,AMD64 FPU SPECULATIVE\n"
"#\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY:OPS_ADD,NOTE,'Counts speculative adds and multiplies. Variable and higher than theoretical.'\n"
"#\n"
"CPU,AMD64 FPU SSE_SP\n"
"#\n"
"PRESET,PAPI_FP_OPS,DERIVED_SUB,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,DISPATCHED_FPU:OPS_STORE,NOTE,'Counts retired ops corrected for data motion. Optimized for single precision; lower than theoretical.'\n"
"#\n"
"CPU,AMD64 FPU SSE_DP\n"
"#\n"
"PRESET,PAPI_FP_OPS,DERIVED_SUB,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,DISPATCHED_FPU:OPS_STORE_PIPE_LOAD_OPS,NOTE,'Counts retired ops corrected for data motion. Optimized for double precision; lower than theoretical.'\n"
"#\n"
"########################\n"
"# AMD64                #\n"
"########################\n"
"CPU,AMD64 (Barcelona)\n"
"CPU,AMD64 (Barcelona RevB)\n"
"CPU,AMD64 (Barcelona RevC)\n"
"CPU,AMD64 (Family 10h RevB Barcelona)\n"
"CPU,AMD64 (Family 10h RevC Shanghai)\n"
"CPU,AMD64 (Family 10h RevD Istanbul)\n"
"CPU,AMD64 (Family 10h RevE)\n"
"CPU,amd64_fam10h_barcelona\n"
"CPU,amd64_fam10h_shanghai\n"
"CPU,amd64_fam10h_istanbul\n"
"CPU,amd64_fam11h_turion\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES\n"
"#\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL\n"
"#\n"
"# no L3_ preset definitions for multi-cores with shared L3 cache,\n"
"# as long as L3 events are automatically shadowed from core- to chip-space\n"
"# PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL\n"
"# PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL\n"
"# PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS:ALL\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS:ALL,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"#\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN\n"
"#\n"
"PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:PACKED_SSE_AND_SSE2\n"
"#\n"
"#    An analysis by Bill Homer of Cray indicates accurate counts over a range of conditions\n"
"#    John McCalpin reports that OP_TYPE expands packed operation counts appropriately.\n"
"#    Therefore, it is included in FP_OPS, but not in FP_INS.\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:OP_TYPE\n"
"PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS\n"
"PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS\n"
"#\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:OP_TYPE\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:OP_TYPE,NOTE,'Also includes subtract instructions'\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,'Counts both divide and square root instructions'\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,'Counts both divide and square root instructions'\n"
"########################\n"
"# AMD64 fam12h llano   #\n"
"########################\n"
"CPU,amd64_fam12h_llano\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES\n"
"#\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL\n"
"#\n"
"# no L3_ preset definitions for multi-cores with shared L3 cache,\n"
"# as long as L3 events are automatically shadowed from core- to chip-space\n"
"# PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL\n"
"# PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL\n"
"# PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS:ALL\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS:ALL,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"#\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN\n"
"#\n"
"PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:SSE_AND_SSE2\n"
"#\n"
"#    An analysis by Bill Homer of Cray indicates accurate counts over a range of conditions\n"
"#    John McCalpin reports that OP_TYPE expands packed operation counts appropriately.\n"
"#    Therefore, it is included in FP_OPS, but not in FP_INS.\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:OP_TYPE\n"
"PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS\n"
"PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS\n"
"#\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:OP_TYPE\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:OP_TYPE,NOTE,'Also includes subtract instructions'\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,'Counts both divide and square root instructions'\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,'Counts both divide and square root instructions'\n"
"#########################\n"
"# AMD Fam14h Bobcat     #\n"
"#########################\n"
"#\n"
"CPU,amd64_fam14h_bobcat\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN\n"
"PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_FLOATING_POINT_INSTRUCTIONS:ALL\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:ANY\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:ALL\n"
"PRESET,PAPI_VEC_SP,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS\n"
"PRESET,PAPI_VEC_DP,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS\n"
"#\n"
"CPU,AMD64 (Family 15h RevB)\n"
"CPU,amd64_fam15h_interlagos\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE\n"
"PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE,INSTRUCTION_CACHE_MISSES\n"
"#\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL\n"
"#\n"
"# not implemented: PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL\n"
"# not implemented: PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL\n"
"# not implemented: PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,UNIFIED_TLB_MISS:4K_DATA:2M_DATA:1GB_DATA\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,UNIFIED_TLB_MISS:4K_INST:2M_INST:1G_INST\n"
"PRESET,PAPI_TLB_TL,NOT_DERIVED,UNIFIED_TLB_MISS:ALL\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"#\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN\n"
"#\n"
"PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_FPU_EMPTY\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPS:ALL\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:ALL\n"
"PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS:SINGLE_MUL_ADD_OPS\n"
"PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS:DOUBLE_MUL_ADD_OPS\n"
"#\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:SINGLE_MUL_ADD_OPS:DOUBLE_MUL_ADD_OPS,NOTE,'Also includes multiply-add instructions'\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:SINGLE_MUL_ADD_OPS:DOUBLE_MUL_ADD_OPS,NOTE,'Also includes subtract and multiply-add instructions'\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,'Counts both divide and square root instructions'\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,'Counts both divide and square root instructions'\n"
"#\n"
"#\n"
"CPU,amd64_fam16h\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"#PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES\n"
"# Only have 3 slots???\n"
"#PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES\n"
"#\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,INSTRUCTION_CACHE_MISSES\n"
"#\n"
"# Note, need access to special L2 uncore events\n"
"#  to get L2 related events\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,DTLB_MISS,ITLB_MISS\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"#\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,INSTRUCTION_FETCH_STALL\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN\n"
"#\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS\n"
"PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS\n"
"PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS\n"
"#\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,'Counts both divide and square root instructions'\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,'Counts both divide and square root instructions'\n"
"#\n"
"#\n"
"CPU,amd64_fam17h\n"
"CPU,amd64_fam17h_zen1\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,32_BYTE_INSTRUCTION_CACHE_FETCH,32_BYTE_INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_FETCH\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_FETCH\n"
"# Same event code, confusing name?\n"
"#PRESET,PAPI_L1_DCM,NOT_DERIVED,MAB_ALLOCATION_BY_PIPE\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,32_BYTE_INSTRUCTION_CACHE_FETCH\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_MISSES\n"
"#\n"
"# Note, need access to special L2 uncore events\n"
"#  to get L2 related events\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT\n"
"PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:IF1G:IF2M:IF4K\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"# Note, the processor supports various kinds of mispredictions\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED\n"
"#\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,INSTRUCTION_PIPE_STALL:IC_STALL_ANY\n"
"#\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS\n"
"PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_ADD_SUB_FLOPS:SP_MULT_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS\n"
"PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_ADD_SUB_FLOPS:DP_MULT_FLOPS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS\n"
"#\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_MULT_FLOPS:DP_MULT_FLOPS\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_ADD_SUB_FLOPS:DP_ADD_SUB_FLOPS\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_DIV_FLOPS:DP_DIV_FLOPS,NOTE,'Counts both divide and square root instructions'\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_DIV_FLOPS:DP_DIV_FLOPS,NOTE,'Counts both divide and square root instructions'\n"
"# Events discovered via CAT\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L\n"
"PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_L_HIT_X\n"
"#\n"
"#\n"
"CPU,amd64_fam17h_zen2\n"
"# Events copied from zen1 that also exist on zen2\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT\n"
"PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:IF1G:IF2M:IF4K\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT\n"
"# Events discovered via CAT\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,perf::PERF_COUNT_HW_CACHE_L1D:ACCESS\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L\n"
"PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_L_HIT_X\n"
"#\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ\n"
"#\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S\n"
"# New FLOP event on zen2\n"
"# PPR (under section 2.1.15.3. --\n"
"# https://www.amd.com/system/files/TechDocs/54945_3.03_ppr_ZP_B2_pub.zip)\n"
"# explains that FLOP events require MergeEvent support, which was included \n"
"# in the 5.6 kernel. \n"
"# Hence, a kernel version 5.6 or greater is required.\n"
"# NOTE: without the MergeEvent support in the kernel, there is no guarantee\n"
"# that this SSE/AVX FLOP event produces any useful data whatsoever.  \n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY\n"
"# Since FP_OPS counts both single- and double-prec operations\n"
"# correctly, we don't need to confuse the user with additional\n"
"# DP_OPS and SP_OPS events. So, I'm taking them out.  \n"
"#PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY\n"
"#PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY\n"
"#\n"
"# Floating-point instructions (including non-numeric floating-point instructions,\n"
"# e.g. Move or Merge Scalar Double-Precision Floating-Point values)\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE_INSTR:MMX_INSTR:X87_INSTR\n"
"# Since FP_INS counts both single- and double-prec instuctions\n"
"# correctly, we don't need to confuse the user with additional\n"
"# VEC_DP and VEC_SP events. So, I'm taking them out.  \n"
"#PRESET,PAPI_VEC_DP,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE_INSTR:MMX_INSTR:X87_INSTR\n"
"#PRESET,PAPI_VEC_SP,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE_INSTR:MMX_INSTR:X87_INSTR\n"
"#\n"
"#\n"
"CPU,amd64_fam19h_zen3\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_UCN,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,DERIVED_POSTFIX,N0|N1|-|N2|+|,RETIRED_TAKEN_BRANCH_INSTRUCTIONS,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_NTK,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,    L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT\n"
"PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:COALESCED4K:IF1G:IF2M:IF4K\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,LS_DISPATCH:LD_ST_DISPATCH:STORE_DISPATCH:LD_DISPATCH\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X\n"
"PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C_S:LS_RD_BLK_L_HIT_X:LS_RD_BLK_L_HIT_S:LS_RD_BLK_X\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S\n"
"# RETIRED_SSE_AVX_FLOPS requires MergeEvent support.\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:MULT_FLOPS\n"
"PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ADD_SUB_FLOPS\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:DIV_FLOPS\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:DIV_FLOPS\n"
"#\n"
"#\n"
"CPU,amd64_fam19h_zen4\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_UCN,NOT_DERIVED,RETIRED_UNCONDITIONAL_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_TKN,DERIVED_SUB,RETIRED_TAKEN_BRANCH_INSTRUCTIONS,RETIRED_UNCONDITIONAL_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_NTK,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_TAKEN_BRANCH_INSTRUCTIONS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY\n"
"PRESET,PAPI_FP_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_ALL,RETIRED_FP_OPS_BY_TYPE:SCALAR_ALL\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_FP_OPS_BY_TYPE:VECTOR_ALL\n"
"PRESET,PAPI_FMA_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_MAC,RETIRED_FP_OPS_BY_TYPE:SCALAR_MAC\n"
"PRESET,PAPI_FML_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_MUL,RETIRED_FP_OPS_BY_TYPE:SCALAR_MUL\n"
"PRESET,PAPI_FAD_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_ADD,RETIRED_FP_OPS_BY_TYPE:SCALAR_ADD\n"
"PRESET,PAPI_FDV_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_DIV,RETIRED_FP_OPS_BY_TYPE:SCALAR_DIV\n"
"PRESET,PAPI_FSQ_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_SQRT,RETIRED_FP_OPS_BY_TYPE:SCALAR_SQRT\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,LS_DISPATCH:LD_ST_DISPATCH:STORE_DISPATCH:LD_DISPATCH\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X\n"
"PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C_S:LS_RD_BLK_L_HIT_X:LS_RD_BLK_L_HIT_S:LS_RD_BLK_X\n"
"PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:COALESCED4K:IF1G:IF2M:IF4K\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ:L2_HW_PF\n"
"PRESET,PAPI_L2_ICM,DERIVED_SUB,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S\n"
"PRESET,PAPI_L2_TCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C_S:LS_RD_BLK_L_HIT_X:LS_RD_BLK_L_HIT_S:LS_RD_BLK_X:IC_FILL_HIT_X:IC_FILL_HIT_S\n"
"PRESET,PAPI_L2_TCM,DERIVED_ADD,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS\n"
"CPU,Intel architectural PMU\n"
"CPU,ix86arch\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS\n"
"#\n"
"# Intel Atom\n"
"CPU,Intel Atom\n"
"CPU,atom\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES\n"
"PRESET,PAPI_L1_DCM,DERIVED_SUB,L2_RQSTS:SELF:MESI,ICACHE:MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,ICACHE:ACCESSES,ICACHE:MISSES\n"
"#PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE:LD:ST\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_CACHE:LD,L1D_CACHE:ST\n"
"PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:SELF:MESI\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:SELF:ANY\n"
"PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,L2_M_LINES_IN:SELF\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:SELF:ANY:MESI\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:SELF:MESI,BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:SELF:ANY:MESI,L2_LINES_IN:SELF:ANY\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:SELF:ANY:MESI\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI\n"
"#\n"
"PRESET,PAPI_CA_SNP,NOT_DERIVED,EXT_SNOOP:SELF:MESI\n"
"PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE\n"
"PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF\n"
"PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF\n"
"#\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB:MISSES\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DATA_TLB_MISSES:DTLB_MISS\n"
"#\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:PRED_NOT_TAKEN:MISPRED_NOT_TAKEN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED\n"
"#\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:ALL_DECODED\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RCV\n"
"#PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY\n"
"#\n"
"#PRESET,PAPI_FP_INS,NOT_DERIVED,X87_COMP_OPS_EXE:ANY_AR\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,SIMD_INST_RETIRED:ANY\n"
"#PRESET,PAPI_FP_OPS,NOT_DERIVED,X87_COMP_OPS_EXE:ANY_AR\n"
"#PRESET,PAPI_FP_OPS,NOT_DERIVED,SIMD_UOPS_EXEC:AR\n"
"PRESET,PAPI_FP_OPS,DERIVED_ADD,SIMD_INST_RETIRED:ANY,X87_COMP_OPS_EXE:ANY_AR\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,MUL:AR\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV:AR\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR\n"
"#\n"
"# Intel Atom Silvermont\n"
"CPU,slm\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,ICACHE:ACCESSES,ICACHE:MISSES\n"
"PRESET,PAPI_L1_TCM,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_MISSES\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,LLC_REFERENCES,LLC_MISSES\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,LLC_REFERENCES\n"
"#\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:JCC\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED\n"
"#\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,UOPS_RETIRED:STALLS\n"
"#\n"
"#PRESET,PAPI_FP_INS,NOT_DERIVED,UOPS_RETIRED:X87\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,UOPS_RETIRED:MUL\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,UOPS_RETIRED:DIV\n"
"#\n"
"CPU,Intel Nehalem\n"
"CPU,Intel Westmere\n"
"CPU,nhm\n"
"CPU,nhm_ex\n"
"CPU,wsm\n"
"CPU,wsm_dp\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTION_RETIRED\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I:MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I:READS\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,L1I:HITS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPL\n"
"#PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:SELF:MESI\n"
"#PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI\n"
"#PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI\n"
"# OLD VALUE PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_RQSTS:MISS,L2_RQSTS:IFETCH_MISS\n"
"PRESET,PAPI_L2_DCM,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:IFETCH_MISS\n"
"# OLD VALUE PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_RQSTS:MISS\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:LD_MISS\n"
"#PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF\n"
"# OLD VALUE PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_DATA_RQSTS:ANY\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPL\n"
"# OLD VALUE PRESET,PAPI_L2_DCR,DERIVED_SUB,L2_RQSTS:LOADS,L2_RQSTS:IFETCHES\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:LOADS\n"
"#PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:IFETCH_HIT\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:IFETCHES\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:REFERENCES, L2_RQSTS:MISS\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:REFERENCES\n"
"# OLD VALUE PRESET,PAPI_L2_TCR,NOT_DERIVED,L2_RQSTS:LOADS\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:LOADS,L2_RQSTS:IFETCHES\n"
"#PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI\n"
"#\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,L1I:READS\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:LOADS\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,L2_WRITE:RFO_MESI\n"
"PRESET,PAPI_L1_TCM,DERIVED_SUB,L2_RQSTS:REFERENCES,L2_RQSTS:PREFETCHES\n"
"PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:LD_HIT,L2_RQSTS:RFO_HIT\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_WRITE:RFO_MESI\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:IFETCHES\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFOS\n"
"PRESET,PAPI_L3_DCA,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,L2_RQSTS:LD_MISS\n"
"PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:IFETCH_MISS\n"
"PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:IFETCH_MISS\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES\n"
"PRESET,PAPI_L3_TCR,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:IFETCH_MISS\n"
"PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:LOADS,MEM_INST_RETIRED:STORES\n"
"#\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:LOADS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:STORES\n"
"#\n"
"#PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE\n"
"#PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF\n"
"#PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF\n"
"#\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:ANY\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISSES:ANY\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,ITLB_MISSES:ANY, DTLB_MISSES:ANY\n"
"#\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_EXEC:TAKEN\n"
"PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_EXEC:ANY, BR_INST_EXEC:TAKEN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_EXEC:ANY\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_EXEC:ANY\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_EXEC:COND\n"
"PRESET,PAPI_BR_UCN,NOT_DERIVED,BR_INST_EXEC:DIRECT\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_EXEC:COND, BR_MISP_EXEC:COND\n"
"#\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:DECODED\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY\n"
"#\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP\n"
"# PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP\n"
"# PAPI_FP_OPS counts single and double precision SCALAR operations\n"
"# PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION:SSE_DOUBLE_PRECISION\n"
"# According to Stephane (Jan 2010), it's not allowed to combine unit masks for FP_COMP_OPS_EXE;\n"
"# we have to use two counters instead\n"
"#PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION,FP_COMP_OPS_EXE:SSE_DOUBLE_PRECISION\n"
"PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_FP,FP_COMP_OPS_EXE:X87\n"
"# PAPI_SP_OPS = single precision scalar ops + 3 * packed ops\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|3|*|+|,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION,FP_COMP_OPS_EXE:SSE_FP_PACKED\n"
"PRESET,PAPI_DP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_DOUBLE_PRECISION,FP_COMP_OPS_EXE:SSE_FP_PACKED\n"
"PRESET,PAPI_VEC_SP,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP_PACKED\n"
"PRESET,PAPI_VEC_DP,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP_PACKED\n"
"#PRESET,PAPI_FML_INS,NOT_DERIVED,MUL\n"
"#PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV\n"
"#PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR\n"
"#\n"
"# Not available on Westmere\n"
"#\n"
"CPU,Intel Nehalem\n"
"CPU,nhm\n"
"CPU,nhm_ex\n"
"#PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT:RCV\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_ALL_REF:ANY\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_ALL_REF:ANY,L1D:REPL\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_ALL_REF:ANY,L1I:READS\n"
"#\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_LD:MESI\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_ST:MESI\n"
"PRESET,PAPI_L1_TCR,DERIVED_ADD,L1D_CACHE_LD:MESI,L1I:READS\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L1D_CACHE_ST:MESI\n"
"#\n"
"# Intel SandyBridge and IvyBridge\n"
"CPU,snb\n"
"CPU,snb_ep\n"
"CPU,ivb\n"
"CPU,ivb_ep\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTION_RETIRED\n"
"#\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,ICACHE:MISSES,L1D:REPLACEMENT\n"
"#\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES\n"
"PRESET,PAPI_L2_TCA,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD\n"
"#\n"
"PRESET,PAPI_L3_DCA,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD\n"
"PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES\n"
"PRESET,PAPI_L3_TCR,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:RFO_MISS\n"
"PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS\n"
"#\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:NOT_TAKEN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:ALL_BRANCHES\n"
"#\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:CAUSES_A_WALK\n"
"#\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,ARITH:FPU_DIV\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,ILD_STALL:IQ_FULL\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_LOADS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_STORES\n"
"#\n"
"# Counts scalars only; no SSE or AVX is counted; includes speculative\n"
"PRESET,PAPI_FP_INS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:X87\n"
"PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:X87\n"
"#\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|N2|8|*|+|+|,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,SIMD_FP_256:PACKED_SINGLE\n"
"PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|N2|4|*|+|+|,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,SIMD_FP_256:PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|4|*|N1|8|*|+|,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,SIMD_FP_256:PACKED_SINGLE\n"
"PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|2|*|N1|4|*|+|,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,SIMD_FP_256:PACKED_DOUBLE\n"
"#\n"
"# Intel SandyBridge only\n"
"CPU,snb\n"
"CPU,snb_ep\n"
"#\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFO_ANY\n"
"PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_RD_HIT,L2_RQSTS:RFO_HITS\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL\n"
"PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_MISP_RETIRED:ALL_BRANCHES\n"
"PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_INST_RETIRED:NOT_TAKEN\n"
"PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK\n"
"#\n"
"# Intel IvyBridge only\n"
"CPU,ivb\n"
"CPU,ivb_ep\n"
"#\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:ALL_RFO\n"
"PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:DEMAND_DATA_RD_HIT,L2_RQSTS:RFO_HIT\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND\n"
"PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:COND,BR_MISP_RETIRED:ALL_BRANCHES\n"
"PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:COND,BR_INST_RETIRED:NOT_TAKEN\n"
"PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK\n"
"#PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INTERRUPTS\n"
"#\n"
"# Intel Haswell events\n"
"# Using also for Broadwell events, this is what the Linux kernel does\n"
"CPU,hsw\n"
"CPU,hsw_ep\n"
"CPU,bdw\n"
"CPU,bdw_ep\n"
"CPU,skl\n"
"# Note, libpfm4 treats Kaby Lake as just a form of skylake\n"
"CPU,kbl\n"
"CPU,skx\n"
"# Note, libpfm4 treats Cascade Lake-X as just a form of skylake-X\n"
"CPU,clx\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:THREAD_P\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"#PRESET,PAPI_REF_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:REF_XCLK\n"
"# Loads and stores\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ALL_LOADS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ALL_STORES\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_UOPS_RETIRED:ALL_LOADS,MEM_UOPS_RETIRED:ALL_STORES\n"
"# L1 cache\n"
"#PRESET,PAPI_L1_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L1_HIT\n"
"#PRESET,PAPI_L1_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L1_MISS\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"# Added by FMB\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD\n"
"# L2 cache\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_REFERENCES\n"
"# NOTE on IVB it is PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT\n"
"#PRESET,PAPI_L2_DCH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT\n"
"#PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"#PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:REFERENCES\n"
"#PRESET,PAPI_L2_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_HIT\n"
"#PRESET,PAPI_L2_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_MISS\n"
"# Added by FMB\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"#PRESET,PAPI_L2_LDH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS\n"
"PRESET,PAPI_L2_TCA,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_REFERENCES,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD\n"
"# L3 cache\n"
"#PRESET,PAPI_L3_TCA,NOT_DERIVED,LONGEST_LAT_CACHE:REFERENCE\n"
"#PRESET,PAPI_L3_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT\n"
"#PRESET,PAPI_L3_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_MISS\n"
"# Added by FMB\n"
"PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD\n"
"PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"#PRESET,PAPI_L3_LDH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_MISS\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES\n"
"PRESET,PAPI_L3_TCR,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:DEMAND_RFO_MISS\n"
"PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS\n"
"# SMP\n"
"PRESET,PAPI_CA_SNP,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_ANY\n"
"PRESET,PAPI_CA_SHR,NOT_DERIVED,OFFCORE_REQUESTS:ALL_DATA_RD\n"
"PRESET,PAPI_CA_CLN,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_RFO\n"
"# TLB\n"
"PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK,DTLB_STORE_MISSES:MISS_CAUSES_A_WALK\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:MISS_CAUSES_A_WALK\n"
"# Stalls\n"
"PRESET,PAPI_MEM_WCY,NOT_DERIVED,RESOURCE_STALLS:SB\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY\n"
"PRESET,PAPI_STL_CCY,NOT_DERIVED,UOPS_RETIRED:ALL:c=1:i=1\n"
"PRESET,PAPI_FUL_ICY,DERIVED_ADD,IDQ:ALL_DSB_CYCLES_4_UOPS,IDQ:ALL_MITE_CYCLES_4_UOPS\n"
"PRESET,PAPI_FUL_CCY,NOT_DERIVED,UOPS_RETIRED:ALL:c=4\n"
"# Branches\n"
"PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL\n"
"PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_INST_RETIRED:NOT_TAKEN\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:NOT_TAKEN\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:CONDITIONAL\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_MISP_RETIRED:CONDITIONAL\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES\n"
"CPU,hsw\n"
"CPU,hsw_ep\n"
"CPU,bdw\n"
"CPU,bdw_ep\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_TRANS:DEMAND_DATA_RD\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,L2_TRANS:L1D_WB\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_TRANS:RFO\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_TRANS:RFO\n"
"PRESET,PAPI_PRF_DM,NOT_DERIVED,L2_RQSTS:L2_PF_MISS\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ:EMPTY\n"
"PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_FWD\n"
"CPU,hsw\n"
"CPU,hsw_ep\n"
"PRESET,PAPI_CA_INV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HITM\n"
"CPU,bdw\n"
"CPU,bdw_ep\n"
"PRESET,PAPI_CA_INV,NOT_DERIVED,OFFCORE_RESPONSE_0:HITM\n"
"# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE\n"
"PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE\n"
"# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE\n"
"PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE\n"
"CPU,skl\n"
"CPU,skx\n"
"CPU,clx\n"
"# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE + 8*512B_PACKED_DOUBLE\n"
"PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE\n"
"# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE + 16*512B_PACKED_SINGLE\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE\n"
"PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,L2_RQSTS:ALL_RFO\n"
"PRESET,PAPI_L2_DCW,DERIVED_ADD,L2_RQSTS:DEMAND_RFO_HIT,L2_RQSTS:RFO_HIT\n"
"PRESET,PAPI_L2_TCW,DERIVED_ADD,L2_RQSTS:DEMAND_RFO_HIT,L2_RQSTS:RFO_HIT\n"
"PRESET,PAPI_PRF_DM,NOT_DERIVED,L2_RQSTS:PF_MISS\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ_UOPS_NOT_DELIVERED:CYCLES_0_UOPS_DELIV_CORE\n"
"PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HIT_WITH_FWD\n"
"# End of hsw,bdw,skl,clx list\n"
"#\n"
"# Intel Ice Lake SP events\n"
"CPU,icx\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:THREAD_P\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"# Loads and stores\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_LOADS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_STORES\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:ALL_LOADS,MEM_INST_RETIRED:ALL_STORES\n"
"# L1 cache\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD\n"
"# L2 cache\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_REFERENCES\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"#PRESET,PAPI_L2_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_HIT\n"
"#PRESET,PAPI_L2_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_MISS\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"#PRESET,PAPI_L2_LDH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS\n"
"PRESET,PAPI_L2_TCA,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_REFERENCES,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD\n"
"# L3 cache\n"
"PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"#PRESET,PAPI_L3_LDH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES\n"
"# SMP\n"
"PRESET,PAPI_CA_SHR,NOT_DERIVED,OFFCORE_REQUESTS:ALL_DATA_RD\n"
"# Branches\n"
"PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:COND_TAKEN\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:COND_NTAKEN\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:COND\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:COND,BR_MISP_RETIRED:COND\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES\n"
"#FLOPs\n"
"# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE + 8*512B_PACKED_DOUBLE\n"
"PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE\n"
"# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE + 16*512B_PACKED_SINGLE\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|N4|+|N5|2|*|+|N6|4|*|+|N7|8|*|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_FP_INS,DERIVED_POSTFIX,N0|N1|N2|N3|N4|N5|N6|N7|+|+|+|+|+|+|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE\n"
"PRESET,PAPI_VEC_INS,DERIVED_POSTFIX,N0|N1|N2|N3|N4|N5|+|+|+|+|+|,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"# End of icx list\n"
"# Intel Sapphire Rapids events\n"
"CPU,spr\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:THREAD_P\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"# FLOPs\n"
"PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|N4|+|N5|2|*|+|N6|4|*|+|N7|8|*|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_FP_INS,DERIVED_POSTFIX,N0|N1|N2|N3|N4|N5|N6|N7|+|+|+|+|+|+|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE\n"
"PRESET,PAPI_VEC_INS,DERIVED_POSTFIX,N0|N1|N2|N3|N4|N5|+|+|+|+|+|,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE\n"
"# Branches\n"
"PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:COND_TAKEN\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:COND_NTAKEN\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:COND\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:COND,BR_MISP_RETIRED:COND\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES\n"
"# Instruction Caches\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS\n"
"# Loads and stores\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_LOADS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_STORES\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:ALL_LOADS,MEM_INST_RETIRED:ALL_STORES\n"
"# Data Caches\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD\n"
"#PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,OFFCORE_REQUESTS:DATA_RD\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS\n"
"#PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS\n"
"PRESET,PAPI_L3_DCA,NOT_DERIVED,OFFCORE_REQUESTS:DATA_RD\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS\n"
"# SMP\n"
"PRESET,PAPI_CA_SHR,NOT_DERIVED,OFFCORE_REQUESTS:DATA_RD\n"
"# Total Caches\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_TCA,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES\n"
"# End of spr list\n"
"#\n"
"# Intel MIC / Xeon-Phi / Knights Landing\n"
"# Intel Knights Mill\n"
"#\n"
"CPU,knl\n"
"CPU,knm\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,ICACHE:HIT\n"
"#\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,MEM_UOPS_RETIRED:ANY_LD,MEM_UOPS_RETIRED:ANY_ST\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_DCU_MISS\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,MEM_UOPS_RETIRED:LD_DCU_MISS,ICACHE:MISSES\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_DCU_MISS\n"
"#\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,LLC_REFERENCES\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_MISSES\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,LLC_REFERENCES,LLC_MISSES\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_L2_MISS\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ANY_LD\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ANY_ST\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_UOPS_RETIRED:ANY_LD,MEM_UOPS_RETIRED:ANY_ST\n"
"#\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_UTLB_MISS\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:JCC\n"
"PRESET,PAPI_BR_UCN,DERIVED_SUB,BRANCH_INSTRUCTIONS_RETIRED,BR_INST_RETIRED:JCC\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN_JCC\n"
"PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_RETIRED:JCC,BR_INST_RETIRED:TAKEN_JCC\n"
"#\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,RS_FULL_STALL:ANY\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,NO_ALLOC_CYCLES:ANY\n"
"#\n"
"# End of knl,knm list\n"
"CPU,Intel Core2\n"
"CPU,Intel Core\n"
"CPU,core\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_MISSES\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_READS\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_READS,L1I_MISSES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_REPL\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_ALL_REF\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_ALL_REF,L1D_REPL\n"
"PRESET,PAPI_L1_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_ALL_REF,L1I_READS\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:SELF:ANY\n"
"PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,L2_M_LINES_IN:SELF\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:SELF:ANY:MESI\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:SELF:MESI,BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:SELF:ANY:MESI,L2_LINES_IN:SELF:ANY\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:SELF:ANY:MESI\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI\n"
"#\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,INST_RETIRED:LOADS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,INST_RETIRED:STORES\n"
"#\n"
"PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE\n"
"PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF\n"
"PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF\n"
"#\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB:MISSES\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISSES:ANY\n"
"#\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:PRED_NOT_TAKEN:MISPRED_NOT_TAKEN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_EXEC\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISSP_EXEC\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_CND_EXEC\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_CND_EXEC,BR_CND_MISSP_EXEC\n"
"#\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:DECODED\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RCV\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY\n"
"#\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_OPS_EXE\n"
"# This is an alternate definition of OPS that produces no error with calibrate\n"
"# the previous definition was identical to FP_INS\n"
"# PRESET,PAPI_FP_OPS,NOT_DERIVED,X87_OPS_RETIRED:ANY\n"
"# PRESET,PAPI_FP_OPS,DERIVED_ADD, FP_COMP_OPS_EXE, SIMD_COMP_INST_RETIRED:SCALAR_DOUBLE:PACKED_DOUBLE:SCALAR_SINGLE:PACKED_SINGLE\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE\n"
"# PAPI_SP_OPS = FP_COMP_OPS_EXE + 3 * SIMD_COMP_INST_RETIRED:PACKED_SINGLE\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|3|*|+|,FP_COMP_OPS_EXE,SIMD_COMP_INST_RETIRED:PACKED_SINGLE\n"
"PRESET,PAPI_DP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE,SIMD_COMP_INST_RETIRED:PACKED_DOUBLE\n"
"PRESET,PAPI_VEC_SP,NOT_DERIVED,SIMD_COMP_INST_RETIRED:PACKED_SINGLE\n"
"PRESET,PAPI_VEC_DP,NOT_DERIVED,SIMD_COMP_INST_RETIRED:PACKED_DOUBLE\n"
"#\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,MUL\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR\n"
"#\n"
"CPU,Intel Core Duo/Solo\n"
"CPU,coreduo\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_TAKEN_RET\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_INSTR_RET\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_INSTR_RET\n"
"#\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED, DCACHE_REPL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED, L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB, L2_LINES_IN:SELF:ANY, BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED, BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L1_TCM,NOT_DERIVED, L2_RQSTS:SELF:MESI\n"
"#PRESET,PAPI_L2_TCM,NOT_DERIVED, L2_LINES_IN:SELF:ANY\n"
"PRESET,PAPI_CA_SHR,NOT_DERIVED, L2_RQSTS:SELF:ANY:S_STATE\n"
"PRESET,PAPI_CA_CLN,NOT_DERIVED, BUS_TRANS_RFO:SELF\n"
"PRESET,PAPI_CA_ITV,NOT_DERIVED, BUS_TRANS_INVAL:SELF\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED, ITLB_MISSES\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED, DTLB_MISS\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED, L2_LD:SELF:MESI\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED, L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_LDM,DERIVED_SUB, L2_LINES_IN:SELF:ANY, L2_M_LINES_IN:SELF\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED, L2_M_LINES_IN:SELF\n"
"PRESET,PAPI_BTAC_M,NOT_DERIVED, PREF_RQSTS_DN\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED, HW_INT_RX\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED, BR_CND_EXEC\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED, BR_TAKEN_RET\n"
"PRESET,PAPI_BR_NTK,DERIVED_SUB, BR_INSTR_RET,BR_TAKEN_RET\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED, BR_MISSP_EXEC\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB, BR_INSTR_RET,BR_MISPRED_RET\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED, INSTR_DECODED\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED, RESOURCE_STALL\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB, DATA_MEM_REF, DCACHE_REPL\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED, DATA_MEM_REF\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD, L2_LD:SELF:MESI, L2_ST:SELF:MESI\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED, L2_LD:SELF:MESI\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED, L2_ST:SELF:MESI\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB, BUS_TRANS_IFETCH:SELF, L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_ICH,DERIVED_SUB, L2_IFETCH:SELF:MESI, BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED, BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED, L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED, BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED, L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB, L2_RQSTS:SELF:ANY:MESI, L2_LINES_IN:SELF:ANY\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD, DATA_MEM_REF, BUS_TRANS_IFETCH:SELF\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED, L2_RQSTS:SELF:ANY:MESI\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD, L2_LD:SELF:MESI, L2_IFETCH:SELF:MESI\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED, L2_ST:SELF:MESI\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED, MUL\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED, DIV\n"
"#\n"
"CPU,Intel PentiumIII\n"
"CPU,Intel P6 Processor Family\n"
"CPU,p6\n"
"#\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN,BUS_TRAN_IFETCH:SELF\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN\n"
"PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN,L2_M_LINES_INM\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:M:E:S:I,L2_LINES_IN\n"
"#\n"
"CPU,Intel PentiumM\n"
"CPU,Intel Pentium M\n"
"CPU,pm\n"
"#\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH,BUS_TRAN_IFETCH:SELF\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH\n"
"PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH,L2_M_LINES_INM\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:M:E:S:I,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH\n"
"#\n"
"CPU,Intel P6\n"
"CPU,Intel PentiumIII\n"
"CPU,Intel PentiumM\n"
"CPU,Intel P6 Processor Family\n"
"CPU,Intel Pentium Pro\n"
"CPU,Intel Pentium II\n"
"CPU,Intel Pentium M\n"
"CPU,p6\n"
"CPU,ppro\n"
"CPU,pii\n"
"CPU,pm\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DCU_LINES_IN\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_IFETCH:M:E:S:I\n"
"PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:M:E:S:I\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:M:E:S:I\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:M:E:S:I\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_MEM_REFS,DCU_LINES_IN\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_MEM_REFS\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,IFU_IFETCH,L2_IFETCH:M:E:S:I\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,IFU_IFETCH\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,IFU_IFETCH\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_MEM_REFS,IFU_IFETCH\n"
"#\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRAN_IFETCH:SELF\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_INM\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:M:E:S:I,L2_ST:M:E:S:I\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:M:E:S:I\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:M:E:S:I\n"
"PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:M:E:S:I,BUS_TRAN_IFETCH:SELF\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:M:E:S:I\n"
"PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_IFETCH:M:E:S:I\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:M:E:S:I\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:M:E:S:I,L2_IFETCH:M:E:S:I\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:M:E:S:I\n"
"#\n"
"PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:S\n"
"PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF\n"
"PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRAN_INVAL:SELF\n"
"#\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RX\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_DECODED\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS\n"
"#\n"
"PRESET,PAPI_BTAC_M,NOT_DERIVED,BTB_MISSES\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_TAKEN_RETIRED\n"
"PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_RETIRED,BR_TAKEN_RETIRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISS_PRED_RETIRED\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED,BR_MISS_PRED_RETIRED\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED\n"
"#\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FLOPS\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,FLOPS\n"
"PRESET,PAPI_FML_INS,NOT_DERIVED,MUL\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV\n"
"#\n"
"# This is an example of multiple processor names matching the same table\n"
"CPU,Intel Pentium4\n"
"CPU,Intel Pentium4 L3\n"
"CPU,Pentium4/Xeon/EM64T\n"
"CPU,netburst\n"
"CPU,netburst_p\n"
"#\n"
"# Note: the proper event is GLOBAL_POWER_EVENTS:RUNNING\n"
"#       but the kernel grabs that for the watchdog timer\n"
"#       and suggests '' is equivalent\n"
"#PRESET,PAPI_TOT_CYC,NOT_DERIVED,GLOBAL_POWER_EVENTS:RUNNING\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,execution_event:nbogus0:nbogus1:nbogus2:nbogus3:bogus0:bogus1:bogus2:bogus3:cmpl:thr=15\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_RETIRED:NBOGUSNTAG\n"
"PRESET,PAPI_RES_STL, NOT_DERIVED, resource_stall:SBFULL\n"
"PRESET,PAPI_BR_INS, NOT_DERIVED, branch_retired:MMNP:MMNM:MMTP:MMTM\n"
"PRESET,PAPI_BR_TKN, NOT_DERIVED, branch_retired:MMTP:MMTM\n"
"PRESET,PAPI_BR_NTK, NOT_DERIVED, branch_retired:MMNP:MMNM\n"
"PRESET,PAPI_BR_MSP, NOT_DERIVED, branch_retired:MMNM:MMTM\n"
"PRESET,PAPI_BR_PRC, NOT_DERIVED, branch_retired:MMNP:MMTP\n"
"PRESET,PAPI_TLB_DM, NOT_DERIVED, page_walk_type:DTMISS\n"
"PRESET,PAPI_TLB_IM, NOT_DERIVED, page_walk_type:ITMISS\n"
"PRESET,PAPI_TLB_TL, NOT_DERIVED, page_walk_type:DTMISS:ITMISS\n"
"PRESET,PAPI_LD_INS, DERIVED_CMPD, front_end_event:NBOGUS, uops_type:TAGLOADS\n"
"PRESET,PAPI_SR_INS, DERIVED_CMPD, front_end_event:NBOGUS, uops_type:TAGSTORES\n"
"PRESET,PAPI_LST_INS, DERIVED_CMPD, front_end_event:NBOGUS, uops_type:TAGLOADS:TAGSTORES\n"
"PRESET,PAPI_FP_INS, DERIVED_CMPD, execution_event:NBOGUS0, x87_FP_uop:ALL:TAG0,NOTE,'PAPI_FP_INS counts only retired x87 uops tagged with 0. If you add other native events tagged with 0, their counts will be included in PAPI_FP_INS'\n"
"PRESET,PAPI_TOT_IIS, NOT_DERIVED, instr_retired:NBOGUSNTAG:NBOGUSTAG:BOGUSNTAG:BOGUSTAG, NOTE, 'Only on model 2 and above'\n"
"PRESET,PAPI_L1_ICM, NOT_DERIVED, BPU_fetch_request:TCMISS\n"
"PRESET,PAPI_L1_ICA, NOT_DERIVED, uop_queue_writes:FROM_TC_BUILD:FROM_TC_DELIVER\n"
"PRESET,PAPI_L1_LDM, NOT_DERIVED, replay_event:NBOGUS:L1_LD_MISS\n"
"PRESET,PAPI_L2_LDM, NOT_DERIVED, replay_event:NBOGUS:L2_LD_MISS\n"
"PRESET,PAPI_L2_TCH, NOT_DERIVED, BSQ_cache_reference:RD_2ndL_HITS:RD_2ndL_HITE:RD_2ndL_HITM\n"
"PRESET,PAPI_L2_TCM, NOT_DERIVED, BSQ_cache_reference:RD_2ndL_MISS\n"
"PRESET,PAPI_L2_TCA, NOT_DERIVED, BSQ_cache_reference:RD_2ndL_MISS:RD_2ndL_HITS:RD_2ndL_HITE:RD_2ndL_HITM\n"
"#\n"
"CPU,Intel Pentium4 L3\n"
"PRESET,PAPI_L3_TCH, NOT_DERIVED, BSQ_cache_reference:RD_3rdL_HITS:RD_3rdL_HITE:RD_3rdL_HITM\n"
"PRESET,PAPI_L3_TCM, NOT_DERIVED, BSQ_cache_reference:RD_3rdL_MISS\n"
"PRESET,PAPI_L3_TCA, NOT_DERIVED, BSQ_cache_reference:RD_3rdL_MISS:RD_3rdL_HITS:RD_3rdL_HITE:RD_3rdL_HITM\n"
"#\n"
"CPU,Intel Pentium4 FPU X87\n"
"PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, x87_FP_uop:ALL:TAG1,NOTE,'PAPI_FP_OPS counts retired x87 uops tagged with 1.'\n"
"#\n"
"CPU,Intel Pentium4 FPU SSE_SP\n"
"PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_SP_uop:ALL:TAG1,NOTE,'PAPI_FP_OPS counts retired scalar_SP SSE uops tagged with 1.'\n"
"#\n"
"CPU,Intel Pentium4 FPU SSE_DP\n"
"PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_DP_uop:ALL:TAG1,NOTE,'PAPI_FP_OPS counts retired scalar_DP SSE uops tagged with 1.'\n"
"#\n"
"CPU,Intel Pentium4 FPU X87 SSE_SP\n"
"PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_SP_uop:ALL:TAG1, x87_FP_uop:ALL:TAG1,NOTE,'PAPI_FP_OPS counts retired x87 and scalar_SP SSE uops tagged with 1.'\n"
"#\n"
"CPU,Intel Pentium4 FPU X87 SSE_DP\n"
"PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_DP_uop:ALL:TAG1, x87_FP_uop:ALL:TAG1,NOTE,'PAPI_FP_OPS counts retired x87 and scalar_DP SSE uops tagged with 1.'\n"
"#\n"
"CPU,Intel Pentium4 FPU SSE_SP SSE_DP\n"
"PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_SP_uop:ALL:TAG1, scalar_DP_uop:ALL:TAG1,NOTE,'PAPI_FP_OPS counts retired scalar_SP and scalar_DP SSE uops tagged with 1.'\n"
"#\n"
"CPU,Intel Pentium4 VEC MMX\n"
"PRESET,PAPI_VEC_INS, DERIVED_CMPD, execution_event:NBOGUS2, 64bit_MMX_uop:ALL:TAG2, 128bit_MMX_uop:ALL:TAG2,NOTE,'PAPI_VEC_INS counts retired 64bit and 128bit MMX uops tagged with 2.'\n"
"#\n"
"CPU,Intel Pentium4 VEC SSE\n"
"PRESET,PAPI_VEC_INS, DERIVED_CMPD, execution_event:NBOGUS2, packed_SP_uop:ALL:TAG2, packed_DP_uop:ALL:TAG2,NOTE,'PAPI_VEC_INS counts retired packed single and double precision SSE uops tagged with 2.'\n"
"#\n"
"CPU,IA-64\n"
"#\n"
"CPU,dual-core Itanium 2\n"
"#\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_OPS_RETIRED\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,DISP_STALLED\n"
"PRESET,PAPI_STL_CCY,NOT_DERIVED,BACK_END_BUBBLE_ALL\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_DISPERSED\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,BE_EXE_BUBBLE_ALL\n"
"PRESET,PAPI_FP_STAL,NOT_DERIVED,BE_EXE_BUBBLE_FRALL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L2I_READS_ALL_DMND\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_READ_MISSES_ALL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2I_READS_MISS_ALL\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L2I_READS_MISS_ALL\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_MISSES\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,L3_READS_INST_FETCH_MISS:M:E:S:I\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,L3_READS_ALL_MISS:M:E:S:I\n"
"PRESET,PAPI_L3_STM,NOT_DERIVED,L3_WRITES_DATA_WRITE_MISS:M:E:S:I\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,L1D_READ_MISSES_ALL\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L3_READS_ALL_ALL:M:E:S:I\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L3_WRITES_ALL_ALL:M:E:S:I\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_READS_SET1\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_REFERENCES_ALL\n"
"PRESET,PAPI_L3_DCA,NOT_DERIVED,L3_REFERENCES\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READS_SET1\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_REFERENCES_READS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,L3_READS_DATA_READ_ALL:M:E:S:I\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_REFERENCES_WRITES\n"
"PRESET,PAPI_L3_DCW,NOT_DERIVED,L3_WRITES_DATA_WRITE_ALL:M:E:S:I\n"
"PRESET,PAPI_L3_ICH,NOT_DERIVED,L3_READS_DINST_FETCH_HIT:M:E:S:I\n"
"PRESET,PAPI_L3_ICR,NOT_DERIVED,L3_READS_INST_FETCH_ALL:M:E:S:I\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,L3_REFERENCES\n"
"PRESET,PAPI_L3_TCR,NOT_DERIVED,L3_READS_ALL_ALL:M:E:S:I\n"
"PRESET,PAPI_L3_TCW,NOT_DERIVED,L3_WRITES_ALL_ALL:M:E:S:I\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L2DTLB_MISSES\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES_FETCH_L2ITLB\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_EVENT\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,BR_MISPRED_DETAIL_ALL_CORRECT_PRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_OP_CYCLES_ALL\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_OPS_RETIRED\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,IA64_INST_RETIRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LOADS_RETIRED\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,STORES_RETIRED\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2I_DEMAND_READS\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,L3_READS_INST_FETCH_ALL:M:E:S:I\n"
"PRESET,PAPI_L1_TCR,NOT_DERIVED,L2I_READS_ALL_ALL\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2D_REFERENCES_WRITES\n"
"#\n"
"CPU,itanium2\n"
"#\n"
"PRESET,PAPI_CA_SNP,NOT_DERIVED,BUS_SNOOPS_SELF\n"
"PRESET,PAPI_CA_INV,DERIVED_ADD,BUS_MEM_READ_BRIL_SELF,BUS_MEM_READ_BIL_SELF\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,ITLB_MISSES_FETCH_L2ITLB,L2DTLB_MISSES\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,DISP_STALLED\n"
"PRESET,PAPI_STL_CCY,NOT_DERIVED,BACK_END_BUBBLE_ALL\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_DISPERSED\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,BE_EXE_BUBBLE_ALL\n"
"PRESET,PAPI_FP_STAL,NOT_DERIVED,BE_EXE_BUBBLE_FRALL\n"
"PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_DATA_REFERENCES_L2_DATA_READS,L2_INST_DEMAND_READS,L2_INST_PREFETCHES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,L2_INST_DEMAND_READS,L1D_READ_MISSES_ALL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_INST_DEMAND_READS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_READ_MISSES_ALL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_MISSES\n"
"PRESET,PAPI_L2_DCM, DERIVED_SUB,L2_MISSES,L3_READS_INST_FETCH_ALL\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,L3_READS_INST_FETCH_ALL\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_MISSES\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,L3_READS_INST_FETCH_MISS\n"
"PRESET,PAPI_L3_DCM, DERIVED_ADD,L3_READS_DATA_READ_MISS,L3_WRITES_DATA_WRITE_MISS\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,L3_READS_ALL_MISS\n"
"PRESET,PAPI_L3_STM,NOT_DERIVED,L3_WRITES_DATA_WRITE_MISS\n"
"PRESET,PAPI_L1_LDM,DERIVED_ADD,L1D_READ_MISSES_ALL,L2_INST_DEMAND_READS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L3_READS_ALL_ALL\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L3_WRITES_ALL_ALL\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_READS_SET1,L1D_READ_MISSES_ALL\n"
"PRESET,PAPI_L2_DCH,DERIVED_SUB,L2_DATA_REFERENCES_L2_ALL,L2_MISSES\n"
"PRESET,PAPI_L3_DCH,DERIVED_ADD,L3_READS_DATA_READ_HIT,L3_WRITES_DATA_WRITE_HIT\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_READS_SET1\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_DATA_REFERENCES_L2_ALL\n"
"PRESET,PAPI_L3_DCA,DERIVED_ADD,L3_READS_DATA_READ_ALL,L3_WRITES_DATA_WRITE_ALL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READS_SET1\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_DATA_REFERENCES_L2_DATA_READS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,L3_READS_DATA_READ_ALL\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_DATA_REFERENCES_L2_DATA_WRITES\n"
"PRESET,PAPI_L3_DCW,NOT_DERIVED,L3_WRITES_DATA_WRITE_ALL\n"
"PRESET,PAPI_L3_ICH,NOT_DERIVED,L3_READS_DINST_FETCH_HIT\n"
"PRESET,PAPI_L1_ICR,DERIVED_ADD,L1I_PREFETCHES,L1I_READS\n"
"PRESET,PAPI_L2_ICR,DERIVED_ADD,L2_INST_DEMAND_READS,L2_INST_PREFETCHES\n"
"PRESET,PAPI_L3_ICR,NOT_DERIVED,L3_READS_INST_FETCH_ALL\n"
"PRESET,PAPI_L1_ICA,DERIVED_ADD,L1I_PREFETCHES,L1I_READS\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_REFERENCES,L2_MISSES\n"
"PRESET,PAPI_L3_TCH,DERIVED_SUB,L3_REFERENCES,L3_MISSES\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_REFERENCES\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,L3_REFERENCES\n"
"PRESET,PAPI_L3_TCR,NOT_DERIVED,L3_READS_ALL_ALL\n"
"PRESET,PAPI_L3_TCW,NOT_DERIVED,L3_WRITES_ALL_ALL\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L2DTLB_MISSES\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES_FETCH_L2ITLB\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_EVENT\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,BR_MISPRED_DETAIL_ALL_CORRECT_PRED\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,BR_MISPRED_DETAIL_ALL_WRONG_PATH,BR_MISPRED_DETAIL_ALL_WRONG_TARGET\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_OPS_RETIRED\n"
"PRESET,PAPI_TOT_INS,DERIVED_ADD,IA64_INST_RETIRED,IA32_INST_RETIRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LOADS_RETIRED\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,STORES_RETIRED\n"
"PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_INST_DEMAND_READS\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,L3_READS_INST_FETCH_ALL\n"
"PRESET,PAPI_L1_TCR,DERIVED_ADD,L1D_READS_SET0,L1I_READS \n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_READS_SET0,L1I_READS \n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_DATA_REFERENCES_L2_DATA_WRITES\n"
"#\n"
"CPU,itanium\n"
"#\n"
"CPU,PPC970\n"
"#\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L2_DCR,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L2_DCH,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L1_ICM,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM\n"
"PRESET,PAPI_L2_ICA,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM\n"
"PRESET,PAPI_L2_ICH,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_MEM\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|-|,PM_FPU0_FIN,PM_FPU1_FIN,PM_FPU_FMA,PM_FPU_STF\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_CYC\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA\n"
"PRESET,PAPI_L1_DCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_REF_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L3_DCM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_MEM\n"
"#\n"
"CPU,PPC970MP\n"
"#\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L2_DCR,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L2_DCH,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"#PRESET,PAPI_L1_ICM,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM\n"
"#PRESET,PAPI_L2_ICA,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM\n"
"#PRESET,PAPI_L2_ICH,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_MEM\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|-|,PM_FPU0_FIN,PM_FPU1_FIN,PM_FPU_FMA,PM_FPU_STF \n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_CYC\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA\n"
"PRESET,PAPI_L1_DCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_REF_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L3_DCM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L3_LDM,NOT_DERIVED,PM_DATA_FROM_MEM\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_MEM\n"
"#\n"
"CPU,POWER5\n"
"#\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3\n"
"PRESET,PAPI_L3_ICM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN\n"
"PRESET,PAPI_FP_OPS,DERIVED_ADD,PM_FPU_1FLOP,PM_FPU_FMA,PM_FPU_FMA\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED_CR_TA\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"#\n"
"CPU,POWER5+\n"
"#\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3\n"
"PRESET,PAPI_L3_ICM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|N3|+|4|*|+|,PM_FPU_1FLOP,PM_FPU_FMA,PM_FPU_FSQRT,PM_FPU_FDIV\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED_CR_TA\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"#\n"
"CPU,POWER6\n"
"CPU,power6\n"
"#\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"PRESET,PAPI_INT_INS,DERIVED_ADD,PM_FXU0_FIN,PM_FXU1_FIN\n"
"# This definition comes from the (unreleased) IBM PM documentation\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|3|*|N1|N2|+|+|,PM_FPU_FSQRT_FDIV,PM_FPU_FLOP,PM_FPU_FMA\n"
"# The following counts SQRT and DIV as one FP event instead of 4\n"
"#PRESET,PAPI_FP_OPS,DERIVED_ADD,PM_FPU_FLOP,PM_FPU_FMA\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN\n"
"# It appears PM_CYC is not widely available\n"
"#PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_CYC\n"
"# PM_RUN_CYC is in every group; but it doesn't overflow :(\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_BR_MPRED\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"#\n"
"CPU,POWER7\n"
"CPU,power7\n"
"#\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,DERIVED_SUB,PM_ST_FIN,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCR,DERIVED_SUB,PM_LD_REF_L1,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_DCA,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-,PM_ST_FIN,PM_ST_MISS_L1,PM_LD_REF_L1,PM_LD_MISS_L1\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_L2_INST_MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_VSU_FMA\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"PRESET,PAPI_INT_INS,DERIVED_ADD,PM_FXU0_FIN,PM_FXU1_FIN\n"
"#\n"
"# We'd like to do a 1FLOP + 2*2FLOP + 4*4FLOP + 8*8FLOP + 16*16FLOP, but\n"
"# we run out of counters (we have 4, but need 5).  So for now, just assume\n"
"# that the vast majority of users won't be using the single precision\n"
"# vector FDIV and FSQRT instructions that would tick PM_VSU0_16FLOP.\n"
"#\n"
"#PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|N4|16|*|+|,PM_VSU_1FLOP,PM_VSU_2FLOP,PM_VSU_4FLOP,PM_VSU_8FLOP,PM_VSU0_16FLOP\n"
"#\n"
"#PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,PM_VSU_1FLOP,PM_VSU_2FLOP,PM_VSU_4FLOP,PM_VSU_8FLOP\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,PM_FLOP\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FLOP\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN\n"
"PRESET,PAPI_LD_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1\n"
"PRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN\n"
"#PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_BR_MPRED\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"#\n"
"CPU,POWER8\n"
"CPU,power8\n"
"#\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,DERIVED_SUB,PM_ST_FIN,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCR,DERIVED_SUB,PM_LD_REF_L1,PM_LD_MISS_L1\n"
"PRESET,PAPI_L1_DCA,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-,PM_ST_FIN,PM_ST_MISS_L1,PM_LD_REF_L1,PM_LD_MISS_L1\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"#n/aPRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS\n"
"#n/aPRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"#n/aPRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"#n/aPRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"#n/aPRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"#n/aPRESET,PAPI_L2_ICM,NOT_DERIVED,PM_L2_INST_MISS\n"
"#n/aPRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2\n"
"#n/aPRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"#n/aPRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS\n"
"#n/aPRESET,PAPI_FMA_INS,NOT_DERIVED,PM_VSU_FMA\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"#n/aPRESET,PAPI_INT_INS,DERIVED_ADD,PM_FXU0_FIN,PM_FXU1_FIN\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,PM_FLOP\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FLOP\n"
"PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|4|*|N1|8|*|N2|16|*|N3|32|*|+|+|+|,PM_VSU0_2FLOP,PM_VSU0_4FLOP,PM_VSU0_8FLOP,PM_VSU0_16FLOP\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|4|*|N1|8|*|N2|16|*|N3|32|*|+|+|+|,PM_VSU0_2FLOP,PM_VSU0_4FLOP,PM_VSU0_8FLOP,PM_VSU0_16FLOP\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN\n"
"#n/aPRESET,PAPI_LD_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1\n"
"#/naPRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN\n"
"#PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_CMPL\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_BR_MPRED_CMPL\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED_BR_CMPL\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_TAKEN_CMPL\n"
"PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND_CMPL\n"
"#n/aPRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"#\n"
"CPU,POWER9\n"
"CPU,power9\n"
"#\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1_ALT,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1_ALT\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCW,DERIVED_SUB,PM_ST_FIN,PM_ST_MISS_L1\n"
"PRESET,PAPI_L1_DCR,DERIVED_SUB,PM_LD_REF_L1,PM_LD_MISS_L1_ALT\n"
"#PRESET,PAPI_L1_DCA,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-,PM_ST_FIN,PM_ST_MISS_L1,PM_LD_REF_L1,PM_LD_MISS_L1_ALT\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_CMPL\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,PM_DATA_FROM_L2\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,PM_L2_ST_HIT\n"
"PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS\n"
"PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_L2_INST_MISS\n"
"PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2\n"
"PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS\n"
"PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3\n"
"PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FMA_CMPL\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,PM_FLOP_CMPL\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FLOP_CMPL\n"
"PRESET,PAPI_DP_OPS,NOT_DERIVED,PM_DP_QP_FLOP_CMPL\n"
"PRESET,PAPI_SP_OPS,NOT_DERIVED,PM_SP_FLOP_CMPL\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT\n"
"PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1\n"
"PRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_TAKEN_BR_MPRED_CMPL\n"
"PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED\n"
"PRESET,PAPI_BR_CN,DERIVED_SUB,PM_BR_CMPL,PM_BR_UNCOND\n"
"PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|,PM_BR_CMPL,PM_BR_TAKEN_CMPL\n"
"PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_CORECT_PRED_TAKEN_CMPL\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE\n"
"#\n"
"CPU,ultra12\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLE_CNT\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,DISPATCH0_IC_MISS\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,IC_REF\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,DC_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,DC_WR\n"
"PRESET,PAPI_MEM_RCY,NOT_DERIVED,LOAD_USE\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,EC_REF\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,DISPATCH0_MISPRED\n"
"PRESET,PAPI_L1_ICH,NOT_DERIVED,IC_HIT\n"
"PRESET,PAPI_L2_TCH,NOT_DERIVED,EC_HIT\n"
"PRESET,PAPI_L2_TCM,DERIVED_SUB,EC_REF,EC_HIT\n"
"#\n"
"CPU,ultra3\n"
"CPU,ultra3i\n"
"CPU,ultra3+\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLE_CNT\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,DISPATCH0_IC_MISS\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,IC_REF\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,DC_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,DC_WR\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,EC_REF\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,IU_STAT_BR_COUNT_TAKEN\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,IU_STAT_BR_COUNT_UNTAKEN\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,IU_STAT_BR_MISS_TAKEN,IU_STAT_BR_MISS_UNTAKEN\n"
"PRESET,PAPI_BR_INS,DERIVED_ADD,IU_STAT_BR_COUNT_TAKEN,IU_STAT_BR_COUNT_UNTAKEN\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,EC_MISSES\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS\n"
"#\n"
"CPU,ultra4+\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLE_CNT\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,DISPATCH0_IC_MISS\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,IC_REF\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,DC_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,DC_WR\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_REF\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,IU_STAT_BR_COUNT_TAKEN\n"
"PRESET,PAPI_BR_NTK,NOT_DERIVED,IU_STAT_BR_COUNT_UNTAKEN\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,IU_STAT_BR_MISS_TAKEN,IU_STAT_BR_MISS_UNTAKEN\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS\n"
"PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_MISS\n"
"#\n"
"CPU,niagara\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FP_INSTR_CNT\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,IC_MISS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DC_MISS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS\n"
"#\n"
"CPU,niagara2\n"
"#\n"
"CPU,Cell\n"
"#\n"
"PRESET,PAPI_TOT_INS,DERIVED_POSTFIX,N0|N1|+|2|*|,PPC_INST_COMMIT_TH0,PPC_INST_COMMIT_TH1\n"
"#PRESET,PAPI_L1_DCM,DERIVED_ADD,L1_DCACHE_MISS_TH0,L1_DCACHE_MISS_TH1 where's TH1??\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1_DCACHE_MISS_TH0\n"
"PRESET,PAPI_L2_TCH,NOT_DERIVED,L2_CACHE_HIT\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_LD_MISS\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2_ST_MISS\n"
"PRESET,PAPI_BR_MSP,DERIVED_ADD,BRANCH_FLUSH_TH0,BRANCH_FLUSH_TH1\n"
"PRESET,PAPI_BR_INS,DERIVED_ADD,BRANCH_COMMIT_TH0,BRANCH_COMMIT_TH1\n"
"#\n"
"CPU,arm_1176\n"
"#\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE_MISS\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,IBUF_STALL\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_EXEC\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISPREDICT\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_EXEC\n"
"PRESET,PAPI_L1_DCH,NOT_DERIVED,DCACHE_HIT\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_MISS\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"#\n"
"CPU,arm_ac7\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_READS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_WRITES\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,EXCEPTION_TAKEN\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,SW_CHANGE_PC\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_MEM_ACCESS\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE_ACCESS\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,EXTERNAL_MEMORY_REQUEST\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1I_TLB_REFILL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1D_TLB_REFILL\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"#\n"
"CPU,arm_ac8\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_EXECUTED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PC_WRITE\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PC_BRANCH_MIS_PRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,DREAD\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,DWRITE\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_REFILL\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1_INST\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,IFETCH_MISS\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_ACCESS\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS\n"
"PRESET,PAPI_BR_TKN,NOT_DERIVED,PC_BRANCH_EXECUTED\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,CYCLES_INST_STALL\n"
"#\n"
"CPU,arm_ac9\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_OUT_OF_RENAME_STAGE\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,MAIN_UNIT_EXECUTED_INST\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,EXT_INTERRUPTS\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FP_EXECUTED_INST\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,NEON_EXECUTED_INST\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PC_WRITE\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PC_BRANCH_MIS_PRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,DREAD\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,DWRITE\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_REFILL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,IFETCH_MISS\n"
"#\n"
"CPU,arm_ac15\n"
"CPU,arm_ac57\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_SPEC_EXEC\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_READ_REFILL,L1D_WRITE_REFILL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READ_ACCESS\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_WRITE_ACCESS\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE_ACCESS\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL\n"
"#####################\n"
"# ARM Cortex A53    #\n"
"#####################\n"
"# These are based entirely on libpfm4 event table\n"
"# They have not been tested on real hardware\n"
"CPU,arm_ac53\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_PRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE_ACCESS\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_CACHE_REFILL\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LD_RETIRED\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,ST_RETIRED\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE_ACCESS\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1I_TLB_REFILL\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L1D_TLB_REFILL\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,EXCEPTION_TAKEN\n"
"#\n"
"CPU,qcom_krait\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_EXECUTED\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,INSTR_EXECUTED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PC_WRITE\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PC_BRANCH_MIS_PRED\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE_ACCESS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"# Will be supported eventually\n"
"#PRESET,PAPI_L1_ICA,NOT_DERIVED,KRAIT_L1_ICACHE_ACCESS\n"
"#PRESET,PAPI_L1_ICM,NOT_DERIVED,KRAIT_L1_ICACHE_MISS\n"
"#\n"
"CPU,arm_xgene\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READ_ACCESS\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_WRITE_ACCESS\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE_ACCESS\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL\n"
"#####################\n"
"# ARM ThunderX2     #\n"
"#####################\n"
"CPU,arm_thunderx2\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,ASE_SPEC\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LD_RETIRED\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,ST_RETIRED\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_CACHE_RD,L1D_CACHE_WR\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD\n"
"#########################\n"
"# ARM Fujitsu A64FX     #\n"
"#########################\n"
"CPU,arm_a64fx\n"
"#\n"
"PRESET,PAPI_PRF_DM,DERIVED_SUB,L2D_CACHE_REFILL_PRF,L2D_CACHE_MIBMCH_PRF\n"
"PRESET,PAPI_MEM_SCY,NOT_DERIVED,LD_COMP_WAIT_L2_MISS\n"
"PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND\n"
"PRESET,PAPI_STL_CCY,NOT_DERIVED,0INST_COMMIT\n"
"PRESET,PAPI_FUL_CCY,DERIVED_SUB,CPU_CYCLES,0INST_COMMIT,1INST_COMMIT,2INST_COMMIT,3INST_COMMIT\n"
"PRESET,PAPI_BRU_IDL,NOT_DERIVED,BR_COMP_WAIT\n"
"PRESET,PAPI_FXU_IDL,DERIVED_SUB,EU_COMP_WAIT,FL_COMP_WAIT\n"
"PRESET,PAPI_FPU_IDL,NOT_DERIVED,FL_COMP_WAIT\n"
"PRESET,PAPI_LSU_IDL,NOT_DERIVED,LD_COMP_WAIT\n"
"PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED\n"
"PRESET,PAPI_FMA_INS,NOT_DERIVED,FP_FMA_SPEC\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FP_SPEC\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND\n"
"PRESET,PAPI_LST_INS,NOT_DERIVED,LDST_SPEC\n"
"PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC\n"
"#PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE\n"
"#PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"#PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE\n"
"#PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE\n"
"PRESET,PAPI_L2_DCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|+|,L2D_CACHE,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF\n"
"PRESET,PAPI_L2_DCM,DERIVED_SUB,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE\n"
"PRESET,PAPI_L2_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|+|,L2D_CACHE,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF\n"
"PRESET,PAPI_L2_TCM,DERIVED_SUB,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L2I_TLB_REFILL\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,L2D_TLB_REFILL,L2I_TLB_REFILL\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SCALE_OPS_SPEC,FP_FIXED_OPS_SPEC\n"
"PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SP_SCALE_OPS_SPEC,FP_SP_FIXED_OPS_SPEC\n"
"PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_DP_SCALE_OPS_SPEC,FP_DP_FIXED_OPS_SPEC\n"
"#########################\n"
"# ARM Neoverse N1       #\n"
"#########################\n"
"CPU,arm_n1\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,ASE_SPEC\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD\n"
"PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND\n"
"PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ\n"
"PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL\n"
"#########################\n"
"# ARM Neoverse N2       #\n"
"#########################\n"
"CPU,arm_n2\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC\n"
"PRESET,PAPI_VEC_INS,DERIVED_ADD,SVE_INST_SPEC,ASE_INST_SPEC\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD\n"
"PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND\n"
"PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ\n"
"PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL\n"
"#########################\n"
"# ARM Neoverse V1       #\n"
"#########################\n"
"CPU,arm_v1\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC\n"
"PRESET,PAPI_VEC_INS,DERIVED_ADD,SVE_INST_SPEC,ASE_INST_SPEC\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD\n"
"PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND\n"
"PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ\n"
"PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL\n"
"#########################\n"
"# ARM Neoverse V2       #\n"
"#########################\n"
"CPU,arm_v2\n"
"#\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,DP_SPEC\n"
"#NOT_IMPLEMENTED,PAPI_TOT_IIS,Instructions issued\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_REF_CYC,NOT_DERIVED,CNT_CYCLES\n"
"PRESET,PAPI_STL_CCY,NOT_DERIVED,STALL\n"
"#NOT_IMPLEMENTED,PAPI_FUL_CCY,Cycles with maximum instructions completed\n"
"#NOT_IMPLEMENTED,PAPI_FUL_ICY,Cycles with maximum instruction issue\n"
"#NOT_IMPLEMENTED,PAPI_FXU_IDL,Cycles integer units are idle\n"
"#NOT_IMPLEMENTED,PAPI_LSU_IDL,Cycles load/store units are idle\n"
"#NOT_IMPLEMENTED,PAPI_MEM_RCY,Cycles Stalled Waiting for memory Reads\n"
"#NOT_IMPLEMENTED,PAPI_MEM_SCY,Cycles Stalled Waiting for memory accesses\n"
"#NOT_IMPLEMENTED,PAPI_MEM_WCY,Cycles Stalled Waiting for memory writes\n"
"#NOT_IMPLEMENTED,PAPI_FP_STAL,Cycles the FP unit(s) are stalled\n"
"#NOT_IMPLEMENTED,PAPI_FPU_IDL,Cycles floating point units are idle\n"
"#NOT_IMPLEMENTED,PAPI_BRU_IDL,Cycles branch units are idle\n"
"PRESET,PAPI_STL_ICY,NOT_DERIVED,STALL\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND\n"
"PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_SCALE_OPS_SPEC,FP_FIXED_OPS_SPEC\n"
"#NOT_IMPLEMENTED,PAPI_SP_OPS,Floating point operations; optimized to count scaled single precision vector operations\n"
"#NOT_IMPLEMENTED,PAPI_DP_OPS,Floating point operations; optimized to count scaled double precision vector operations\n"
"PRESET,PAPI_FP_INS,DERIVED_ADD,FP_HP_SPEC,FP_SP_SPEC,FP_DP_SPEC\n"
"#NOT_IMPLEMENTED,PAPI_FAD_INS,Floating point add instructions\n"
"#NOT_IMPLEMENTED,PAPI_FDV_INS,Floating point divide instructions\n"
"#NOT_IMPLEMENTED,PAPI_FMA_INS,FMA instructions completed\n"
"#NOT_IMPLEMENTED,PAPI_FML_INS,Floating point multiply instructions\n"
"#NOT_IMPLEMENTED,PAPI_FNV_INS,Floating point inverse instructions\n"
"#NOT_IMPLEMENTED,PAPI_FSQ_INS,Floating point square root instructions\n"
"PRESET,PAPI_VEC_INS,DERIVED_ADD,SVE_INST_SPEC,ASE_INST_SPEC\n"
"#NOT_IMPLEMENTED,PAPI_VEC_DP,Double precision vector/SIMD instructions\n"
"#NOT_IMPLEMENTED,PAPI_VEC_SP,Single precision vector/SIMD instructions\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED\n"
"#NOT_IMPLEMENTED,PAPI_BR_CN,Conditional branch instructions\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_RETIRED,BR_MIS_PRED_RETIRED\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED_RETIRED\n"
"#NOT_IMPLEMENTED,PAPI_BR_NTK,Conditional branch instructions not taken\n"
"#NOT_IMPLEMENTED,PAPI_BR_TKN,Conditional branch instructions taken\n"
"#NOT_IMPLEMENTED,PAPI_BR_UCN,Unconditional branch instructions\n"
"#NOT_IMPLEMENTED,PAPI_BTAC_M,Branch target address cache misses\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE\n"
"PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL\n"
"#NOT_IMPLEMENTED,PAPI_L1_ICR,Level 1 instruction cache reads\n"
"#NOT_IMPLEMENTED,PAPI_L1_ICW,Level 1 instruction cache writes\n"
"#NOT_IMPLEMENTED,PAPI_L1_LDM,Level 1 load misses\n"
"#NOT_IMPLEMENTED,PAPI_L1_STM,Level 1 store misses\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE_ACCESS\n"
"PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE_ACCESS,L1I_CACHE_REFILL\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL\n"
"#NOT_IMPLEMENTED,PAPI_L1_TCR,Level 1 total cache reads\n"
"#NOT_IMPLEMENTED,PAPI_L1_TCW,Level 1 total cache writes\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE\n"
"PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE\n"
"PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD\n"
"PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR\n"
"PRESET,PAPI_L2_DCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD\n"
"PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_CACHE_REFILL_WR\n"
"#NOT_IMPLEMENTED,PAPI_L2_ICA,Level 2 instruction cache accesses\n"
"#NOT_IMPLEMENTED,PAPI_L2_ICH,Level 2 instruction cache hits\n"
"#NOT_IMPLEMENTED,PAPI_L2_ICM,Level 2 instruction cache misses\n"
"#NOT_IMPLEMENTED,PAPI_L2_ICR,Level 2 instruction cache reads\n"
"#NOT_IMPLEMENTED,PAPI_L2_ICW,Level 2 instruction cache writes\n"
"PRESET,PAPI_L2_TCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2D_CACHE_REFILL\n"
"PRESET,PAPI_L2_TCR,NOT_DERIVED,L2D_CACHE_RD\n"
"PRESET,PAPI_L2_TCW,NOT_DERIVED,L2D_CACHE_WR\n"
"PRESET,PAPI_L3_TCA,NOT_DERIVED,L3D_CACHE\n"
"PRESET,PAPI_L3_DCA,NOT_DERIVED,L3D_CACHE\n"
"#NOT_IMPLEMENTED,PAPI_L3_DCH,Level 3 data cache hits\n"
"PRESET,PAPI_L3_DCM,NOT_DERIVED,L3D_CACHE_REFILL\n"
"#NOT_IMPLEMENTED,PAPI_L3_DCR,Level 3 data cache reads\n"
"#NOT_IMPLEMENTED,PAPI_L3_DCW,Level 3 data cache writes\n"
"#NOT_IMPLEMENTED,PAPI_L3_ICA,Level 3 instruction cache accesses\n"
"#NOT_IMPLEMENTED,PAPI_L3_ICH,Level 3 instruction cache hits\n"
"#NOT_IMPLEMENTED,PAPI_L3_ICM,Level 3 instruction cache misses\n"
"#NOT_IMPLEMENTED,PAPI_L3_ICR,Level 3 instruction cache reads\n"
"#NOT_IMPLEMENTED,PAPI_L3_ICW,Level 3 instruction cache writes\n"
"#NOT_IMPLEMENTED,PAPI_L3_LDM,Level 3 load misses\n"
"#NOT_IMPLEMENTED,PAPI_L3_STM,Level 3 store misses\n"
"#NOT_IMPLEMENTED,PAPI_L3_TCH,Level 3 total cache hits\n"
"#NOT_IMPLEMENTED,PAPI_L3_TCM,Level 3 cache misses\n"
"#NOT_IMPLEMENTED,PAPI_L3_TCR,Level 3 total cache reads\n"
"#NOT_IMPLEMENTED,PAPI_L3_TCW,Level 3 total cache writes\n"
"PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ\n"
"PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,L1I_TLB_REFILL\n"
"#NOT_IMPLEMENTED,PAPI_TLB_SD,Translation lookaside buffer shootdowns\n"
"PRESET,PAPI_TLB_TL,DERIVED_ADD,L1D_TLB_REFILL,L2D_TLB_REFILL\n"
"#NOT_IMPLEMENTED,PAPI_CA_CLN,Requests for exclusive access to clean cache line\n"
"#NOT_IMPLEMENTED,PAPI_CA_INV,Requests for cache line invalidation\n"
"#NOT_IMPLEMENTED,PAPI_CA_ITV,Requests for cache line intervention\n"
"#NOT_IMPLEMENTED,PAPI_CA_SHR,Requests for exclusive access to shared cache line\n"
"#NOT_IMPLEMENTED,PAPI_CA_SNP,Requests for a snoop\n"
"#NOT_IMPLEMENTED,PAPI_CSR_FAL,Failed store conditional instructions\n"
"#NOT_IMPLEMENTED,PAPI_CSR_SUC,Successful store conditional instructions\n"
"#NOT_IMPLEMENTED,PAPI_CSR_TOT,Total store conditional instructions\n"
"#NOT_IMPLEMENTED,PAPI_PRF_DM,Data prefetch cache misses\n"
"#\n"
"CPU,mips_74k\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE_ACCESSES\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE_MISSES\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESSES\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_MISSES\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,DCACHE_ACCESSES,ICACHE_ACCESSES\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,ICACHE_MISSES,DCACHE_MISSES\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_CACHE_ACCESSES\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISSES\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,FPU_INSNS\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,INTEGER_INSNS\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,LOAD_INSNS\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,STORE_INSNS\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,JTLB_INSN_MISSES\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,JTLB_DATA_MISSES\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,COND_BRANCH_INSNS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_INSNS\n"
"PRESET,PAPI_CSR_FAL,NOT_DERIVED,FAILED_SC_INSNS\n"
"PRESET,PAPI_CSR_TOT,NOT_DERIVED,SC_INSNS\n"
"PRESET,PAPI_FUL_ICY,NOT_DERIVED,DUAL_ISSUE_CYCLES\n"
"PRESET,PAPI_STL_CCY,NOT_DERIVED,NO_INSN_CYCLES\n"
"PRESET,PAPI_FUL_CCY,NOT_DERIVED,TWO_INSNS_CYCLES\n"
"#\n"
"CPU,MIPSICE9A\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,CPU_INSEXEC\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,CPU_INSFETCH\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,CPU_LOAD\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,CPU_STORE\n"
"PRESET,PAPI_CSR_FAL,NOT_DERIVED,CPU_SCFAIL\n"
"PRESET,PAPI_CSR_TOT,NOT_DERIVED,CPU_SC\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,CPU_FLOAT\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,CPU_BRANCH\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,CPU_ITLBMISS\n"
"PRESET,PAPI_TLB_TL,NOT_DERIVED,CPU_TLBTRAP\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,CPU_DTLBMISS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,CPU_MISPRED\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,CPU_ICMISS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,CPU_DCMISS\n"
"PRESET,PAPI_MEM_SCY,NOT_DERIVED,CPU_MSTALL\n"
"PRESET,PAPI_FUL_ICY,NOT_DERIVED,CPU_INSDUAL\n"
"#\n"
"CPU,MIPSICE9B\n"
"#\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,CPU_INSEXEC\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,CPU_INSFETCH\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,CPU_LOAD\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,CPU_STORE\n"
"PRESET,PAPI_CSR_FAL,NOT_DERIVED,CPU_SCFAIL\n"
"PRESET,PAPI_CSR_TOT,NOT_DERIVED,CPU_SC\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,CPU_FPARITH\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,CPU_BRANCH\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,CPU_ITLBMISS\n"
"PRESET,PAPI_TLB_TL,NOT_DERIVED,CPU_TLBTRAP\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,CPU_DTLBMISS\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,CPU_MISPRED\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,CPU_ICMISS\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,CPU_DCMISS\n"
"PRESET,PAPI_MEM_SCY,NOT_DERIVED,CPU_MSTALL\n"
"PRESET,PAPI_FUL_ICY,NOT_DERIVED,CPU_INSDUAL\n"
"PRESET,PAPI_L2_TCM,NOT_DERIVED,CPU_L2MISSALL\n"
"PRESET,PAPI_L2_TCA,NOT_DERIVED,CPU_L2REQ\n"
"#\n"
"CPU,BGQ\n"
"#\n"
"# Conditional Branching\n"
"PRESET,PAPI_BR_CN,NOT_DERIVED,PEVT_INST_XU_BRC\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,PEVT_XU_BR_COMMIT\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,PEVT_XU_BR_MISPRED_COMMIT\n"
"PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|N2|-|,PEVT_INST_XU_BRC,PEVT_XU_BR_TAKEN_COMMIT,PEVT_INST_XU_BRU\n"
"#PRESET,PAPI_BR_NTK,DERIVED_SUB,PEVT_INST_XU_BRC,PEVT_XU_BR_TAKEN_COMMIT # Not sure if branches_taken includes unconditional branches as well\n"
"PRESET,PAPI_BR_PRC,DERIVED_SUB,PEVT_INST_XU_BRC,PEVT_XU_BR_MISPRED_COMMIT\n"
"PRESET,PAPI_BR_TKN,DERIVED_SUB,PEVT_XU_BR_TAKEN_COMMIT,PEVT_INST_XU_BRU\n"
"#PRESET,PAPI_BR_TKN,NOT_DERIVED,PEVT_XU_BR_TAKEN_COMMIT # Not sure if branches_taken includes unconditional branches as well\n"
"PRESET,PAPI_BR_UCN,NOT_DERIVED,PEVT_INST_XU_BRU\n"
"PRESET,PAPI_BTAC_M,NOT_DERIVED,PEVT_XU_BR_TARG_ADDR_MISPRED_COMMIT\n"
"#\n"
"# Cache Requests\n"
"# none so far\n"
"#\n"
"# Conditional Store\n"
"PRESET,PAPI_CSR_FAL,NOT_DERIVED,PEVT_XU_STCX_FAIL\n"
"PRESET,PAPI_CSR_SUC,DERIVED_SUB,PEVT_LSU_COMMIT_STCX,PEVT_XU_STCX_FAIL\n"
"PRESET,PAPI_CSR_TOT,NOT_DERIVED,PEVT_LSU_COMMIT_STCX\n"
"#\n"
"# Floating Point Operations\n"
"PRESET,PAPI_FAD_INS,DERIVED_ADD,PEVT_INST_QFPU_FADD,PEVT_INST_QFPU_QADD\n"
"PRESET,PAPI_FDV_INS,NOT_DERIVED,PEVT_INST_QFPU_FDIV\n"
"PRESET,PAPI_FMA_INS,DERIVED_ADD,PEVT_INST_QFPU_FMA,PEVT_INST_QFPU_QMA\n"
"PRESET,PAPI_FML_INS,DERIVED_ADD,PEVT_INST_QFPU_FMUL,PEVT_INST_QFPU_QMUL\n"
"PRESET,PAPI_FP_INS,NOT_DERIVED,PEVT_INST_QFPU_ALL\n"
"# TODO: for PAPI_FP_OPS it's either FPGRP1 or FPGRP2. Needs to be tested\n"
"PRESET,PAPI_FP_OPS,NOT_DERIVED,PEVT_INST_QFPU_FPGRP1\n"
"# PRESET,PAPI_FP_OPS,NOT_DERIVED,PEVT_INST_QFPU_FPGRP2\n"
"PRESET,PAPI_FP_STAL,NOT_DERIVED,PEVT_IU_AXU_FXU_DEP_HIT_CYC\n"
"PRESET,PAPI_FSQ_INS,NOT_DERIVED,PEVT_INST_QFPU_FSQ\n"
"#\n"
"# Instruction Counting\n"
"#PRESET,PAPI_FUL_ICY,NOT_DERIVED,PEVT_IU_TWO_INSTR_ISSUE\n"
"PRESET,PAPI_FXU_IDL,NOT_DERIVED,PEVT_AXU_IDLE\n"
"PRESET,PAPI_HW_INT,NOT_DERIVED,PEVT_XU_INTS_TAKEN\n"
"PRESET,PAPI_INT_INS,NOT_DERIVED,PEVT_INST_XU_GRP_MASK:837800,NOTE,'UPC_P_XU_OGRP_IADD|UPC_P_XU_OGRP_IMUL|UPC_P_XU_OGRP_IDIV|UPC_P_XU_OGRP_ICMP|UPC_P_XU_OGRP_IMOV|UPC_P_XU_OGRP_ILOG|UPC_P_XU_OGRP_BITS'\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PEVT_CYCLES\n"
"PRESET,PAPI_TOT_IIS,NOT_DERIVED,PEVT_IU_TOT_ISSUE_COUNT\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,PEVT_INST_ALL\n"
"PRESET,PAPI_VEC_INS,DERIVED_ADD,PEVT_INST_QFPU_GRP_MASK:3FE,PEVT_INST_XU_GRP_MASK:3000000,NOTE,'UPC_P_AXU_OGRP_QADD|UPC_P_AXU_OGRP_QCMP|UPC_P_AXU_OGRP_QCVT|UPC_P_AXU_OGRP_QMA|UPC_P_AXU_OGRP_QMOV|UPC_P_AXU_OGRP_QMUL|UPC_P_AXU_OGRP_QOTH|UPC_P_AXU_OGRP_QRES|UPC_P_AXU_OGRP_QRND + UPC_P_XU_OGRP_QLD|UPC_P_XU_OGRP_QST'\n"
"#\n"
"# Cache Access\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PEVT_LSU_COMMIT_LD_MISSES,PEVT_LSU_COMMIT_ST_MISSES\n"
"PRESET,PAPI_L1_DCR,NOT_DERIVED,PEVT_LSU_COMMIT_CACHEABLE_LDS\n"
"PRESET,PAPI_L1_DCW,NOT_DERIVED,PEVT_LSU_COMMIT_STS\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,PEVT_IU_IL1_MISS\n"
"PRESET,PAPI_L1_ICR,NOT_DERIVED,PEVT_IU_ICACHE_FETCH\n"
"PRESET,PAPI_L1_LDM,DERIVED_ADD,PEVT_IU_IL1_MISS,PEVT_LSU_COMMIT_LD_MISSES\n"
"PRESET,PAPI_L1_STM,NOT_DERIVED,PEVT_LSU_COMMIT_ST_MISSES\n"
"#PRESET,PAPI_L2_TCH,NOT_DERIVED,PEVT_L2_HITS\n"
"#PRESET,PAPI_L2_TCM,NOT_DERIVED,PEVT_L2_MISSES\n"
"#\n"
"# Data Access\n"
"PRESET,PAPI_LD_INS,DERIVED_ADD,PEVT_LSU_COMMIT_CACHEABLE_LDS,PEVT_LSU_COMMIT_CACHE_INHIB_LD_MISSES\n"
"# may not be possible\n"
"#PRESET,PAPI_LST_INS,DERIVED_POSTFIX,N0|N1|+|N2|+|,PEVT_LSU_COMMIT_CACHEABLE_LDS,PEVT_LSU_COMMIT_CACHE_INHIB_LD_MISSES,PEVT_LSU_COMMIT_STS\n"
"#PRESET,PAPI_MEM_RCY,NOT_DERIVED,PEVT_IU_RAW_DEP_HIT_CYC\n"
"#PRESET,PAPI_PRF_DM,NOT_DERIVED,PEVT_LSU_COMMIT_DCBT_MISSES\n"
"PRESET,PAPI_RES_STL,NOT_DERIVED,PEVT_IU_IS1_STALL_CYC\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,PEVT_LSU_COMMIT_STS\n"
"PRESET,PAPI_STL_CCY,DERIVED_SUB,PEVT_CYCLES,PEVT_INST_ALL\n"
"PRESET,PAPI_STL_ICY,DERIVED_SUB,PEVT_CYCLES,PEVT_IU_TOT_ISSUE_COUNT\n"
"PRESET,PAPI_SYC_INS,NOT_DERIVED,PEVT_INST_XU_SYNC\n"
"#\n"
"# TLB Operations\n"
"PRESET,PAPI_TLB_DM,DERIVED_ADD,PEVT_MMU_TLB_MISS_DIRECT_DERAT,PEVT_MMU_TLB_MISS_INDIR_DERAT\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,PEVT_MMU_TLB_MISS_DIRECT_DERAT\n"
"PRESET,PAPI_TLB_SD,NOT_DERIVED,PEVT_MMU_TLBIVAX_SNOOP_TOT\n"
"PRESET,PAPI_TLB_TL,DERIVED_POSTFIX,N0|N1|+|N2|+|,PEVT_MMU_TLB_MISS_DIRECT_DERAT,PEVT_MMU_TLB_MISS_INDIR_DERAT,PEVT_MMU_TLB_MISS_DIRECT_IERAT\n"
"#################################\n"
"# Intel MIC / Xeon-Phi / Knights Corner\n"
"CPU,knc\n"
"#\n"
"PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCHES:mg=1:mh=1\n"
"PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCHES_MISPREDICTED:mg=1:mh=1\n"
"PRESET,PAPI_L1_ICM,NOT_DERIVED,CODE_CACHE_MISS:mg=1:mh=1\n"
"PRESET,PAPI_TLB_IM,NOT_DERIVED,CODE_PAGE_WALK:mg=1:mh=1\n"
"PRESET,PAPI_L1_ICA,NOT_DERIVED,CODE_READ:mg=1:mh=1\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:mg=1:mh=1\n"
"PRESET,PAPI_TLB_DM,NOT_DERIVED,DATA_PAGE_WALK:mg=1:mh=1\n"
"PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_READ:mg=1:mh=1\n"
"PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_WRITE:mg=1:mh=1\n"
"PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_READ_MISS_OR_WRITE_MISS:mg=1:mh=1\n"
"PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_READ_OR_WRITE:mg=1:mh=1\n"
"PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_EXECUTED:mg=1:mh=1\n"
"PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_READ_MISS:mg=1:mh=1\n"
"PRESET,PAPI_VEC_INS,NOT_DERIVED,VPU_INSTRUCTIONS_EXECUTED:mg=1:mh=1\n"
"CPU,BGP\n"
"# The following PAPI presets are accurate for all application nodes\n"
"# using SMP processing for zero or one threads.  The appropriate native\n"
"# hardware counters mapped to the following PAPI preset counters are\n"
"# only collected for processors 0 and 1 for each physical compute card.\n"
"# The values are correct for other processing mode/thread combinations,\n"
"# but only for those application nodes running on processor 0 or 1 of\n"
"# a given physical compute card.\n"
"PRESET,PAPI_L1_DCM,DERIVED_ADD,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS\n"
"PRESET,PAPI_L1_ICM,DERIVED_ADD,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS\n"
"PRESET,PAPI_L1_TCM,DERIVED_ADD,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS\n"
"PRESET,PAPI_CA_SNP,DERIVED_ADD,PNE_BGP_PU0_L1_INVALIDATION_REQUESTS,PNE_BGP_PU1_L1_INVALIDATION_REQUESTS\n"
"PRESET,PAPI_PRF_DM,DERIVED_ADD,NE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS\n"
"PRESET,PAPI_FMA_INS,DERIVED_ADD,PNE_BGP_PU0_FPU_FMA_2,PNE_BGP_PU1_FPU_FMA_2,PNE_BGP_PU0_FPU_FMA_4,PNE_BGP_PU1_FPU_FMA_4\n"
"PRESET,PAPI_FP_INS,DERIVED_ADD,PNE_BGP_PU0_FPU_ADD_SUB_1,PNE_BGP_PU1_FPU_ADD_SUB_1,PNE_BGP_PU0_FPU_MULT_1,PNE_BGP_PU1_FPU_MULT_1,PNE_BGP_PU0_FPU_FMA_2,PNE_BGP_PU1_FPU_FMA_2,PNE_BGP_PU0_FPU_DIV_1,PNE_BGP_PU1_FPU_DIV_1,PNE_BGP_PU0_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU0_FPU_ADD_SUB_2,PNE_BGP_PU1_FPU_ADD_SUB_2,PNE_BGP_PU0_FPU_MULT_2,PNE_BGP_PU1_FPU_MULT_2,PNE_BGP_PU0_FPU_FMA_4,PNE_BGP_PU1_FPU_FMA_4,PNE_BGP_PU0_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS\n"
"PRESET,PAPI_LD_INS,DERIVED_ADD,PNE_BGP_PU0_DATA_LOADS,PNE_BGP_PU1_DATA_LOADS\n"
"PRESET,PAPI_SR_INS,DERIVED_ADD,PNE_BGP_PU0_DATA_STORES,PNE_BGP_PU1_DATA_STORES\n"
"PRESET,PAPI_LST_INS,DERIVED_ADD,PNE_BGP_PU0_DATA_LOADS,PNE_BGP_PU1_DATA_LOADS,PNE_BGP_PU0_DATA_STORES,PNE_BGP_PU1_DATA_STORES\n"
"PRESET,PAPI_L1_DCH,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT\n"
"PRESET,PAPI_L1_DCA,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS\n"
"PRESET,PAPI_L1_DCR,DERIVED_ADD,PNE_BGP_PU0_DATA_LOADS,PNE_BGP_PU1_DATA_LOADS\n"
"PRESET,PAPI_L1_ICH,DERIVED_ADD,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT\n"
"PRESET,PAPI_L1_ICA,DERIVED_ADD,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS\n"
"PRESET,PAPI_L1_ICR,DERIVED_ADD,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS\n"
"PRESET,PAPI_L1_ICW,DERIVED_ADD,PNE_BGP_PU0_ICACHE_LINEFILLINPROG,PNE_BGP_PU1_ICACHE_LINEFILLINPROG\n"
"PRESET,PAPI_L1_TCH, DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,\n"
"PRESET,PAPI_L1_TCA,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS,PNE_BGP_PU0_DCACHE_LINEFILLINPROG,PNE_BGP_PU1_DCACHE_LINEFILLINPROG\n"
"PRESET,PAPI_L1_TCR,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS\n"
"PRESET,PAPI_L1_TCW,DERIVED_ADD,PNE_BGP_PU0_DCACHE_LINEFILLINPROG,PNE_BGP_PU1_DCACHE_LINEFILLINPROG,PNE_BGP_PU0_ICACHE_LINEFILLINPROG,PNE_BGP_PU1_ICACHE_LINEFILLINPROG\n"
"PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|+|N4|2|*|+|N5|2|*|+|N6|13|*|+|N7|13|*|+|N8|+|N9|+|N10|2|*|+|N11|2|*|+|N12|2|*|+|N13|2|*|+|N14|4|*|+|N15|4|*|+|N16|2|*|+|N17|2|*|+|,PNE_BGP_PU0_FPU_ADD_SUB_1,PNE_BGP_PU1_FPU_ADD_SUB_1,PNE_BGP_PU0_FPU_MULT_1,PNE_BGP_PU1_FPU_MULT_1,PNE_BGP_PU0_FPU_FMA_2,PNE_BGP_PU1_FPU_FMA_2,PNE_BGP_PU0_FPU_DIV_1,PNE_BGP_PU1_FPU_DIV_1,PNE_BGP_PU0_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU0_FPU_ADD_SUB_2,PNE_BGP_PU1_FPU_ADD_SUB_2,PNE_BGP_PU0_FPU_MULT_2,PNE_BGP_PU1_FPU_MULT_2,PNE_BGP_PU0_FPU_FMA_4,PNE_BGP_PU1_FPU_FMA_4,PNE_BGP_PU0_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS\n"
"# The following PAPI presets are accurate for any processing mode of \n"
"# SMP, DUAL, or VN for all application nodes.  The appropriate native \n"
"# hardware counters used for the following PAPI preset counters are\n"
"# collected for all four processors for each physical compute card.\n"
"PRESET,PAPI_L2_DCM,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|+|N4|-|N5|-|N6|-|N7|-|,PNE_BGP_PU0_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU1_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU2_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU3_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU0_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU1_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU2_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU3_L2_PREFETCH_HITS_IN_STREAM\n"
"PRESET,PAPI_L3_LDM,DERIVED_ADD,PNE_BGP_L3_M0_RD0_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_RD0_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD0_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD0_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_RD1_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_RD1_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD1_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD1_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_R2_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_R2_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_R2_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_R2_DIR1_MISS_OR_LOCKDOWN\n"
"# NOTE:  This value is for the time the counters are active,\n"
"# and not for the total cycles for the job.\n"
"PRESET,PAPI_TOT_CYC,NOT_DERIVED,PNE_BGP_MISC_ELAPSED_TIME\n"
"PRESET,PAPI_L2_DCH,DERIVED_ADD,PNE_BGP_PU0_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU1_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU2_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU3_L2_PREFETCH_HITS_IN_STREAM\n"
"PRESET,PAPI_L2_DCA,DERIVED_ADD,PNE_BGP_PU0_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU1_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU2_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU3_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU0_L2_MEMORY_WRITES,PNE_BGP_PU1_L2_MEMORY_WRITES,PNE_BGP_PU2_L2_MEMORY_WRITES,PNE_BGP_PU3_L2_MEMORY_WRITES\n"
"PRESET,PAPI_L2_DCR,DERIVED_ADD,PNE_BGP_PU0_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU1_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU2_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU3_L2_PREFETCHABLE_REQUESTS\n"
"PRESET,PAPI_L2_DCW,DERIVED_ADD,PNE_BGP_PU0_L2_MEMORY_WRITES,PNE_BGP_PU1_L2_MEMORY_WRITES,PNE_BGP_PU2_L2_MEMORY_WRITES,PNE_BGP_PU3_L2_MEMORY_WRITES\n"
"PRESET,PAPI_L3_TCA,DERIVED_ADD,PNE_BGP_L3_M0_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M0_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M0_R2_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M1_R2_BURST_DELIVERED_L2,BGP_L3_M0_W0_DEPOSIT_REQUESTS,BGP_L3_M0_W1_DEPOSIT_REQUESTS,BGP_L3_M1_W0_DEPOSIT_REQUESTS,BGP_L3_M1_W1_DEPOSIT_REQUESTS\n"
"PRESET,PAPI_L3_TCR,DERIVED_ADD,PNE_BGP_L3_M0_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M0_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M0_R2_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M1_R2_BURST_DELIVERED_L2\n"
"PRESET,PAPI_L3_TCW,DERIVED_ADD,PNE_BGP_L3_M0_W0_DEPOSIT_REQUESTS,PNE_BGP_L3_M0_W1_DEPOSIT_REQUESTS,PNE_BGP_L3_M1_W0_DEPOSIT_REQUESTS,PNE_BGP_L3_M1_W1_DEPOSIT_REQUESTS\n"
;