PAPI 7.1.0.0
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intel_wsm_unc_events.h
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1/*
2 * Copyright (c) 2010 Google, Inc
3 * Contributed by Stephane Eranian <eranian@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
16 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
17 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
18 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
19 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * This file is part of libpfm, a performance monitoring support library for
23 * applications on Linux.
24 */
25static pme_nhm_entry_t intel_wsm_unc_pe[]={
26 /*
27 * BEGIN uncore events
28 */
29 { .pme_name = "UNC_CLK_UNHALTED",
30 .pme_desc = "Uncore clockticks.",
31 .pme_code = 0x0000,
32 .pme_flags = PFMLIB_NHM_UNC_FIXED,
33 },
34 { .pme_name = "UNC_DRAM_OPEN",
35 .pme_desc = "DRAM open comamnds issued for read or write",
36 .pme_code = 0x60,
37 .pme_flags = PFMLIB_NHM_UNC,
38 .pme_umasks = {
39 { .pme_uname = "CH0",
40 .pme_udesc = "DRAM Channel 0 open comamnds issued for read or write",
41 .pme_ucode = 0x01,
42 },
43 { .pme_uname = "CH1",
44 .pme_udesc = "DRAM Channel 1 open comamnds issued for read or write",
45 .pme_ucode = 0x02,
46 },
47 { .pme_uname = "CH2",
48 .pme_udesc = "DRAM Channel 2 open comamnds issued for read or write",
49 .pme_ucode = 0x04,
50 },
51 },
52 .pme_numasks = 3
53 },
54 { .pme_name = "UNC_GC_OCCUPANCY",
55 .pme_desc = "Number of queue entries",
56 .pme_code = 0x02,
57 .pme_flags = PFMLIB_NHM_UNC,
58 .pme_umasks = {
59 { .pme_uname = "READ_TRACKER",
60 .pme_udesc = "in the read tracker",
61 .pme_ucode = 0x01,
62 },
63 },
64 .pme_numasks = 1
65 },
66 { .pme_name = "UNC_DRAM_PAGE_CLOSE",
67 .pme_desc = "DRAM page close due to idle timer expiration",
68 .pme_code = 0x61,
69 .pme_flags = PFMLIB_NHM_UNC,
70 .pme_umasks = {
71 { .pme_uname = "CH0",
72 .pme_udesc = "DRAM Channel 0 page close",
73 .pme_ucode = 0x01,
74 },
75 { .pme_uname = "CH1",
76 .pme_udesc = "DRAM Channel 1 page close",
77 .pme_ucode = 0x02,
78 },
79 { .pme_uname = "CH2",
80 .pme_udesc = "DRAM Channel 2 page close",
81 .pme_ucode = 0x04,
82 },
83 },
84 .pme_numasks = 3
85 },
86 { .pme_name = "UNC_DRAM_PAGE_MISS",
87 .pme_desc = "DRAM Channel 0 page miss",
88 .pme_code = 0x62,
89 .pme_flags = PFMLIB_NHM_UNC,
90 .pme_umasks = {
91 { .pme_uname = "CH0",
92 .pme_udesc = "DRAM Channel 0 page miss",
93 .pme_ucode = 0x01,
94 },
95 { .pme_uname = "CH1",
96 .pme_udesc = "DRAM Channel 1 page miss",
97 .pme_ucode = 0x02,
98 },
99 { .pme_uname = "CH2",
100 .pme_udesc = "DRAM Channel 2 page miss",
101 .pme_ucode = 0x04,
102 },
103 },
104 .pme_numasks = 3
105 },
106 { .pme_name = "UNC_DRAM_PRE_ALL",
107 .pme_desc = "DRAM Channel 0 precharge all commands",
108 .pme_code = 0x66,
109 .pme_flags = PFMLIB_NHM_UNC,
110 .pme_umasks = {
111 { .pme_uname = "CH0",
112 .pme_udesc = "DRAM Channel 0 precharge all commands",
113 .pme_ucode = 0x01,
114 },
115 { .pme_uname = "CH1",
116 .pme_udesc = "DRAM Channel 1 precharge all commands",
117 .pme_ucode = 0x02,
118 },
119 { .pme_uname = "CH2",
120 .pme_udesc = "DRAM Channel 2 precharge all commands",
121 .pme_ucode = 0x04,
122 },
123 },
124 .pme_numasks = 3
125 },
126 { .pme_name = "UNC_DRAM_THERMAL_THROTTLED",
127 .pme_desc = "uncore cycles DRAM was throttled due to its temperature being above thermal throttling threshold",
128 .pme_code = 0x0167,
129 .pme_flags = PFMLIB_NHM_UNC,
130 },
131 { .pme_name = "UNC_DRAM_READ_CAS",
132 .pme_desc = "DRAM Channel 0 read CAS commands",
133 .pme_code = 0x63,
134 .pme_flags = PFMLIB_NHM_UNC,
135 .pme_umasks = {
136 { .pme_uname = "CH0",
137 .pme_udesc = "DRAM Channel 0 read CAS commands",
138 .pme_ucode = 0x01,
139 },
140 { .pme_uname = "AUTOPRE_CH0",
141 .pme_udesc = "DRAM Channel 0 read CAS auto page close commands",
142 .pme_ucode = 0x02,
143 },
144 { .pme_uname = "CH1",
145 .pme_udesc = "DRAM Channel 1 read CAS commands",
146 .pme_ucode = 0x04,
147 },
148 { .pme_uname = "AUTOPRE_CH1",
149 .pme_udesc = "DRAM Channel 1 read CAS auto page close commands",
150 .pme_ucode = 0x08,
151 },
152 { .pme_uname = "CH2",
153 .pme_udesc = "DRAM Channel 2 read CAS commands",
154 .pme_ucode = 0x10,
155 },
156 { .pme_uname = "AUTOPRE_CH2",
157 .pme_udesc = "DRAM Channel 2 read CAS auto page close commands",
158 .pme_ucode = 0x20,
159 },
160 },
161 .pme_numasks = 6
162 },
163 { .pme_name = "UNC_DRAM_REFRESH",
164 .pme_desc = "DRAM Channel 0 refresh commands",
165 .pme_code = 0x65,
166 .pme_flags = PFMLIB_NHM_UNC,
167 .pme_umasks = {
168 { .pme_uname = "CH0",
169 .pme_udesc = "DRAM Channel 0 refresh commands",
170 .pme_ucode = 0x01,
171 },
172 { .pme_uname = "CH1",
173 .pme_udesc = "DRAM Channel 1 refresh commands",
174 .pme_ucode = 0x02,
175 },
176 { .pme_uname = "CH2",
177 .pme_udesc = "DRAM Channel 2 refresh commands",
178 .pme_ucode = 0x04,
179 },
180 },
181 .pme_numasks = 3
182 },
183 { .pme_name = "UNC_DRAM_WRITE_CAS",
184 .pme_desc = "DRAM Channel 0 write CAS commands",
185 .pme_code = 0x64,
186 .pme_flags = PFMLIB_NHM_UNC,
187 .pme_umasks = {
188 { .pme_uname = "CH0",
189 .pme_udesc = "DRAM Channel 0 write CAS commands",
190 .pme_ucode = 0x01,
191 },
192 { .pme_uname = "AUTOPRE_CH0",
193 .pme_udesc = "DRAM Channel 0 write CAS auto page close commands",
194 .pme_ucode = 0x02,
195 },
196 { .pme_uname = "CH1",
197 .pme_udesc = "DRAM Channel 1 write CAS commands",
198 .pme_ucode = 0x04,
199 },
200 { .pme_uname = "AUTOPRE_CH1",
201 .pme_udesc = "DRAM Channel 1 write CAS auto page close commands",
202 .pme_ucode = 0x08,
203 },
204 { .pme_uname = "CH2",
205 .pme_udesc = "DRAM Channel 2 write CAS commands",
206 .pme_ucode = 0x10,
207 },
208 { .pme_uname = "AUTOPRE_CH2",
209 .pme_udesc = "DRAM Channel 2 write CAS auto page close commands",
210 .pme_ucode = 0x20,
211 },
212 },
213 .pme_numasks = 6
214 },
215 { .pme_name = "UNC_GQ_ALLOC",
216 .pme_desc = "GQ read tracker requests",
217 .pme_code = 0x03,
218 .pme_flags = PFMLIB_NHM_UNC,
219 .pme_umasks = {
220 { .pme_uname = "READ_TRACKER",
221 .pme_udesc = "GQ read tracker requests",
222 .pme_ucode = 0x01,
223 },
224 { .pme_uname = "RT_LLC_MISS",
225 .pme_udesc = "GQ read tracker LLC misses",
226 .pme_ucode = 0x02,
227 },
228 { .pme_uname = "RT_TO_LLC_RESP",
229 .pme_udesc = "GQ read tracker LLC requests",
230 .pme_ucode = 0x04,
231 },
232 { .pme_uname = "RT_TO_RTID_ACQUIRED",
233 .pme_udesc = "GQ read tracker LLC miss to RTID acquired",
234 .pme_ucode = 0x08,
235 },
236 { .pme_uname = "WT_TO_RTID_ACQUIRED",
237 .pme_udesc = "GQ write tracker LLC miss to RTID acquired",
238 .pme_ucode = 0x10,
239 },
240 { .pme_uname = "WRITE_TRACKER",
241 .pme_udesc = "GQ write tracker LLC misses",
242 .pme_ucode = 0x20,
243 },
244 { .pme_uname = "PEER_PROBE_TRACKER",
245 .pme_udesc = "GQ peer probe tracker requests",
246 .pme_ucode = 0x40,
247 },
248 },
249 .pme_numasks = 7
250 },
251 { .pme_name = "UNC_GQ_CYCLES_FULL",
252 .pme_desc = "Cycles GQ read tracker is full.",
253 .pme_code = 0x00,
254 .pme_flags = PFMLIB_NHM_UNC,
255 .pme_umasks = {
256 { .pme_uname = "READ_TRACKER",
257 .pme_udesc = "Cycles GQ read tracker is full.",
258 .pme_ucode = 0x01,
259 },
260 { .pme_uname = "WRITE_TRACKER",
261 .pme_udesc = "Cycles GQ write tracker is full.",
262 .pme_ucode = 0x02,
263 },
264 { .pme_uname = "PEER_PROBE_TRACKER",
265 .pme_udesc = "Cycles GQ peer probe tracker is full.",
266 .pme_ucode = 0x04,
267 },
268 },
269 .pme_numasks = 3
270 },
271 { .pme_name = "UNC_GQ_CYCLES_NOT_EMPTY",
272 .pme_desc = "Cycles GQ read tracker is busy",
273 .pme_code = 0x01,
274 .pme_flags = PFMLIB_NHM_UNC,
275 .pme_umasks = {
276 { .pme_uname = "READ_TRACKER",
277 .pme_udesc = "Cycles GQ read tracker is busy",
278 .pme_ucode = 0x01,
279 },
280 { .pme_uname = "WRITE_TRACKER",
281 .pme_udesc = "Cycles GQ write tracker is busy",
282 .pme_ucode = 0x02,
283 },
284 { .pme_uname = "PEER_PROBE_TRACKER",
285 .pme_udesc = "Cycles GQ peer probe tracker is busy",
286 .pme_ucode = 0x04,
287 },
288 },
289 .pme_numasks = 3
290 },
291 { .pme_name = "UNC_GQ_DATA_FROM",
292 .pme_desc = "Cycles GQ data is imported",
293 .pme_code = 0x04,
294 .pme_flags = PFMLIB_NHM_UNC,
295 .pme_umasks = {
296 { .pme_uname = "QPI",
297 .pme_udesc = "Cycles GQ data is imported from Quickpath interface",
298 .pme_ucode = 0x01,
299 },
300 { .pme_uname = "QMC",
301 .pme_udesc = "Cycles GQ data is imported from Quickpath memory interface",
302 .pme_ucode = 0x02,
303 },
304 { .pme_uname = "LLC",
305 .pme_udesc = "Cycles GQ data is imported from LLC",
306 .pme_ucode = 0x04,
307 },
308 { .pme_uname = "CORES_02",
309 .pme_udesc = "Cycles GQ data is imported from Cores 0 and 2",
310 .pme_ucode = 0x08,
311 },
312 { .pme_uname = "CORES_13",
313 .pme_udesc = "Cycles GQ data is imported from Cores 1 and 3",
314 .pme_ucode = 0x10,
315 },
316 },
317 .pme_numasks = 5
318 },
319 { .pme_name = "UNC_GQ_DATA_TO",
320 .pme_desc = "Cycles GQ data is exported",
321 .pme_code = 0x05,
322 .pme_flags = PFMLIB_NHM_UNC,
323 .pme_umasks = {
324 { .pme_uname = "QPI_QMC",
325 .pme_udesc = "Cycles GQ data sent to the QPI or QMC",
326 .pme_ucode = 0x01,
327 },
328 { .pme_uname = "LLC",
329 .pme_udesc = "Cycles GQ data sent to LLC",
330 .pme_ucode = 0x02,
331 },
332 { .pme_uname = "CORES",
333 .pme_udesc = "Cycles GQ data sent to cores",
334 .pme_ucode = 0x04,
335 },
336 },
337 .pme_numasks = 3
338 },
339 { .pme_name = "UNC_LLC_HITS",
340 .pme_desc = "Number of LLC read hits",
341 .pme_code = 0x08,
342 .pme_flags = PFMLIB_NHM_UNC,
343 .pme_umasks = {
344 { .pme_uname = "READ",
345 .pme_udesc = "Number of LLC read hits",
346 .pme_ucode = 0x01,
347 },
348 { .pme_uname = "WRITE",
349 .pme_udesc = "Number of LLC write hits",
350 .pme_ucode = 0x02,
351 },
352 { .pme_uname = "PROBE",
353 .pme_udesc = "Number of LLC peer probe hits",
354 .pme_ucode = 0x04,
355 },
356 { .pme_uname = "ANY",
357 .pme_udesc = "Number of LLC hits",
358 .pme_ucode = 0x03,
359 },
360 },
361 .pme_numasks = 4
362 },
363 { .pme_name = "UNC_LLC_LINES_IN",
364 .pme_desc = "LLC lines allocated in M state",
365 .pme_code = 0x0A,
366 .pme_flags = PFMLIB_NHM_UNC,
367 .pme_umasks = {
368 { .pme_uname = "M_STATE",
369 .pme_udesc = "LLC lines allocated in M state",
370 .pme_ucode = 0x01,
371 },
372 { .pme_uname = "E_STATE",
373 .pme_udesc = "LLC lines allocated in E state",
374 .pme_ucode = 0x02,
375 },
376 { .pme_uname = "S_STATE",
377 .pme_udesc = "LLC lines allocated in S state",
378 .pme_ucode = 0x04,
379 },
380 { .pme_uname = "F_STATE",
381 .pme_udesc = "LLC lines allocated in F state",
382 .pme_ucode = 0x08,
383 },
384 { .pme_uname = "ANY",
385 .pme_udesc = "LLC lines allocated",
386 .pme_ucode = 0x0F,
387 },
388 },
389 .pme_numasks = 5
390 },
391 { .pme_name = "UNC_LLC_LINES_OUT",
392 .pme_desc = "LLC lines victimized in M state",
393 .pme_code = 0x0B,
394 .pme_flags = PFMLIB_NHM_UNC,
395 .pme_umasks = {
396 { .pme_uname = "M_STATE",
397 .pme_udesc = "LLC lines victimized in M state",
398 .pme_ucode = 0x01,
399 },
400 { .pme_uname = "E_STATE",
401 .pme_udesc = "LLC lines victimized in E state",
402 .pme_ucode = 0x02,
403 },
404 { .pme_uname = "S_STATE",
405 .pme_udesc = "LLC lines victimized in S state",
406 .pme_ucode = 0x04,
407 },
408 { .pme_uname = "I_STATE",
409 .pme_udesc = "LLC lines victimized in I state",
410 .pme_ucode = 0x08,
411 },
412 { .pme_uname = "F_STATE",
413 .pme_udesc = "LLC lines victimized in F state",
414 .pme_ucode = 0x10,
415 },
416 { .pme_uname = "ANY",
417 .pme_udesc = "LLC lines victimized",
418 .pme_ucode = 0x1F,
419 },
420 },
421 .pme_numasks = 6
422 },
423 { .pme_name = "UNC_LLC_MISS",
424 .pme_desc = "Number of LLC read misses",
425 .pme_code = 0x09,
426 .pme_flags = PFMLIB_NHM_UNC,
427 .pme_umasks = {
428 { .pme_uname = "READ",
429 .pme_udesc = "Number of LLC read misses",
430 .pme_ucode = 0x01,
431 },
432 { .pme_uname = "WRITE",
433 .pme_udesc = "Number of LLC write misses",
434 .pme_ucode = 0x02,
435 },
436 { .pme_uname = "PROBE",
437 .pme_udesc = "Number of LLC peer probe misses",
438 .pme_ucode = 0x04,
439 },
440 { .pme_uname = "ANY",
441 .pme_udesc = "Number of LLC misses",
442 .pme_ucode = 0x03,
443 },
444 },
445 .pme_numasks = 4
446 },
447 { .pme_name = "UNC_QHL_ADDRESS_CONFLICTS",
448 .pme_desc = "QHL 2 way address conflicts",
449 .pme_code = 0x24,
450 .pme_flags = PFMLIB_NHM_UNC,
451 .pme_umasks = {
452 { .pme_uname = "2WAY",
453 .pme_udesc = "QHL 2 way address conflicts",
454 .pme_ucode = 0x02,
455 },
456 { .pme_uname = "3WAY",
457 .pme_udesc = "QHL 3 way address conflicts",
458 .pme_ucode = 0x04,
459 },
460 },
461 .pme_numasks = 2
462 },
463 { .pme_name = "UNC_QHL_CONFLICT_CYCLES",
464 .pme_desc = "QHL IOH Tracker conflict cycles",
465 .pme_code = 0x25,
466 .pme_flags = PFMLIB_NHM_UNC,
467 .pme_umasks = {
468 { .pme_uname = "IOH",
469 .pme_udesc = "QHL IOH Tracker conflict cycles",
470 .pme_ucode = 0x01,
471 },
472 { .pme_uname = "REMOTE",
473 .pme_udesc = "QHL Remote Tracker conflict cycles",
474 .pme_ucode = 0x02,
475 },
476 { .pme_uname = "LOCAL",
477 .pme_udesc = "QHL Local Tracker conflict cycles",
478 .pme_ucode = 0x04,
479 },
480 },
481 .pme_numasks = 3
482 },
483 { .pme_name = "UNC_QHL_CYCLES_FULL",
484 .pme_desc = "Cycles QHL Remote Tracker is full",
485 .pme_code = 0x21,
486 .pme_flags = PFMLIB_NHM_UNC,
487 .pme_umasks = {
488 { .pme_uname = "REMOTE",
489 .pme_udesc = "Cycles QHL Remote Tracker is full",
490 .pme_ucode = 0x02,
491 },
492 { .pme_uname = "LOCAL",
493 .pme_udesc = "Cycles QHL Local Tracker is full",
494 .pme_ucode = 0x04,
495 },
496 { .pme_uname = "IOH",
497 .pme_udesc = "Cycles QHL IOH Tracker is full",
498 .pme_ucode = 0x01,
499 },
500
501 },
502 .pme_numasks = 3
503 },
504 { .pme_name = "UNC_QHL_CYCLES_NOT_EMPTY",
505 .pme_desc = "Cycles QHL Tracker is not empty",
506 .pme_code = 0x22,
507 .pme_flags = PFMLIB_NHM_UNC,
508 .pme_umasks = {
509 { .pme_uname = "IOH",
510 .pme_udesc = "Cycles QHL IOH is busy",
511 .pme_ucode = 0x01,
512 },
513 { .pme_uname = "REMOTE",
514 .pme_udesc = "Cycles QHL Remote Tracker is busy",
515 .pme_ucode = 0x02,
516 },
517 { .pme_uname = "LOCAL",
518 .pme_udesc = "Cycles QHL Local Tracker is busy",
519 .pme_ucode = 0x04,
520 },
521 },
522 .pme_numasks = 3
523 },
524 { .pme_name = "UNC_QHL_FRC_ACK_CNFLTS",
525 .pme_desc = "QHL FrcAckCnflts sent to local home",
526 .pme_code = 0x33,
527 .pme_flags = PFMLIB_NHM_UNC,
528 .pme_umasks = {
529 { .pme_uname = "LOCAL",
530 .pme_udesc = "QHL FrcAckCnflts sent to local home",
531 .pme_ucode = 0x04,
532 },
533 },
534 .pme_numasks = 1
535 },
536 { .pme_name = "UNC_QHL_SLEEPS",
537 .pme_desc = "number of occurrences a request was put to sleep",
538 .pme_code = 0x34,
539 .pme_flags = PFMLIB_NHM_UNC,
540 .pme_umasks = {
541 { .pme_uname = "IOH_ORDER",
542 .pme_udesc = "due to IOH ordering (write after read) conflicts",
543 .pme_ucode = 0x01,
544 },
545 { .pme_uname = "REMOTE_ORDER",
546 .pme_udesc = "due to remote socket ordering (write after read) conflicts",
547 .pme_ucode = 0x02,
548 },
549 { .pme_uname = "LOCAL_ORDER",
550 .pme_udesc = "due to local socket ordering (write after read) conflicts",
551 .pme_ucode = 0x04,
552 },
553 { .pme_uname = "IOH_CONFLICT",
554 .pme_udesc = "due to IOH address conflicts",
555 .pme_ucode = 0x08,
556 },
557 { .pme_uname = "REMOTE_CONFLICT",
558 .pme_udesc = "due to remote socket address conflicts",
559 .pme_ucode = 0x10,
560 },
561 { .pme_uname = "LOCAL_CONFLICT",
562 .pme_udesc = "due to local socket address conflicts",
563 .pme_ucode = 0x20,
564 },
565
566 },
567 .pme_numasks = 6
568 },
569 { .pme_name = "UNC_QHL_OCCUPANCY",
570 .pme_desc = "Cycles QHL Tracker Allocate to Deallocate Read Occupancy",
571 .pme_code = 0x23,
572 .pme_flags = PFMLIB_NHM_UNC,
573 .pme_umasks = {
574 { .pme_uname = "IOH",
575 .pme_udesc = "Cycles QHL IOH Tracker Allocate to Deallocate Read Occupancy",
576 .pme_ucode = 0x01,
577 },
578 { .pme_uname = "REMOTE",
579 .pme_udesc = "Cycles QHL Remote Tracker Allocate to Deallocate Read Occupancy",
580 .pme_ucode = 0x02,
581 },
582 { .pme_uname = "LOCAL",
583 .pme_udesc = "Cycles QHL Local Tracker Allocate to Deallocate Read Occupancy",
584 .pme_ucode = 0x04,
585 },
586 },
587 .pme_numasks = 3
588 },
589 { .pme_name = "UNC_QHL_REQUESTS",
590 .pme_desc = "Quickpath Home Logic local read requests",
591 .pme_code = 0x20,
592 .pme_flags = PFMLIB_NHM_UNC,
593 .pme_umasks = {
594 { .pme_uname = "LOCAL_READS",
595 .pme_udesc = "Quickpath Home Logic local read requests",
596 .pme_ucode = 0x10,
597 },
598 { .pme_uname = "LOCAL_WRITES",
599 .pme_udesc = "Quickpath Home Logic local write requests",
600 .pme_ucode = 0x20,
601 },
602 { .pme_uname = "REMOTE_READS",
603 .pme_udesc = "Quickpath Home Logic remote read requests",
604 .pme_ucode = 0x04,
605 },
606 { .pme_uname = "IOH_READS",
607 .pme_udesc = "Quickpath Home Logic IOH read requests",
608 .pme_ucode = 0x01,
609 },
610 { .pme_uname = "IOH_WRITES",
611 .pme_udesc = "Quickpath Home Logic IOH write requests",
612 .pme_ucode = 0x02,
613 },
614 { .pme_uname = "REMOTE_WRITES",
615 .pme_udesc = "Quickpath Home Logic remote write requests",
616 .pme_ucode = 0x08,
617 },
618 },
619 .pme_numasks = 6
620 },
621 { .pme_name = "UNC_QHL_TO_QMC_BYPASS",
622 .pme_desc = "Number of requests to QMC that bypass QHL",
623 .pme_code = 0x0126,
624 .pme_flags = PFMLIB_NHM_UNC,
625 },
626 { .pme_name = "UNC_QMC_BUSY",
627 .pme_desc = "Cycles QMC busy with a read request",
628 .pme_code = 0x29,
629 .pme_flags = PFMLIB_NHM_UNC,
630 .pme_umasks = {
631 { .pme_uname = "READ_CH0",
632 .pme_udesc = "Cycles QMC channel 0 busy with a read request",
633 .pme_ucode = 0x01,
634 },
635 { .pme_uname = "READ_CH1",
636 .pme_udesc = "Cycles QMC channel 1 busy with a read request",
637 .pme_ucode = 0x02,
638 },
639 { .pme_uname = "READ_CH2",
640 .pme_udesc = "Cycles QMC channel 2 busy with a read request",
641 .pme_ucode = 0x04,
642 },
643 { .pme_uname = "WRITE_CH0",
644 .pme_udesc = "Cycles QMC channel 0 busy with a write request",
645 .pme_ucode = 0x08,
646 },
647 { .pme_uname = "WRITE_CH1",
648 .pme_udesc = "Cycles QMC channel 1 busy with a write request",
649 .pme_ucode = 0x10,
650 },
651 { .pme_uname = "WRITE_CH2",
652 .pme_udesc = "Cycles QMC channel 2 busy with a write request",
653 .pme_ucode = 0x20,
654 },
655 },
656 .pme_numasks = 6
657 },
658 { .pme_name = "UNC_QMC_CANCEL",
659 .pme_desc = "QMC cancels",
660 .pme_code = 0x30,
661 .pme_flags = PFMLIB_NHM_UNC,
662 .pme_umasks = {
663 { .pme_uname = "CH0",
664 .pme_udesc = "QMC channel 0 cancels",
665 .pme_ucode = 0x01,
666 },
667 { .pme_uname = "CH1",
668 .pme_udesc = "QMC channel 1 cancels",
669 .pme_ucode = 0x02,
670 },
671 { .pme_uname = "CH2",
672 .pme_udesc = "QMC channel 2 cancels",
673 .pme_ucode = 0x04,
674 },
675 { .pme_uname = "ANY",
676 .pme_udesc = "QMC cancels",
677 .pme_ucode = 0x07,
678 },
679 },
680 .pme_numasks = 4
681 },
682 { .pme_name = "UNC_QMC_CRITICAL_PRIORITY_READS",
683 .pme_desc = "QMC critical priority read requests",
684 .pme_code = 0x2E,
685 .pme_flags = PFMLIB_NHM_UNC,
686 .pme_umasks = {
687 { .pme_uname = "CH0",
688 .pme_udesc = "QMC channel 0 critical priority read requests",
689 .pme_ucode = 0x01,
690 },
691 { .pme_uname = "CH1",
692 .pme_udesc = "QMC channel 1 critical priority read requests",
693 .pme_ucode = 0x02,
694 },
695 { .pme_uname = "CH2",
696 .pme_udesc = "QMC channel 2 critical priority read requests",
697 .pme_ucode = 0x04,
698 },
699 { .pme_uname = "ANY",
700 .pme_udesc = "QMC critical priority read requests",
701 .pme_ucode = 0x07,
702 },
703 },
704 .pme_numasks = 4
705 },
706 { .pme_name = "UNC_QMC_HIGH_PRIORITY_READS",
707 .pme_desc = "QMC high priority read requests",
708 .pme_code = 0x2D,
709 .pme_flags = PFMLIB_NHM_UNC,
710 .pme_umasks = {
711 { .pme_uname = "CH0",
712 .pme_udesc = "QMC channel 0 high priority read requests",
713 .pme_ucode = 0x01,
714 },
715 { .pme_uname = "CH1",
716 .pme_udesc = "QMC channel 1 high priority read requests",
717 .pme_ucode = 0x02,
718 },
719 { .pme_uname = "CH2",
720 .pme_udesc = "QMC channel 2 high priority read requests",
721 .pme_ucode = 0x04,
722 },
723 { .pme_uname = "ANY",
724 .pme_udesc = "QMC high priority read requests",
725 .pme_ucode = 0x07,
726 },
727 },
728 .pme_numasks = 4
729 },
730 { .pme_name = "UNC_QMC_ISOC_FULL",
731 .pme_desc = "Cycles DRAM full with isochronous (ISOC) read requests",
732 .pme_code = 0x28,
733 .pme_flags = PFMLIB_NHM_UNC,
734 .pme_umasks = {
735 { .pme_uname = "READ_CH0",
736 .pme_udesc = "Cycles DRAM channel 0 full with isochronous read requests",
737 .pme_ucode = 0x01,
738 },
739 { .pme_uname = "READ_CH1",
740 .pme_udesc = "Cycles DRAM channel 1 full with isochronous read requests",
741 .pme_ucode = 0x02,
742 },
743 { .pme_uname = "READ_CH2",
744 .pme_udesc = "Cycles DRAM channel 2 full with isochronous read requests",
745 .pme_ucode = 0x04,
746 },
747 { .pme_uname = "WRITE_CH0",
748 .pme_udesc = "Cycles DRAM channel 0 full with isochronous write requests",
749 .pme_ucode = 0x08,
750 },
751 { .pme_uname = "WRITE_CH1",
752 .pme_udesc = "Cycles DRAM channel 1 full with isochronous write requests",
753 .pme_ucode = 0x10,
754 },
755 { .pme_uname = "WRITE_CH2",
756 .pme_udesc = "Cycles DRAM channel 2 full with isochronous write requests",
757 .pme_ucode = 0x20,
758 },
759 },
760 .pme_numasks = 6
761 },
762 { .pme_name = "UNC_IMC_ISOC_OCCUPANCY",
763 .pme_desc = "IMC isochronous (ISOC) Read Occupancy",
764 .pme_code = 0x2B,
765 .pme_flags = PFMLIB_NHM_UNC,
766 .pme_umasks = {
767 { .pme_uname = "CH0",
768 .pme_udesc = "IMC channel 0 isochronous read request occupancy",
769 .pme_ucode = 0x01,
770 },
771 { .pme_uname = "CH1",
772 .pme_udesc = "IMC channel 1 isochronous read request occupancy",
773 .pme_ucode = 0x02,
774 },
775 { .pme_uname = "CH2",
776 .pme_udesc = "IMC channel 2 isochronous read request occupancy",
777 .pme_ucode = 0x04,
778 },
779 { .pme_uname = "ANY",
780 .pme_udesc = "IMC isochronous read request occupancy",
781 .pme_ucode = 0x07,
782 },
783 },
784 .pme_numasks = 4
785 },
786 { .pme_name = "UNC_QMC_NORMAL_READS",
787 .pme_desc = "QMC normal read requests",
788 .pme_code = 0x2C,
789 .pme_flags = PFMLIB_NHM_UNC,
790 .pme_umasks = {
791 { .pme_uname = "CH0",
792 .pme_udesc = "QMC channel 0 normal read requests",
793 .pme_ucode = 0x01,
794 },
795 { .pme_uname = "CH1",
796 .pme_udesc = "QMC channel 1 normal read requests",
797 .pme_ucode = 0x02,
798 },
799 { .pme_uname = "CH2",
800 .pme_udesc = "QMC channel 2 normal read requests",
801 .pme_ucode = 0x04,
802 },
803 { .pme_uname = "ANY",
804 .pme_udesc = "QMC normal read requests",
805 .pme_ucode = 0x07,
806 },
807 },
808 .pme_numasks = 4
809 },
810 { .pme_name = "UNC_QMC_OCCUPANCY",
811 .pme_desc = "QMC Occupancy",
812 .pme_code = 0x2A,
813 .pme_flags = PFMLIB_NHM_UNC,
814 .pme_umasks = {
815 { .pme_uname = "CH0",
816 .pme_udesc = "IMC channel 0 normal read request occupancy",
817 .pme_ucode = 0x01,
818 },
819 { .pme_uname = "CH1",
820 .pme_udesc = "IMC channel 1 normal read request occupancy",
821 .pme_ucode = 0x02,
822 },
823 { .pme_uname = "CH2",
824 .pme_udesc = "IMC channel 2 normal read request occupancy",
825 .pme_ucode = 0x04,
826 },
827 },
828 .pme_numasks = 3
829 },
830 { .pme_name = "UNC_QMC_PRIORITY_UPDATES",
831 .pme_desc = "QMC priority updates",
832 .pme_code = 0x31,
833 .pme_flags = PFMLIB_NHM_UNC,
834 .pme_umasks = {
835 { .pme_uname = "CH0",
836 .pme_udesc = "QMC channel 0 priority updates",
837 .pme_ucode = 0x01,
838 },
839 { .pme_uname = "CH1",
840 .pme_udesc = "QMC channel 1 priority updates",
841 .pme_ucode = 0x02,
842 },
843 { .pme_uname = "CH2",
844 .pme_udesc = "QMC channel 2 priority updates",
845 .pme_ucode = 0x04,
846 },
847 { .pme_uname = "ANY",
848 .pme_udesc = "QMC priority updates",
849 .pme_ucode = 0x07,
850 },
851 },
852 .pme_numasks = 4
853 },
854 { .pme_name = "UNC_IMC_RETRY",
855 .pme_desc = "Number of IMC DRAM channel retries (retries occur in RAS mode only)",
856 .pme_code = 0x32,
857 .pme_flags = PFMLIB_NHM_UNC,
858 .pme_umasks = {
859 { .pme_uname = "CH0",
860 .pme_udesc = "channel 0",
861 .pme_ucode = 0x01,
862 },
863 { .pme_uname = "CH1",
864 .pme_udesc = "channel 1",
865 .pme_ucode = 0x02,
866 },
867 { .pme_uname = "CH2",
868 .pme_udesc = "channel 2",
869 .pme_ucode = 0x04,
870 },
871 { .pme_uname = "ANY",
872 .pme_udesc = "any channel",
873 .pme_ucode = 0x07,
874 },
875 },
876 .pme_numasks = 4
877 },
878 { .pme_name = "UNC_QMC_WRITES",
879 .pme_desc = "QMC cache line writes",
880 .pme_code = 0x2F,
881 .pme_flags = PFMLIB_NHM_UNC,
882 .pme_umasks = {
883 { .pme_uname = "FULL_CH0",
884 .pme_udesc = "QMC channel 0 full cache line writes",
885 .pme_ucode = 0x01,
886 },
887 { .pme_uname = "FULL_CH1",
888 .pme_udesc = "QMC channel 1 full cache line writes",
889 .pme_ucode = 0x02,
890 },
891 { .pme_uname = "FULL_CH2",
892 .pme_udesc = "QMC channel 2 full cache line writes",
893 .pme_ucode = 0x04,
894 },
895 { .pme_uname = "FULL_ANY",
896 .pme_udesc = "QMC full cache line writes",
897 .pme_ucode = 0x07,
898 },
899 { .pme_uname = "PARTIAL_CH0",
900 .pme_udesc = "QMC channel 0 partial cache line writes",
901 .pme_ucode = 0x08,
902 },
903 { .pme_uname = "PARTIAL_CH1",
904 .pme_udesc = "QMC channel 1 partial cache line writes",
905 .pme_ucode = 0x10,
906 },
907 { .pme_uname = "PARTIAL_CH2",
908 .pme_udesc = "QMC channel 2 partial cache line writes",
909 .pme_ucode = 0x20,
910 },
911 { .pme_uname = "PARTIAL_ANY",
912 .pme_udesc = "QMC partial cache line writes",
913 .pme_ucode = 0x38,
914 },
915 },
916 .pme_numasks = 8
917 },
918 { .pme_name = "UNC_QPI_RX_NO_PPT_CREDIT",
919 .pme_desc = "Link 0 snoop stalls due to no PPT entry",
920 .pme_code = 0x43,
921 .pme_flags = PFMLIB_NHM_UNC,
922 .pme_umasks = {
923 { .pme_uname = "STALLS_LINK_0",
924 .pme_udesc = "Link 0 snoop stalls due to no PPT entry",
925 .pme_ucode = 0x01,
926 },
927 { .pme_uname = "STALLS_LINK_1",
928 .pme_udesc = "Link 1 snoop stalls due to no PPT entry",
929 .pme_ucode = 0x02,
930 },
931 },
932 .pme_numasks = 2
933 },
934 { .pme_name = "UNC_QPI_TX_HEADER",
935 .pme_desc = "Cycles link 0 outbound header busy",
936 .pme_code = 0x42,
937 .pme_flags = PFMLIB_NHM_UNC,
938 .pme_umasks = {
939 { .pme_uname = "BUSY_LINK_0",
940 .pme_udesc = "Cycles link 0 outbound header busy",
941 .pme_ucode = 0x02,
942 },
943 { .pme_uname = "BUSY_LINK_1",
944 .pme_udesc = "Cycles link 1 outbound header busy",
945 .pme_ucode = 0x08,
946 },
947 },
948 .pme_numasks = 2
949 },
950 { .pme_name = "UNC_QPI_TX_STALLED_MULTI_FLIT",
951 .pme_desc = "Cycles QPI outbound stalls",
952 .pme_code = 0x41,
953 .pme_flags = PFMLIB_NHM_UNC,
954 .pme_umasks = {
955 { .pme_uname = "DRS_LINK_0",
956 .pme_udesc = "Cycles QPI outbound link 0 DRS stalled",
957 .pme_ucode = 0x01,
958 },
959 { .pme_uname = "NCB_LINK_0",
960 .pme_udesc = "Cycles QPI outbound link 0 NCB stalled",
961 .pme_ucode = 0x02,
962 },
963 { .pme_uname = "NCS_LINK_0",
964 .pme_udesc = "Cycles QPI outbound link 0 NCS stalled",
965 .pme_ucode = 0x04,
966 },
967 { .pme_uname = "DRS_LINK_1",
968 .pme_udesc = "Cycles QPI outbound link 1 DRS stalled",
969 .pme_ucode = 0x08,
970 },
971 { .pme_uname = "NCB_LINK_1",
972 .pme_udesc = "Cycles QPI outbound link 1 NCB stalled",
973 .pme_ucode = 0x10,
974 },
975 { .pme_uname = "NCS_LINK_1",
976 .pme_udesc = "Cycles QPI outbound link 1 NCS stalled",
977 .pme_ucode = 0x20,
978 },
979 { .pme_uname = "LINK_0",
980 .pme_udesc = "Cycles QPI outbound link 0 multi flit stalled",
981 .pme_ucode = 0x07,
982 },
983 { .pme_uname = "LINK_1",
984 .pme_udesc = "Cycles QPI outbound link 1 multi flit stalled",
985 .pme_ucode = 0x38,
986 },
987 },
988 .pme_numasks = 8
989 },
990 { .pme_name = "UNC_QPI_TX_STALLED_SINGLE_FLIT",
991 .pme_desc = "Cycles QPI outbound link stalls",
992 .pme_code = 0x40,
993 .pme_flags = PFMLIB_NHM_UNC,
994 .pme_umasks = {
995 { .pme_uname = "HOME_LINK_0",
996 .pme_udesc = "Cycles QPI outbound link 0 HOME stalled",
997 .pme_ucode = 0x01,
998 },
999 { .pme_uname = "SNOOP_LINK_0",
1000 .pme_udesc = "Cycles QPI outbound link 0 SNOOP stalled",
1001 .pme_ucode = 0x02,
1002 },
1003 { .pme_uname = "NDR_LINK_0",
1004 .pme_udesc = "Cycles QPI outbound link 0 NDR stalled",
1005 .pme_ucode = 0x04,
1006 },
1007 { .pme_uname = "HOME_LINK_1",
1008 .pme_udesc = "Cycles QPI outbound link 1 HOME stalled",
1009 .pme_ucode = 0x08,
1010 },
1011 { .pme_uname = "SNOOP_LINK_1",
1012 .pme_udesc = "Cycles QPI outbound link 1 SNOOP stalled",
1013 .pme_ucode = 0x10,
1014 },
1015 { .pme_uname = "NDR_LINK_1",
1016 .pme_udesc = "Cycles QPI outbound link 1 NDR stalled",
1017 .pme_ucode = 0x20,
1018 },
1019 { .pme_uname = "LINK_0",
1020 .pme_udesc = "Cycles QPI outbound link 0 single flit stalled",
1021 .pme_ucode = 0x07,
1022 },
1023 { .pme_uname = "LINK_1",
1024 .pme_udesc = "Cycles QPI outbound link 1 single flit stalled",
1025 .pme_ucode = 0x38,
1026 },
1027 },
1028 .pme_numasks = 8
1029 },
1030 { .pme_name = "UNC_SNP_RESP_TO_LOCAL_HOME",
1031 .pme_desc = "Local home snoop response",
1032 .pme_code = 0x06,
1033 .pme_flags = PFMLIB_NHM_UNC,
1034 .pme_umasks = {
1035 { .pme_uname = "I_STATE",
1036 .pme_udesc = "Local home snoop response - LLC does not have cache line",
1037 .pme_ucode = 0x01,
1038 },
1039 { .pme_uname = "S_STATE",
1040 .pme_udesc = "Local home snoop response - LLC has cache line in S state",
1041 .pme_ucode = 0x02,
1042 },
1043 { .pme_uname = "FWD_S_STATE",
1044 .pme_udesc = "Local home snoop response - LLC forwarding cache line in S state.",
1045 .pme_ucode = 0x04,
1046 },
1047 { .pme_uname = "FWD_I_STATE",
1048 .pme_udesc = "Local home snoop response - LLC has forwarded a modified cache line",
1049 .pme_ucode = 0x08,
1050 },
1051 { .pme_uname = "CONFLICT",
1052 .pme_udesc = "Local home conflict snoop response",
1053 .pme_ucode = 0x10,
1054 },
1055 { .pme_uname = "WB",
1056 .pme_udesc = "Local home snoop response - LLC has cache line in the M state",
1057 .pme_ucode = 0x20,
1058 },
1059 },
1060 .pme_numasks = 6
1061 },
1062 { .pme_name = "UNC_SNP_RESP_TO_REMOTE_HOME",
1063 .pme_desc = "Remote home snoop response",
1064 .pme_code = 0x07,
1065 .pme_flags = PFMLIB_NHM_UNC,
1066 .pme_umasks = {
1067 { .pme_uname = "I_STATE",
1068 .pme_udesc = "Remote home snoop response - LLC does not have cache line",
1069 .pme_ucode = 0x01,
1070 },
1071 { .pme_uname = "S_STATE",
1072 .pme_udesc = "Remote home snoop response - LLC has cache line in S state",
1073 .pme_ucode = 0x02,
1074 },
1075 { .pme_uname = "FWD_S_STATE",
1076 .pme_udesc = "Remote home snoop response - LLC forwarding cache line in S state.",
1077 .pme_ucode = 0x04,
1078 },
1079 { .pme_uname = "FWD_I_STATE",
1080 .pme_udesc = "Remote home snoop response - LLC has forwarded a modified cache line",
1081 .pme_ucode = 0x08,
1082 },
1083 { .pme_uname = "CONFLICT",
1084 .pme_udesc = "Remote home conflict snoop response",
1085 .pme_ucode = 0x10,
1086 },
1087 { .pme_uname = "WB",
1088 .pme_udesc = "Remote home snoop response - LLC has cache line in the M state",
1089 .pme_ucode = 0x20,
1090 },
1091 { .pme_uname = "HITM",
1092 .pme_udesc = "Remote home snoop response - LLC HITM",
1093 .pme_ucode = 0x24,
1094 },
1095 },
1096 .pme_numasks = 7
1097 },
1098 { .pme_name = "UNC_THERMAL_THROTTLING_TEMP",
1099 .pme_desc = "uncore cycles that the PCU records core temperature above threshold",
1100 .pme_code = 0x80,
1101 .pme_flags = PFMLIB_NHM_UNC,
1102 .pme_umasks = {
1103 { .pme_uname = "CORE_0",
1104 .pme_udesc = "Core 0",
1105 .pme_ucode = 0x01,
1106 },
1107 { .pme_uname = "CORE_1",
1108 .pme_udesc = "Core 1",
1109 .pme_ucode = 0x02,
1110 },
1111 { .pme_uname = "CORE_2",
1112 .pme_udesc = "Core 2",
1113 .pme_ucode = 0x04,
1114 },
1115 { .pme_uname = "CORE_3",
1116 .pme_udesc = "Core 3",
1117 .pme_ucode = 0x08,
1118 },
1119 },
1120 .pme_numasks = 4
1121 },
1122 { .pme_name = "UNC_THERMAL_THROTTLED_TEMP",
1123 .pme_desc = "uncore cycles that the PCU records that core is in power throttled state due to temperature being above threshold",
1124 .pme_code = 0x81,
1125 .pme_flags = PFMLIB_NHM_UNC,
1126 .pme_umasks = {
1127 { .pme_uname = "CORE_0",
1128 .pme_udesc = "Core 0",
1129 .pme_ucode = 0x01,
1130 },
1131 { .pme_uname = "CORE_1",
1132 .pme_udesc = "Core 1",
1133 .pme_ucode = 0x02,
1134 },
1135 { .pme_uname = "CORE_2",
1136 .pme_udesc = "Core 2",
1137 .pme_ucode = 0x04,
1138 },
1139 { .pme_uname = "CORE_3",
1140 .pme_udesc = "Core 3",
1141 .pme_ucode = 0x08,
1142 },
1143 },
1144 .pme_numasks = 4
1145 },
1146 { .pme_name = "UNC_PROCHOT_ASSERTION",
1147 .pme_desc = "Number of system ssertions of PROCHOT indicating the entire processor has exceeded the thermal limit",
1148 .pme_code = 0x0182,
1149 },
1150 { .pme_name = "UNC_THERMAL_THROTTLING_PROCHOT",
1151 .pme_desc = "uncore cycles that the PCU records that core is in power throttled state due PROCHOT assertions",
1152 .pme_code = 0x83,
1153 .pme_flags = PFMLIB_NHM_UNC,
1154 .pme_umasks = {
1155 { .pme_uname = "CORE_0",
1156 .pme_udesc = "Core 0",
1157 .pme_ucode = 0x01,
1158 },
1159 { .pme_uname = "CORE_1",
1160 .pme_udesc = "Core 1",
1161 .pme_ucode = 0x02,
1162 },
1163 { .pme_uname = "CORE_2",
1164 .pme_udesc = "Core 2",
1165 .pme_ucode = 0x04,
1166 },
1167 { .pme_uname = "CORE_3",
1168 .pme_udesc = "Core 3",
1169 .pme_ucode = 0x08,
1170 },
1171 },
1172 .pme_numasks = 4
1173 },
1174 { .pme_name = "UNC_TURBO_MODE",
1175 .pme_desc = "uncore cycles that a core is operating in turbo mode",
1176 .pme_code = 0x84,
1177 .pme_flags = PFMLIB_NHM_UNC,
1178 .pme_umasks = {
1179 { .pme_uname = "CORE_0",
1180 .pme_udesc = "Core 0",
1181 .pme_ucode = 0x01,
1182 },
1183 { .pme_uname = "CORE_1",
1184 .pme_udesc = "Core 1",
1185 .pme_ucode = 0x02,
1186 },
1187 { .pme_uname = "CORE_2",
1188 .pme_udesc = "Core 2",
1189 .pme_ucode = 0x04,
1190 },
1191 { .pme_uname = "CORE_3",
1192 .pme_udesc = "Core 3",
1193 .pme_ucode = 0x08,
1194 },
1195 },
1196 .pme_numasks = 4
1197 },
1198 { .pme_name = "UNC_CYCLES_UNHALTED_L3_FLL_ENABLE",
1199 .pme_desc = "uncore cycles where at least one core is unhalted and all L3 ways are enabled",
1200 .pme_code = 0x0285,
1201 },
1202 { .pme_name = "UNC_CYCLES_UNHALTED_L3_FLL_DISABLE",
1203 .pme_desc = "uncore cycles where at least one core is unhalted and all L3 ways are disabled",
1204 .pme_code = 0x0186,
1205 },
1206};
1207#define PME_INTEL_WSM_UNC_CYCLE 0
1208#define PME_WSM_UNC_EVENT_COUNT (sizeof(intel_wsm_unc_pe)/sizeof(pme_nhm_entry_t))
intel_wsm_unc_pe
static pme_nhm_entry_t intel_wsm_unc_pe[]
Definition: intel_wsm_unc_events.h:25
PFMLIB_NHM_UNC
#define PFMLIB_NHM_UNC
Definition: pfmlib_intel_nhm_priv.h:61
PFMLIB_NHM_UNC_FIXED
#define PFMLIB_NHM_UNC_FIXED
Definition: pfmlib_intel_nhm_priv.h:62
pme_nhm_entry_t
Definition: pfmlib_intel_nhm_priv.h:39
pme_nhm_entry_t::pme_name
char * pme_name
Definition: pfmlib_intel_nhm_priv.h:40