Origin 2000 Architecture

• Up to 64 nodes

• Each node has 2 R10000's running at 195 Mhz, 1 memory per node

• Each R10000 has on chip 32K instruction, 32K data caches (32/64 Byte line)

• Each R10000 has a 4MB off-chip unified cache (128 Byte line)

• 64(58) entry TLB (each holds 2 pages)

Previous slide

Next slide

Back to first slide

View graphic version