COSC530: Computer Architecture

Fall 2013

Location: Min Kao 524
Tuesdays and Thursdays 8:10-9:25 AM

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Course Description

COSC530 covers the design and analysis of computer architecutres.

It offers an exploration of the central issues in computer architecture: instruction set principles and design, memory hierarchies (cache and main memories, mass storage, virtual memory) and design, pipelining, instruction-level parallelism, bus organization, RISC (Reduced Instruction Set Computers), CISC (Complex Instruction Set Computers), multiprocessors, implementation issues, technology trends, architecture modeling and simulation. Recommended Background: Course work in architecture or machine organization.


Some familiarity with discrete mathematics (CS311 or equivalent). This background should include a working knowledge of counting and probability theory, and simple proofs by mathematical induction.

Required Textbook


Lecture Notes

  1. Chapter 1: Fundamentals of Quantitative Design and Analysis
  2. Chapter 2: Memory Hierarchy Design
  3. Chapter 3: Instruction Level Parallelism and Its Exploitation
  4. Chapter 4: Data-Level Parallelism in Vector, SIMD, and GPU Architectures
  5. Chapter 5: Thread-Level Parallelism
  6. Chapter 6: Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
  7. Final Review




Project presentation schedule for December 3:
  1. 8:10-8:25 IBM Cell Processor (IBM CELL presentation and IBM CELL report)
  2. 8:25-8:40 Cache simulator (cache simulator Python source code)
  3. 8:40-8:55 Intel Core architecture (Intel Core presentation and Intel Core report)
  4. 8:55-9:10 Dalvik VM vs. Java VM (Dalvik report)
  5. 9:10-9:25 Arm Cortex-A* architecture (ARM Cortex presentation and ARM Cortex report)


Piotr Luszczek

TA: Rui Ma



Last updated: December 12, 2013 (Summary of changes)