1st High-Performance Runtime Workshop (HiPeR) 2015

In conjunction with 29th IEEE International Parallel & Distributed Processing Symposium

May 25-29, 2015
Hyderabad, INDIA

Thank you for your interest. Unfortunately, the 2015 instance of this workshop has been cancelled. See you in 2016.

Call for Papers

Submission deadline

January 30, 2015 AoE.

Author notification

February 21, 2015

Final camera ready version due

February 28, 2015


The past decade has seen a dramatic rise in complexity of parallel architectures at all levels: they now include not only high-speed network boards, but also multicore processors, GPU accelerators, and recently manycore accelerators. From a peak performance point of view, such computational power has never before been made available to the software stack. Yet getting the best performance from such complicated execution environments poses an unprecedented set of challenges: synchronizing immensely parallel computations, exploiting heterogeneity in multiple dimensions (e.g., processor elements, interconnect, memory hierarchy), managing critical data transfers, etc. In addressing these problems, runtime systems provide an interesting alternative to traditional programming paradigms, holding out the promise of dealing with the aforementioned complexity by automatically handling most of the aspects related to hardware characteristics and capabilities. But when we address the development and potential usages of such runtimes, what are emerging challenges must we confront? How, for example, can we facilitate the development and optimization process for applications that can take advantage of such a runtime? Given that many other difficult questions of this type are now arising, this workshop is an open platform to present and discuss innovative ideas and solutions related to the design and use of next generation runtime systems.
The aim of this workshop is to provide a forum for researchers to share the latest advances in various aspects of runtime systems, including their relations with application layers on one hand, and with Operating Systems and hardware on the other. Of particular interest is the integration of these components into larger, more complex, software stacks, either ones that are generic in scope, or ones that are related to a particular computational domain.

Topics of interest to the workshop include, but are not limited, to the following:

Papers should present original research and should provide sufficient background material to make them accessible to the broader community. In addition, we solicit papers from practitioners describing problems and experiences building tasks-based software tools for Multicore processors and accelerators.

What/Where to submit

Full paper submissions should not exceed ten (10) single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. Files should be submitted by following the instructions available at the EDAS portal. Authors must ensure that electronically submitted files are formatted in PDF format for 8.5x11 inch paper. The proceedings of this workshop will be submitted for inclusion to the IEEE Xplore Digital Library.