Publications

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Baboulin, M., A. Buttari, J. Dongarra, J. Kurzak, J. Langou, J. Langou, P. Luszczek, and S. Tomov, “Accelerating Scientific Computations with Mixed Precision Algorithms,” Computer Physics Communications, vol. 180, issue 12, pp. 2526-2533, December 2009. DOI: 10.1016/j.cpc.2008.11.005  (402.69 KB)
Baboulin, M., S. Tomov, and J. Dongarra, “Some Issues in Dense Linear Algebra for Multicore and Special Purpose Architectures,” PARA 2008, 9th International Workshop on State-of-the-Art in Scientific and Parallel Computing, Trondheim Norway, May 2008.
Baboulin, M., S. Donfack, J. Dongarra, L. Grigori, A. Remi, and S. Tomov, “A Class of Communication-Avoiding Algorithms for Solving General Dense Linear Systems on CPU/GPU Parallel Machines,” Proc. of the International Conference on Computational Science (ICCS), vol. 9, pp. 17-26, June 2012.
Baboulin, M., J. Demmel, J. Dongarra, S. Tomov, and V. Volkov, Enhancing the Performance of Dense Linear Algebra Solvers on GPUs (in the MAGMA Project) , Austin, TX, The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC08), November 2008.  (5.28 MB)
Baboulin, M., D. Becker, and J. Dongarra, “A parallel tiled solver for dense symmetric indefinite systems on multicore architectures,” University of Tennessee Computer Science Technical Report, no. ICL-UT-11-07, October 2011.  (544.2 KB)
Baboulin, M., J. Dongarra, J. Herrmann, and S. Tomov, “Accelerating Linear System Solutions Using Randomization Techniques,” ACM Transactions on Mathematical Software (also LAWN 246), vol. 39, issue 2, February 2013. DOI: 10.1145/2427023.2427025  (358.79 KB)
Baboulin, M., D. Becker, G. Bosilca, A. Danalis, and J. Dongarra, “An efficient distributed randomized solver with application to large dense linear systems,” ICL Technical Report, no. ICL-UT-12-02, July 2012.  (626.26 KB)
Badia, R. M., M. Beck, F. Bodin, T. Boku, F. Cappello, A. Choudhary, C. Costa, E. Deelman, N. Ferrier, K. Fujisawa, et al., “A Collection of Presentations from the BDEC2 Workshop in Kobe, Japan,” Innovative Computing Laboratory Technical Report, no. ICL-UT-19-09: University of Tennessee, Knoxville, February 2019.  (58.85 MB)
Bai, Z., J. Dongarra, D. Lu, and I. Yamazaki, “Matrix Powers Kernels for Thick-Restart Lanczos with Explicit External Deflation,” International Parallel and Distributed Processing Symposium (IPDPS), Rio de Janeiro, Brazil, IEEE, May 2019.  (480.73 KB)
Bak, S., O. Hernandez, M. Gates, P. Luszczek, and V. Sarkar, “Task-graph scheduling extensions for efficient synchronization and communication,” Proceedings of the ACM International Conference on Supercomputing, pp. 88–101, 2021. DOI: 10.1145/3447818.3461616
Bak, S., C. Bertoni, S. Boehm, R. Budiardja, B. M. Chapman, J. Doerfert, M. Eisenbach, H. Finkel, O. Hernandez, J. Huber, et al., “OpenMP application experiences: Porting to accelerated nodes,” Parallel Computing, vol. 109, March 2022. DOI: 10.1016/j.parco.2021.102856
Balaprakash, P., J. Dongarra, T. Gamblin, M. Hall, J. Hollingsworth, B. Norris, and R. Vuduc, “Autotuning in High-Performance Computing Applications,” Proceedings of the IEEE, vol. 106, issue 11, pp. 2068–2083, November 2018. DOI: 10.1109/JPROC.2018.2841200  (2.5 MB)
Ballard, G., D. Becker, J. Demmel, J. Dongarra, A. Druinsky, I. Peled, O. Schwartz, S. Toledo, and I. Yamazaki, “Communication-Avoiding Symmetric-Indefinite Factorization,” SIAM Journal on Matrix Analysis and Application, vol. 35, issue 4, pp. 1364-1406, July 2014.  (593.18 KB)
Barbut, Q., A. Benoit, T. Herault, Y. Robert, and F. Vivien, “When to checkpoint at the end of a fixed-length reservation?,” Fault Tolerance for HPC at eXtreme Scales (FTXS) Workshop, Denver, United States, August 2023.
Barry, D., A. Danalis, and J. Dongarra, “Automated Data Analysis for Defining Performance Metrics from Raw Hardware Events,” 2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), San Francisco, CA, USA, IEEE, May 2024. DOI: 10.1109/IPDPSW63119.2024.00134
Barry, D., A. Danalis, and H. Jagode, “Effortless Monitoring of Arithmetic Intensity with PAPI’s Counter Analysis Toolkit,” Tools for High Performance Computing 2018/2019: Springer, pp. 195–218, 2021. DOI: 10.1007/978-3-030-66057-4_11
Barry, D., H. Jagode, A. Danalis, and J. Dongarra, “Memory Traffic and Complete Application Profiling with PAPI Multi-Component Measurements,” 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), St. Petersburg, Florida, IEEE, August 2023. DOI: 10.1109/IPDPSW59300.2023.00070  (1.81 MB)
Barry, D., H. Jagode, A. Danalis, and J. Dongarra, Memory Traffic and Complete Application Profiling with PAPI Multi-Component Measurements , St. Petersburg, FL, 28th HIPS Workshop, May 2023.  (3.99 MB)
Barry, D., A. Danalis, and H. Jagode, “Effortless Monitoring of Arithmetic Intensity with PAPI's Counter Analysis Toolkit,” 13th International Workshop on Parallel Tools for High Performance Computing, Dresden, Germany, Springer International Publishing, September 2020.  (738.47 KB)
Bartlett, R., xSDK4ECP: Extreme-scale Scientific Software Development Kit for ECP (Poster) , Houston, TX, 2020 Exascale Computing Project Annual Meeting, February 2020.  (1.54 MB)
Bathie, G., L. Marchal, Y. Robert, and S. Thibault, “Dynamic DAG scheduling under memory constraints for shared-memory platforms,” Int. J. of Networking and Computing, vol. 11, no. 1, pp. 27-49, 2021.  (574.64 KB)
Bathie, G., L. Marchal, Y. Robert, and S. Thibault, “Revisiting Dynamic DAG Scheduling under Memory Constraints for Shared-Memory Platforms,” 22nd Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2020), New Orleans, LA, IEEE Computer Society Press, May 2020.  (317.93 KB)
Bautista-Gomez, L., A. Benoit, S. Di, T. Herault, Y. Robert, and H. Sun, “A survey on checkpointing strategies: Should we always checkpoint à la Young/Daly?,” Future Generation Computer Systems, July 2024. DOI: 10.1016/j.future.2024.07.022
Beams, N., A. Abdelfattah, S. Tomov, J. Dongarra, T. Kolev, and Y. Dudouit, “High-Order Finite Element Method using Standard and Device-Level Batch GEMM on GPUs,” 2020 IEEE/ACM 11th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA): IEEE, November 2020.  (1.3 MB)
Beck, M., T. Moore, P. Luszczek, and A. Danalis, “Interoperable Convergence of Storage, Networking, and Computation,” Advances in Information and Communication: Proceedings of the 2019 Future of Information and Communication Conference (FICC), no. 2: Springer International Publishing, pp. 667-690, 2020.  (1.8 MB)
Beck, M., T. Moore, N. French, E. Kissel, and M. Swany, “Data Logistics: Toolkit and Applications,” 5th EAI International Conference on Smart Objects and Technologies for Social Good, Valencia, Spain, September 2019.  (6.71 MB)
Becker, D., M. Faverge, and J. Dongarra, “Towards a Parallel Tile LDL Factorization for Multicore Architectures,” ICL Technical Report, no. ICL-UT-11-03, Seattle, WA, April 2011.  (425.45 KB)
Beckman, P., J. Dongarra, N. Ferrier, G. Fox, T. Moore, D. Reed, and M. Beck, “Harnessing the Computing Continuum for Programming Our World,” Fog Computing: Theory and Practice: John Wiley & Sons, Inc., 2020. DOI: 10.1002/9781119551713.ch7  (1.4 MB)
Bell, G., D. Bailey, A. H. Karp, J. Dongarra, and K. Walsh, “A Look Back on 30 Years of the Gordon Bell Prize,” International Journal of High Performance Computing and Networking, vol. 31, issue 6, pp. 469–484, 2017.
Benoit, A., Y. Du, T. Herault, L. Marchal, G. Pallez, L. Perotin, Y. Robert, H. Sun, and F. Vivien, “Checkpointing à la Young/Daly: An Overview,” IC3-2022: Proceedings of the 2022 Fourteenth International Conference on Contemporary Computing, Noida, India, ACM Press, pp. 701-710, August 2022. DOI: 10.1145/3549206  (639.77 KB)

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