Publications

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Cao, C., T. Herault, G. Bosilca, and J. Dongarra, “Design for a Soft Error Resilient Dynamic Task-based Runtime,” ICL Technical Report, no. ICL-UT-14-04: University of Tennessee, November 2014.  (2.61 MB)
Cao, C., G. Bosilca, T. Herault, and J. Dongarra, “Design for a Soft Error Resilient Dynamic Task-based Runtime,” 29th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Hyderabad, India, IEEE, May 2015.  (2.31 MB)
Guidry, M., and A. Haidar, On the Design, Autotuning, and Optimization of GPU Kernels for Kinetic Network Simulations Using Fast Explicit Integration and GPU Batched Computation , Oak Ridge, TN, Joint Institute for Computational Sciences Seminar Series, Presentation, September 2015.  (17.25 MB)
Dongarra, J., S. Hammarling, N. J. Higham, S. Relton, P. Valero-Lara, and M. Zounon, “The Design and Performance of Batched BLAS on Modern High-Performance Computing Systems,” International Conference on Computational Science (ICCS 2017), Zürich, Switzerland, Elsevier, June 2017. DOI: DOI:10.1016/j.procs.2017.05.138  (446.14 KB)
Kurzak, J., P. Luszczek, I. Yamazaki, Y. Robert, and J. Dongarra, “Design and Implementation of the PULSAR Programming System for Large Scale Computing,” Supercomputing Frontiers and Innovations, vol. 4, issue 1, 2017. DOI: 10.14529/jsfi170101  (764.96 KB)
Tomov, S., A. Haidar, A. Ayala, D. Schultz, and J. Dongarra, “Design and Implementation for FFT-ECP on Distributed Accelerated Systems,” Innovative Computing Laboratory Technical Report, no. ICL-UT-19-05: University of Tennessee, April 2019.  (3.19 MB)
Benoit, A., V. Le Fèvre, P. Raghavan, Y. Robert, and H. Sun, “Design and Comparison of Resilient Scheduling Heuristics for Parallel Jobs,” 22nd Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2020), New Orleans, LA, IEEE Computer Society Press, May 2020.  (696.21 KB)
Tomov, S., Dense Linear Algebra Solvers for Multicore with GPU Accelerators , Atlanta, GA, International Parallel and Distributed Processing Symposium (IPDPS 2010), April 2010.  (956.68 KB)
Bosilca, G., A. Bouteiller, A. Danalis, T. Herault, P. Luszczek, and J. Dongarra, “Dense Linear Algebra on Distributed Heterogeneous Hardware with a Symbolic DAG Approach,” Scalable Computing and Communications: Theory and Practice: John Wiley & Sons, pp. 699-735, March 2013.  (1.01 MB)
Nicolae, B., J. Li, J. M. Wozniak, G. Bosilca, M. Dorier, and F. Cappello, “DeepFreeze: Towards Scalable Asynchronous Checkpointing of Deep Learning Models,” 20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGRID), Melbourne, VIC, Australia, IEEE, May 2020. DOI: 10.1109/CCGrid49817.2020.00-76  (424.19 KB)
Sid-Lakhdar, W. M., M. Aznaveh, P. Luszczek, and J. Dongarra, “Deep Gaussian process with multitask and transfer learning for performance optimization,” 2022 IEEE High Performance Extreme Computing Conference (HPEC), pp. 1-7, September 2022. DOI: 10.1109/HPEC55821.2022.9926396
Bouteiller, A., G. Bosilca, T. Herault, and J. Dongarra, “Data Movement Interfaces to Support Dataflow Runtimes,” Innovative Computing Laboratory Technical Report, no. ICL-UT-18-03: University of Tennessee, May 2018.  (210.94 KB)
Beck, M., T. Moore, N. French, E. Kissel, and M. Swany, “Data Logistics: Toolkit and Applications,” 5th EAI International Conference on Smart Objects and Technologies for Social Good, Valencia, Spain, September 2019.  (6.71 MB)
Bosilca, G., A. Bouteiller, A. Danalis, T. Herault, P. Lemariner, and J. Dongarra, “DAGuE: A generic distributed DAG Engine for High Performance Computing.,” Parallel Computing, vol. 38, no. 1-2: Elsevier, pp. 27-51, 00 2012.  (830.85 KB)
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Gruetzmacher, T., T. Cojean, G. Flegar, F. Göbel, and H. Anzt, “A Customized Precision Format Based on Mantissa Segmentation for Accelerating Sparse Linear Algebra,” Concurrency and Computation: Practice and Experience, vol. 40319, issue 262, January 2019. DOI: 10.1002/cpe.5418
Danalis, A., H. Jagode, H. Hanumantharayappa, S. Ragate, and J. Dongarra, “Counter Inspection Toolkit: Making Sense out of Hardware Performance Events,” 11th International Workshop on Parallel Tools for High Performance Computing, Dresden, Germany, Cham, Switzerland: Springer, February 2019. DOI: 10.1007/978-3-030-11987-4_2  (216.39 KB)
Aupy, G., A. Benoit, B. Goglin, L. Pottier, and Y. Robert, “Co-Scheduling HPC Workloads on Cache-Partitioned CMP Platforms,” Cluster 2018, Belfast, UK, IEEE Computer Society Press, September 2018.  (423.75 KB)
Aupy, G., A. Benoit, B. Goglin, L. Pottier, and Y. Robert, “Co-Scheduling HPC Workloads on Cache-Partitioned CMP Platforms,” International Journal of High Performance Computing Applications, vol. 33, issue 6, pp. 1221-1239, November 2019. DOI: 10.1177/1094342019846956  (930.28 KB)
Aupy, G., A. Benoit, S. Dai, L. Pottier, P. Raghavan, Y. Robert, and M. Shantharam, “Co-Scheduling Amdhal Applications on Cache-Partitioned Systems,” International Journal of High Performance Computing Applications, vol. 32, issue 1, pp. 123–138, January 2018. DOI: 10.1177/1094342017710806  (672.52 KB)
Benoit, A., A. Cavelan, F. Cappello, P. Raghavan, Y. Robert, and H. Sun, “Coping with Silent and Fail-Stop Errors at Scale by Combining Replication and Checkpointing,” Journal of Parallel and Distributed Computing, vol. 122, pp. 209–225, December 2018. DOI: 10.1016/j.jpdc.2018.08.002  (837 KB)

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