about PAPI L1D access

[fbarisione]

Hello,

This question may sound philosophical but, what is a L1D access to papi? I seems that an L1D access are all the hits and misses in the L1D cache.

I thought that an Access to L1D is a store or load operation triggered by the processor into the memory hierarchy. I'm just guessing, I have never read a formal definition for it.

Going further, if you read this document http://www.cise.ufl.edu/~sb3/files/pmc.pdf page 41, they calculate the L1 Cache Hit Rate as "1 - (L1 Cache misses ) / (load + store)".
which, the access to the Cache (load + store) are the divisor.

Is there any way to relate the access (with its hits and misses) to loads and stores performed?.
Hope you can help me with my dilemma.

[fbarisione]

Going further, if you read this document http://www.cise.ufl.edu/~sb3/files/pmc.pdf page 41, they calculate the L1 Cache Hit Rate as "1 - (L1 Cache misses ) / (load + store)".
which, the access to the Cache (load + store) are the divisor.

[danterpstra]

PAPI passes through definitions of events from the underlying hardware. If you are using PAPI PRESET events, you can use utils/papi_avail -e "EVENTNAME" to get the definition of a given PAPI PRESET event in terms of the native event(s) it is composed of. Similarly, you can then use utils/papi_native_avail -e "NATIVENAME" to get a more detailed definition of that event as described by the vendor.
Bottom line: Although PAPI tries to be consistent in how it defines PRESET events, we're ultimately at the mercy of what the vendor provides. And as always, YMMV.
Hope this helps...