Papi Read Access and L3

Papi Read Access and L3

Postby volvicer » Tue Jun 03, 2014 4:41 pm

Hi I have two questions about PAPI:

1.) What is the difference between a cache read and a cache access? How is the relation to a miss implemented?
2.) I sample PAPI on one socket with 4 cores and each core gather L3 cache misses. Finallay, I sum them up into one value. Is the the right way to do or do I get the same value four times?

Best regards
volvicer
 
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