L3 data cache hits / misses for Nehalem.

[hari_subramoni]

Hi All,

I am using PAPI-3.7.0 with Red Hat Enterprise Linux Server release 5.2 (Tikanga) (Kernel version 2.6.28) for analyzing the various performance counters available with the Intel Nehalem processor. My intent is to get a count of the number of L1, L2, L3 cache hits/misses. I have patched the kernel with perfmon.

When I tried to add events to the event set, I found that only the following events are supported by PAPI - PAPI_L1_DCA, PAPI_L2_DCA, PAPI_L2_DCM, PAPI_L2_TCM. For events like L3 hits/misses etc, I got error -7 (PAPI_ENOEVNT) when I tried to add the event to the event set. When I went through the Intel Architectures Optimization
Reference Manual, I found that there are counters supporting these events. I believe that perfmon (which PAPI uses to get the counter information), also has support for these.

So, is it that this version of PAPI does not support these counters or is it that I'm doing something wrong?

Thanks in advance,
Hari.

PS: I apologize if I posted this to the wrong forum or anything like that.

[Dan Terpstra]

Hari -
You can find which PAPI Preset events are implemented on a given hardware platform by running the /utils/papi_avail utility. That's usually a little easier than trapping a PAPI_ENOEVNT error.
The problem you're running into is that the L3 cache on Nehalem is shared between all cores on a chip, and the events to measure it are monitored by a shared set of counters that can only be accessed in system-wide monitoring mode. Since PAPI is process or thread oriented, these counters are not currently available from PAPI, even though they are supported by perfmon.